Context Navigation

w3_clock_controller.vhd

Last change on this file was 1766, checked in by murphpo, 12 years ago

File size: 24.6 KB

Line
1	------------------------------------------------------------------------------
2	-- w3_clock_controller.vhd - entity/architecture pair
3	------------------------------------------------------------------------------
4	-- IMPORTANT:
5	-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
6	--
7	-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
8	--
9	-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
10	-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
11	-- OF THE USER_LOGIC ENTITY.
12	------------------------------------------------------------------------------
13	--
14	-- ***************************************************************************
15	-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
16	--
17	-- Xilinx, Inc.
18	-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
19	-- AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
20	-- SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
21	-- OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
22	-- APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
23	-- THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
24	-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
25	-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
26	-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
27	-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
28	-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
29	-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30	-- FOR A PARTICULAR PURPOSE.
31	--
32	-- ***************************************************************************
33	--
34	------------------------------------------------------------------------------
35	-- Filename: w3_clock_controller.vhd
36	-- Version: 3.00.a
37	-- Description: Top level design, instantiates library components and user logic.
38	-- Date: Mon May 14 12:21:28 2012 (by Create and Import Peripheral Wizard)
39	-- VHDL Standard: VHDL'93
40	------------------------------------------------------------------------------
41	-- Naming Conventions:
42	-- active low signals: "*_n"
43	-- clock signals: "clk", "clk_div#", "clk_#x"
44	-- reset signals: "rst", "rst_n"
45	-- generics: "C_*"
46	-- user defined types: "*_TYPE"
47	-- state machine next state: "*_ns"
48	-- state machine current state: "*_cs"
49	-- combinatorial signals: "*_com"
50	-- pipelined or register delay signals: "*_d#"
51	-- counter signals: "cnt"
52	-- clock enable signals: "*_ce"
53	-- internal version of output port: "*_i"
54	-- device pins: "*_pin"
55	-- ports: "- Names begin with Uppercase"
56	-- processes: "*_PROCESS"
57	-- component instantiations: "<ENTITY_>I_<#\|FUNC>"
58	------------------------------------------------------------------------------
59
60	library ieee;
61	use ieee.std_logic_1164.all;
62	use ieee.std_logic_arith.all;
63	use ieee.std_logic_unsigned.all;
64
65	library proc_common_v3_00_a;
66	use proc_common_v3_00_a.proc_common_pkg.all;
67	use proc_common_v3_00_a.ipif_pkg.all;
68
69	library plbv46_slave_single_v1_01_a;
70	use plbv46_slave_single_v1_01_a.plbv46_slave_single;
71
72	------------------------------------------------------------------------------
73	-- Entity section
74	------------------------------------------------------------------------------
75	-- Definition of Generics:
76	-- C_BASEADDR -- PLBv46 slave: base address
77	-- C_HIGHADDR -- PLBv46 slave: high address
78	-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
79	-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
80	-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
81	-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
82	-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
83	-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
84	-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
85	-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
86	-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
87	-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
88	-- C_FAMILY -- Xilinx FPGA family
89	--
90	-- Definition of Ports:
91	-- SPLB_Clk -- PLB main bus clock
92	-- SPLB_Rst -- PLB main bus reset
93	-- PLB_ABus -- PLB address bus
94	-- PLB_UABus -- PLB upper address bus
95	-- PLB_PAValid -- PLB primary address valid indicator
96	-- PLB_SAValid -- PLB secondary address valid indicator
97	-- PLB_rdPrim -- PLB secondary to primary read request indicator
98	-- PLB_wrPrim -- PLB secondary to primary write request indicator
99	-- PLB_masterID -- PLB current master identifier
100	-- PLB_abort -- PLB abort request indicator
101	-- PLB_busLock -- PLB bus lock
102	-- PLB_RNW -- PLB read/not write
103	-- PLB_BE -- PLB byte enables
104	-- PLB_MSize -- PLB master data bus size
105	-- PLB_size -- PLB transfer size
106	-- PLB_type -- PLB transfer type
107	-- PLB_lockErr -- PLB lock error indicator
108	-- PLB_wrDBus -- PLB write data bus
109	-- PLB_wrBurst -- PLB burst write transfer indicator
110	-- PLB_rdBurst -- PLB burst read transfer indicator
111	-- PLB_wrPendReq -- PLB write pending bus request indicator
112	-- PLB_rdPendReq -- PLB read pending bus request indicator
113	-- PLB_wrPendPri -- PLB write pending request priority
114	-- PLB_rdPendPri -- PLB read pending request priority
115	-- PLB_reqPri -- PLB current request priority
116	-- PLB_TAttribute -- PLB transfer attribute
117	-- Sl_addrAck -- Slave address acknowledge
118	-- Sl_SSize -- Slave data bus size
119	-- Sl_wait -- Slave wait indicator
120	-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
121	-- Sl_wrDAck -- Slave write data acknowledge
122	-- Sl_wrComp -- Slave write transfer complete indicator
123	-- Sl_wrBTerm -- Slave terminate write burst transfer
124	-- Sl_rdDBus -- Slave read data bus
125	-- Sl_rdWdAddr -- Slave read word address
126	-- Sl_rdDAck -- Slave read data acknowledge
127	-- Sl_rdComp -- Slave read transfer complete indicator
128	-- Sl_rdBTerm -- Slave terminate read burst transfer
129	-- Sl_MBusy -- Slave busy indicator
130	-- Sl_MWrErr -- Slave write error indicator
131	-- Sl_MRdErr -- Slave read error indicator
132	-- Sl_MIRQ -- Slave interrupt indicator
133	------------------------------------------------------------------------------
134
135	entity w3_clock_controller is
136	generic
137	(
138	-- ADD USER GENERICS BELOW THIS LINE ---------------
139	--USER generics added here
140	-- ADD USER GENERICS ABOVE THIS LINE ---------------
141
142	-- DO NOT EDIT BELOW THIS LINE ---------------------
143	-- Bus protocol parameters, do not add to or delete
144	C_BASEADDR : std_logic_vector := X"FFFFFFFF";
145	C_HIGHADDR : std_logic_vector := X"00000000";
146	C_SPLB_AWIDTH : integer := 32;
147	C_SPLB_DWIDTH : integer := 128;
148	C_SPLB_NUM_MASTERS : integer := 8;
149	C_SPLB_MID_WIDTH : integer := 3;
150	C_SPLB_NATIVE_DWIDTH : integer := 32;
151	C_SPLB_P2P : integer := 0;
152	C_SPLB_SUPPORT_BURSTS : integer := 0;
153	C_SPLB_SMALLEST_MASTER : integer := 32;
154	C_SPLB_CLK_PERIOD_PS : integer := 10000;
155	C_INCLUDE_DPHASE_TIMER : integer := 0;
156	C_FAMILY : string := "virtex6"
157	-- DO NOT EDIT ABOVE THIS LINE ---------------------
158	);
159	port
160	(
161	-- ADD USER PORTS BELOW THIS LINE ------------------
162
163	samp_spi_sclk : out std_logic;
164	samp_spi_mosi : out std_logic;
165	samp_spi_miso : in std_logic;
166	samp_spi_cs_n : out std_logic;
167	samp_func : out std_logic;
168
169	rfref_spi_sclk : out std_logic;
170	rfref_spi_mosi : out std_logic;
171	rfref_spi_miso : in std_logic;
172	rfref_spi_cs_n : out std_logic;
173	rfref_func : out std_logic;
174
175	usr_reset0 : out std_logic;
176	usr_reset1 : out std_logic;
177	usr_reset2 : out std_logic;
178	usr_reset3 : out std_logic;
179	usr_status : in std_logic_vector(0 to 31);
180
181	-- ADD USER PORTS ABOVE THIS LINE ------------------
182
183	-- DO NOT EDIT BELOW THIS LINE ---------------------
184	-- Bus protocol ports, do not add to or delete
185	SPLB_Clk : in std_logic;
186	SPLB_Rst : in std_logic;
187	PLB_ABus : in std_logic_vector(0 to 31);
188	PLB_UABus : in std_logic_vector(0 to 31);
189	PLB_PAValid : in std_logic;
190	PLB_SAValid : in std_logic;
191	PLB_rdPrim : in std_logic;
192	PLB_wrPrim : in std_logic;
193	PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
194	PLB_abort : in std_logic;
195	PLB_busLock : in std_logic;
196	PLB_RNW : in std_logic;
197	PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
198	PLB_MSize : in std_logic_vector(0 to 1);
199	PLB_size : in std_logic_vector(0 to 3);
200	PLB_type : in std_logic_vector(0 to 2);
201	PLB_lockErr : in std_logic;
202	PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
203	PLB_wrBurst : in std_logic;
204	PLB_rdBurst : in std_logic;
205	PLB_wrPendReq : in std_logic;
206	PLB_rdPendReq : in std_logic;
207	PLB_wrPendPri : in std_logic_vector(0 to 1);
208	PLB_rdPendPri : in std_logic_vector(0 to 1);
209	PLB_reqPri : in std_logic_vector(0 to 1);
210	PLB_TAttribute : in std_logic_vector(0 to 15);
211	Sl_addrAck : out std_logic;
212	Sl_SSize : out std_logic_vector(0 to 1);
213	Sl_wait : out std_logic;
214	Sl_rearbitrate : out std_logic;
215	Sl_wrDAck : out std_logic;
216	Sl_wrComp : out std_logic;
217	Sl_wrBTerm : out std_logic;
218	Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
219	Sl_rdWdAddr : out std_logic_vector(0 to 3);
220	Sl_rdDAck : out std_logic;
221	Sl_rdComp : out std_logic;
222	Sl_rdBTerm : out std_logic;
223	Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
224	Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
225	Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
226	Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
227	-- DO NOT EDIT ABOVE THIS LINE ---------------------
228	);
229
230	attribute MAX_FANOUT : string;
231	attribute SIGIS : string;
232
233	attribute SIGIS of SPLB_Clk : signal is "CLK";
234	attribute SIGIS of SPLB_Rst : signal is "RST";
235
236	end entity w3_clock_controller;
237
238	------------------------------------------------------------------------------
239	-- Architecture section
240	------------------------------------------------------------------------------
241
242	architecture IMP of w3_clock_controller is
243
244	------------------------------------------
245	-- Array of base/high address pairs for each address range
246	------------------------------------------
247	constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
248	constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
249	constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
250
251	constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
252	(
253	ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
254	ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
255	);
256
257	------------------------------------------
258	-- Array of desired number of chip enables for each address range
259	------------------------------------------
260	constant USER_SLV_NUM_REG : integer := 8;
261	constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
262
263	constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
264	(
265	0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
266	);
267
268	------------------------------------------
269	-- Ratio of bus clock to core clock (for use in dual clock systems)
270	-- 1 = ratio is 1:1
271	-- 2 = ratio is 2:1
272	------------------------------------------
273	constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
274
275	------------------------------------------
276	-- Width of the slave data bus (32 only)
277	------------------------------------------
278	constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
279
280	constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
281
282	------------------------------------------
283	-- Index for CS/CE
284	------------------------------------------
285	constant USER_SLV_CS_INDEX : integer := 0;
286	constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
287
288	constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
289
290	------------------------------------------
291	-- IP Interconnect (IPIC) signal declarations
292	------------------------------------------
293	signal ipif_Bus2IP_Clk : std_logic;
294	signal ipif_Bus2IP_Reset : std_logic;
295	signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
296	signal ipif_IP2Bus_WrAck : std_logic;
297	signal ipif_IP2Bus_RdAck : std_logic;
298	signal ipif_IP2Bus_Error : std_logic;
299	signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
300	signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
301	signal ipif_Bus2IP_RNW : std_logic;
302	signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
303	signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
304	signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
305	signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
306	signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
307	signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
308	signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
309	signal user_IP2Bus_RdAck : std_logic;
310	signal user_IP2Bus_WrAck : std_logic;
311	signal user_IP2Bus_Error : std_logic;
312
313	------------------------------------------
314	-- Component declaration for verilog user logic
315	------------------------------------------
316	component user_logic is
317	generic
318	(
319	-- ADD USER GENERICS BELOW THIS LINE ---------------
320	--USER generics added here
321	-- ADD USER GENERICS ABOVE THIS LINE ---------------
322
323	-- DO NOT EDIT BELOW THIS LINE ---------------------
324	-- Bus protocol parameters, do not add to or delete
325	C_SLV_DWIDTH : integer := 32;
326	C_NUM_REG : integer := 8
327	-- DO NOT EDIT ABOVE THIS LINE ---------------------
328	);
329	port
330	(
331	-- ADD USER PORTS BELOW THIS LINE ------------------
332
333	samp_spi_sclk : out std_logic;
334	samp_spi_mosi : out std_logic;
335	samp_spi_miso : in std_logic;
336	samp_spi_cs_n : out std_logic;
337	samp_func : out std_logic;
338
339	rfref_spi_sclk : out std_logic;
340	rfref_spi_mosi : out std_logic;
341	rfref_spi_miso : in std_logic;
342	rfref_spi_cs_n : out std_logic;
343	rfref_func : out std_logic;
344
345	usr_reset0 : out std_logic;
346	usr_reset1 : out std_logic;
347	usr_reset2 : out std_logic;
348	usr_reset3 : out std_logic;
349	usr_status : in std_logic_vector(0 to 31);
350	-- ADD USER PORTS ABOVE THIS LINE ------------------
351
352	-- DO NOT EDIT BELOW THIS LINE ---------------------
353	-- Bus protocol ports, do not add to or delete
354	Bus2IP_Clk : in std_logic;
355	Bus2IP_Reset : in std_logic;
356	Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
357	Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
358	Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
359	Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
360	IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
361	IP2Bus_RdAck : out std_logic;
362	IP2Bus_WrAck : out std_logic;
363	IP2Bus_Error : out std_logic
364	-- DO NOT EDIT ABOVE THIS LINE ---------------------
365	);
366	end component user_logic;
367
368	begin
369
370	------------------------------------------
371	-- instantiate plbv46_slave_single
372	------------------------------------------
373	PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
374	generic map
375	(
376	C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
377	C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
378	C_SPLB_P2P => C_SPLB_P2P,
379	C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
380	C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
381	C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
382	C_SPLB_AWIDTH => C_SPLB_AWIDTH,
383	C_SPLB_DWIDTH => C_SPLB_DWIDTH,
384	C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
385	C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
386	C_FAMILY => C_FAMILY
387	)
388	port map
389	(
390	SPLB_Clk => SPLB_Clk,
391	SPLB_Rst => SPLB_Rst,
392	PLB_ABus => PLB_ABus,
393	PLB_UABus => PLB_UABus,
394	PLB_PAValid => PLB_PAValid,
395	PLB_SAValid => PLB_SAValid,
396	PLB_rdPrim => PLB_rdPrim,
397	PLB_wrPrim => PLB_wrPrim,
398	PLB_masterID => PLB_masterID,
399	PLB_abort => PLB_abort,
400	PLB_busLock => PLB_busLock,
401	PLB_RNW => PLB_RNW,
402	PLB_BE => PLB_BE,
403	PLB_MSize => PLB_MSize,
404	PLB_size => PLB_size,
405	PLB_type => PLB_type,
406	PLB_lockErr => PLB_lockErr,
407	PLB_wrDBus => PLB_wrDBus,
408	PLB_wrBurst => PLB_wrBurst,
409	PLB_rdBurst => PLB_rdBurst,
410	PLB_wrPendReq => PLB_wrPendReq,
411	PLB_rdPendReq => PLB_rdPendReq,
412	PLB_wrPendPri => PLB_wrPendPri,
413	PLB_rdPendPri => PLB_rdPendPri,
414	PLB_reqPri => PLB_reqPri,
415	PLB_TAttribute => PLB_TAttribute,
416	Sl_addrAck => Sl_addrAck,
417	Sl_SSize => Sl_SSize,
418	Sl_wait => Sl_wait,
419	Sl_rearbitrate => Sl_rearbitrate,
420	Sl_wrDAck => Sl_wrDAck,
421	Sl_wrComp => Sl_wrComp,
422	Sl_wrBTerm => Sl_wrBTerm,
423	Sl_rdDBus => Sl_rdDBus,
424	Sl_rdWdAddr => Sl_rdWdAddr,
425	Sl_rdDAck => Sl_rdDAck,
426	Sl_rdComp => Sl_rdComp,
427	Sl_rdBTerm => Sl_rdBTerm,
428	Sl_MBusy => Sl_MBusy,
429	Sl_MWrErr => Sl_MWrErr,
430	Sl_MRdErr => Sl_MRdErr,
431	Sl_MIRQ => Sl_MIRQ,
432	Bus2IP_Clk => ipif_Bus2IP_Clk,
433	Bus2IP_Reset => ipif_Bus2IP_Reset,
434	IP2Bus_Data => ipif_IP2Bus_Data,
435	IP2Bus_WrAck => ipif_IP2Bus_WrAck,
436	IP2Bus_RdAck => ipif_IP2Bus_RdAck,
437	IP2Bus_Error => ipif_IP2Bus_Error,
438	Bus2IP_Addr => ipif_Bus2IP_Addr,
439	Bus2IP_Data => ipif_Bus2IP_Data,
440	Bus2IP_RNW => ipif_Bus2IP_RNW,
441	Bus2IP_BE => ipif_Bus2IP_BE,
442	Bus2IP_CS => ipif_Bus2IP_CS,
443	Bus2IP_RdCE => ipif_Bus2IP_RdCE,
444	Bus2IP_WrCE => ipif_Bus2IP_WrCE
445	);
446
447	------------------------------------------
448	-- instantiate User Logic
449	------------------------------------------
450	USER_LOGIC_I : component user_logic
451	generic map
452	(
453	-- MAP USER GENERICS BELOW THIS LINE ---------------
454	--USER generics mapped here
455	-- MAP USER GENERICS ABOVE THIS LINE ---------------
456
457	C_SLV_DWIDTH => USER_SLV_DWIDTH,
458	C_NUM_REG => USER_NUM_REG
459	)
460	port map
461	(
462	-- MAP USER PORTS BELOW THIS LINE ------------------
463
464	samp_spi_sclk => samp_spi_sclk,
465	samp_spi_mosi => samp_spi_mosi,
466	samp_spi_miso => samp_spi_miso,
467	samp_spi_cs_n => samp_spi_cs_n,
468	samp_func => samp_func,
469
470	rfref_spi_sclk => rfref_spi_sclk,
471	rfref_spi_mosi => rfref_spi_mosi,
472	rfref_spi_miso => rfref_spi_miso,
473	rfref_spi_cs_n => rfref_spi_cs_n,
474	rfref_func => rfref_func,
475	usr_reset0 => usr_reset0,
476	usr_reset1 => usr_reset1,
477	usr_reset2 => usr_reset2,
478	usr_reset3 => usr_reset3,
479	usr_status => usr_status,
480	-- MAP USER PORTS ABOVE THIS LINE ------------------
481
482	Bus2IP_Clk => ipif_Bus2IP_Clk,
483	Bus2IP_Reset => ipif_Bus2IP_Reset,
484	Bus2IP_Data => ipif_Bus2IP_Data,
485	Bus2IP_BE => ipif_Bus2IP_BE,
486	Bus2IP_RdCE => user_Bus2IP_RdCE,
487	Bus2IP_WrCE => user_Bus2IP_WrCE,
488	IP2Bus_Data => user_IP2Bus_Data,
489	IP2Bus_RdAck => user_IP2Bus_RdAck,
490	IP2Bus_WrAck => user_IP2Bus_WrAck,
491	IP2Bus_Error => user_IP2Bus_Error
492	);
493
494	------------------------------------------
495	-- connect internal signals
496	------------------------------------------
497	ipif_IP2Bus_Data <= user_IP2Bus_Data;
498	ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
499	ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
500	ipif_IP2Bus_Error <= user_IP2Bus_Error;
501
502	user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
503	user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
504
505	end IMP;

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: PlatformSupport/CustomPeripherals/pcores/w3_clock_controller_v3_00_b/hdl/vhdl/w3_clock_controller.vhd

Download in other formats: