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w3_clock_controller.vhd

Last change on this file was 1898, checked in by murphpo, 11 years ago
Updated WARP v3 clock controller core to support selection on/off board sampling clock source at configuration time (before MB boot)
File size: 25.4 KB

Line
1	------------------------------------------------------------------------------
2	-- WARP v3 Clock Controller
3	-- Copyright (c) 2013 Mango Communications
4	-- Based on the peripheral template generated by XPS 13.4
5	-- Original Xilinx copyright statement for peripheral template included below
6	------------------------------------------------------------------------------
7	------------------------------------------------------------------------------
8	-- w3_clock_controller.vhd - entity/architecture pair
9	------------------------------------------------------------------------------
10	-- IMPORTANT:
11	-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
12	--
13	-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
14	--
15	-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
16	-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
17	-- OF THE USER_LOGIC ENTITY.
18	------------------------------------------------------------------------------
19	--
20	-- ***************************************************************************
21	-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
22	--
23	-- Xilinx, Inc.
24	-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
25	-- AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
26	-- SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
27	-- OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
28	-- APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
29	-- THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
30	-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
31	-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
32	-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
33	-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
34	-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
35	-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
36	-- FOR A PARTICULAR PURPOSE.
37	--
38	-- ***************************************************************************
39	--
40	------------------------------------------------------------------------------
41	-- Filename: w3_clock_controller.vhd
42	-- Version: 3.00.a
43	-- Description: Top level design, instantiates library components and user logic.
44	-- Date: Mon May 14 12:21:28 2012 (by Create and Import Peripheral Wizard)
45	-- VHDL Standard: VHDL'93
46	------------------------------------------------------------------------------
47	-- Naming Conventions:
48	-- active low signals: "*_n"
49	-- clock signals: "clk", "clk_div#", "clk_#x"
50	-- reset signals: "rst", "rst_n"
51	-- generics: "C_*"
52	-- user defined types: "*_TYPE"
53	-- state machine next state: "*_ns"
54	-- state machine current state: "*_cs"
55	-- combinatorial signals: "*_com"
56	-- pipelined or register delay signals: "*_d#"
57	-- counter signals: "cnt"
58	-- clock enable signals: "*_ce"
59	-- internal version of output port: "*_i"
60	-- device pins: "*_pin"
61	-- ports: "- Names begin with Uppercase"
62	-- processes: "*_PROCESS"
63	-- component instantiations: "<ENTITY_>I_<#\|FUNC>"
64	------------------------------------------------------------------------------
65
66	library ieee;
67	use ieee.std_logic_1164.all;
68	use ieee.std_logic_arith.all;
69	use ieee.std_logic_unsigned.all;
70
71	library proc_common_v3_00_a;
72	use proc_common_v3_00_a.proc_common_pkg.all;
73	use proc_common_v3_00_a.ipif_pkg.all;
74
75	library plbv46_slave_single_v1_01_a;
76	use plbv46_slave_single_v1_01_a.plbv46_slave_single;
77
78	------------------------------------------------------------------------------
79	-- Entity section
80	------------------------------------------------------------------------------
81	-- Definition of Generics:
82	-- C_BASEADDR -- PLBv46 slave: base address
83	-- C_HIGHADDR -- PLBv46 slave: high address
84	-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
85	-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
86	-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
87	-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
88	-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
89	-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
90	-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
91	-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
92	-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
93	-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
94	-- C_FAMILY -- Xilinx FPGA family
95	--
96	-- Definition of Ports:
97	-- SPLB_Clk -- PLB main bus clock
98	-- SPLB_Rst -- PLB main bus reset
99	-- PLB_ABus -- PLB address bus
100	-- PLB_UABus -- PLB upper address bus
101	-- PLB_PAValid -- PLB primary address valid indicator
102	-- PLB_SAValid -- PLB secondary address valid indicator
103	-- PLB_rdPrim -- PLB secondary to primary read request indicator
104	-- PLB_wrPrim -- PLB secondary to primary write request indicator
105	-- PLB_masterID -- PLB current master identifier
106	-- PLB_abort -- PLB abort request indicator
107	-- PLB_busLock -- PLB bus lock
108	-- PLB_RNW -- PLB read/not write
109	-- PLB_BE -- PLB byte enables
110	-- PLB_MSize -- PLB master data bus size
111	-- PLB_size -- PLB transfer size
112	-- PLB_type -- PLB transfer type
113	-- PLB_lockErr -- PLB lock error indicator
114	-- PLB_wrDBus -- PLB write data bus
115	-- PLB_wrBurst -- PLB burst write transfer indicator
116	-- PLB_rdBurst -- PLB burst read transfer indicator
117	-- PLB_wrPendReq -- PLB write pending bus request indicator
118	-- PLB_rdPendReq -- PLB read pending bus request indicator
119	-- PLB_wrPendPri -- PLB write pending request priority
120	-- PLB_rdPendPri -- PLB read pending request priority
121	-- PLB_reqPri -- PLB current request priority
122	-- PLB_TAttribute -- PLB transfer attribute
123	-- Sl_addrAck -- Slave address acknowledge
124	-- Sl_SSize -- Slave data bus size
125	-- Sl_wait -- Slave wait indicator
126	-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
127	-- Sl_wrDAck -- Slave write data acknowledge
128	-- Sl_wrComp -- Slave write transfer complete indicator
129	-- Sl_wrBTerm -- Slave terminate write burst transfer
130	-- Sl_rdDBus -- Slave read data bus
131	-- Sl_rdWdAddr -- Slave read word address
132	-- Sl_rdDAck -- Slave read data acknowledge
133	-- Sl_rdComp -- Slave read transfer complete indicator
134	-- Sl_rdBTerm -- Slave terminate read burst transfer
135	-- Sl_MBusy -- Slave busy indicator
136	-- Sl_MWrErr -- Slave write error indicator
137	-- Sl_MRdErr -- Slave read error indicator
138	-- Sl_MIRQ -- Slave interrupt indicator
139	------------------------------------------------------------------------------
140
141	entity w3_clock_controller is
142	generic
143	(
144	-- ADD USER GENERICS BELOW THIS LINE ---------------
145	--USER generics added here
146	-- ADD USER GENERICS ABOVE THIS LINE ---------------
147
148	-- DO NOT EDIT BELOW THIS LINE ---------------------
149	-- Bus protocol parameters, do not add to or delete
150	C_BASEADDR : std_logic_vector := X"FFFFFFFF";
151	C_HIGHADDR : std_logic_vector := X"00000000";
152	C_SPLB_AWIDTH : integer := 32;
153	C_SPLB_DWIDTH : integer := 128;
154	C_SPLB_NUM_MASTERS : integer := 8;
155	C_SPLB_MID_WIDTH : integer := 3;
156	C_SPLB_NATIVE_DWIDTH : integer := 32;
157	C_SPLB_P2P : integer := 0;
158	C_SPLB_SUPPORT_BURSTS : integer := 0;
159	C_SPLB_SMALLEST_MASTER : integer := 32;
160	C_SPLB_CLK_PERIOD_PS : integer := 10000;
161	C_INCLUDE_DPHASE_TIMER : integer := 0;
162	C_FAMILY : string := "virtex6"
163	-- DO NOT EDIT ABOVE THIS LINE ---------------------
164	);
165	port
166	(
167	-- ADD USER PORTS BELOW THIS LINE ------------------
168
169	at_boot_clk : in std_logic;
170	at_boot_config_sw : in std_logic_vector(0 to 1);
171	at_boot_clocks_invalid : out std_logic;
172
173	samp_spi_sclk : out std_logic;
174	samp_spi_mosi : out std_logic;
175	samp_spi_miso : in std_logic;
176	samp_spi_cs_n : out std_logic;
177	samp_func : out std_logic;
178
179	rfref_spi_sclk : out std_logic;
180	rfref_spi_mosi : out std_logic;
181	rfref_spi_miso : in std_logic;
182	rfref_spi_cs_n : out std_logic;
183	rfref_func : out std_logic;
184
185	usr_reset0 : out std_logic;
186	usr_reset1 : out std_logic;
187	usr_reset2 : out std_logic;
188	usr_reset3 : out std_logic;
189	usr_status : in std_logic_vector(0 to 31);
190
191	-- ADD USER PORTS ABOVE THIS LINE ------------------
192
193	-- DO NOT EDIT BELOW THIS LINE ---------------------
194	-- Bus protocol ports, do not add to or delete
195	SPLB_Clk : in std_logic;
196	SPLB_Rst : in std_logic;
197	PLB_ABus : in std_logic_vector(0 to 31);
198	PLB_UABus : in std_logic_vector(0 to 31);
199	PLB_PAValid : in std_logic;
200	PLB_SAValid : in std_logic;
201	PLB_rdPrim : in std_logic;
202	PLB_wrPrim : in std_logic;
203	PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
204	PLB_abort : in std_logic;
205	PLB_busLock : in std_logic;
206	PLB_RNW : in std_logic;
207	PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
208	PLB_MSize : in std_logic_vector(0 to 1);
209	PLB_size : in std_logic_vector(0 to 3);
210	PLB_type : in std_logic_vector(0 to 2);
211	PLB_lockErr : in std_logic;
212	PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
213	PLB_wrBurst : in std_logic;
214	PLB_rdBurst : in std_logic;
215	PLB_wrPendReq : in std_logic;
216	PLB_rdPendReq : in std_logic;
217	PLB_wrPendPri : in std_logic_vector(0 to 1);
218	PLB_rdPendPri : in std_logic_vector(0 to 1);
219	PLB_reqPri : in std_logic_vector(0 to 1);
220	PLB_TAttribute : in std_logic_vector(0 to 15);
221	Sl_addrAck : out std_logic;
222	Sl_SSize : out std_logic_vector(0 to 1);
223	Sl_wait : out std_logic;
224	Sl_rearbitrate : out std_logic;
225	Sl_wrDAck : out std_logic;
226	Sl_wrComp : out std_logic;
227	Sl_wrBTerm : out std_logic;
228	Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
229	Sl_rdWdAddr : out std_logic_vector(0 to 3);
230	Sl_rdDAck : out std_logic;
231	Sl_rdComp : out std_logic;
232	Sl_rdBTerm : out std_logic;
233	Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
234	Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
235	Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
236	Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
237	-- DO NOT EDIT ABOVE THIS LINE ---------------------
238	);
239
240	attribute MAX_FANOUT : string;
241	attribute SIGIS : string;
242
243	attribute SIGIS of SPLB_Clk : signal is "CLK";
244	attribute SIGIS of SPLB_Rst : signal is "RST";
245
246	end entity w3_clock_controller;
247
248	------------------------------------------------------------------------------
249	-- Architecture section
250	------------------------------------------------------------------------------
251
252	architecture IMP of w3_clock_controller is
253
254	------------------------------------------
255	-- Array of base/high address pairs for each address range
256	------------------------------------------
257	constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
258	constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
259	constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
260
261	constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
262	(
263	ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
264	ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
265	);
266
267	------------------------------------------
268	-- Array of desired number of chip enables for each address range
269	------------------------------------------
270	constant USER_SLV_NUM_REG : integer := 8;
271	constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
272
273	constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
274	(
275	0 => pad_power2(USER_SLV_NUM_REG) -- number of ce for user logic slave space
276	);
277
278	------------------------------------------
279	-- Ratio of bus clock to core clock (for use in dual clock systems)
280	-- 1 = ratio is 1:1
281	-- 2 = ratio is 2:1
282	------------------------------------------
283	constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
284
285	------------------------------------------
286	-- Width of the slave data bus (32 only)
287	------------------------------------------
288	constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
289
290	constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
291
292	------------------------------------------
293	-- Index for CS/CE
294	------------------------------------------
295	constant USER_SLV_CS_INDEX : integer := 0;
296	constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
297
298	constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
299
300	------------------------------------------
301	-- IP Interconnect (IPIC) signal declarations
302	------------------------------------------
303	signal ipif_Bus2IP_Clk : std_logic;
304	signal ipif_Bus2IP_Reset : std_logic;
305	signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
306	signal ipif_IP2Bus_WrAck : std_logic;
307	signal ipif_IP2Bus_RdAck : std_logic;
308	signal ipif_IP2Bus_Error : std_logic;
309	signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
310	signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
311	signal ipif_Bus2IP_RNW : std_logic;
312	signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
313	signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
314	signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
315	signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
316	signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
317	signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
318	signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
319	signal user_IP2Bus_RdAck : std_logic;
320	signal user_IP2Bus_WrAck : std_logic;
321	signal user_IP2Bus_Error : std_logic;
322
323	------------------------------------------
324	-- Component declaration for verilog user logic
325	------------------------------------------
326	component user_logic is
327	generic
328	(
329	-- ADD USER GENERICS BELOW THIS LINE ---------------
330	--USER generics added here
331	-- ADD USER GENERICS ABOVE THIS LINE ---------------
332
333	-- DO NOT EDIT BELOW THIS LINE ---------------------
334	-- Bus protocol parameters, do not add to or delete
335	C_SLV_DWIDTH : integer := 32;
336	C_NUM_REG : integer := 8
337	-- DO NOT EDIT ABOVE THIS LINE ---------------------
338	);
339	port
340	(
341	-- ADD USER PORTS BELOW THIS LINE ------------------
342
343	at_boot_clk : in std_logic;
344	at_boot_config_sw : in std_logic_vector(0 to 1);
345	at_boot_clocks_invalid : out std_logic;
346
347	samp_spi_sclk : out std_logic;
348	samp_spi_mosi : out std_logic;
349	samp_spi_miso : in std_logic;
350	samp_spi_cs_n : out std_logic;
351	samp_func : out std_logic;
352
353	rfref_spi_sclk : out std_logic;
354	rfref_spi_mosi : out std_logic;
355	rfref_spi_miso : in std_logic;
356	rfref_spi_cs_n : out std_logic;
357	rfref_func : out std_logic;
358
359	usr_reset0 : out std_logic;
360	usr_reset1 : out std_logic;
361	usr_reset2 : out std_logic;
362	usr_reset3 : out std_logic;
363	usr_status : in std_logic_vector(0 to 31);
364	-- ADD USER PORTS ABOVE THIS LINE ------------------
365
366	-- DO NOT EDIT BELOW THIS LINE ---------------------
367	-- Bus protocol ports, do not add to or delete
368	Bus2IP_Clk : in std_logic;
369	Bus2IP_Reset : in std_logic;
370	Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
371	Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
372	Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
373	Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
374	IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
375	IP2Bus_RdAck : out std_logic;
376	IP2Bus_WrAck : out std_logic;
377	IP2Bus_Error : out std_logic
378	-- DO NOT EDIT ABOVE THIS LINE ---------------------
379	);
380	end component user_logic;
381
382	begin
383
384	------------------------------------------
385	-- instantiate plbv46_slave_single
386	------------------------------------------
387	PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single
388	generic map
389	(
390	C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
391	C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
392	C_SPLB_P2P => C_SPLB_P2P,
393	C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
394	C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
395	C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
396	C_SPLB_AWIDTH => C_SPLB_AWIDTH,
397	C_SPLB_DWIDTH => C_SPLB_DWIDTH,
398	C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
399	C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
400	C_FAMILY => C_FAMILY
401	)
402	port map
403	(
404	SPLB_Clk => SPLB_Clk,
405	SPLB_Rst => SPLB_Rst,
406	PLB_ABus => PLB_ABus,
407	PLB_UABus => PLB_UABus,
408	PLB_PAValid => PLB_PAValid,
409	PLB_SAValid => PLB_SAValid,
410	PLB_rdPrim => PLB_rdPrim,
411	PLB_wrPrim => PLB_wrPrim,
412	PLB_masterID => PLB_masterID,
413	PLB_abort => PLB_abort,
414	PLB_busLock => PLB_busLock,
415	PLB_RNW => PLB_RNW,
416	PLB_BE => PLB_BE,
417	PLB_MSize => PLB_MSize,
418	PLB_size => PLB_size,
419	PLB_type => PLB_type,
420	PLB_lockErr => PLB_lockErr,
421	PLB_wrDBus => PLB_wrDBus,
422	PLB_wrBurst => PLB_wrBurst,
423	PLB_rdBurst => PLB_rdBurst,
424	PLB_wrPendReq => PLB_wrPendReq,
425	PLB_rdPendReq => PLB_rdPendReq,
426	PLB_wrPendPri => PLB_wrPendPri,
427	PLB_rdPendPri => PLB_rdPendPri,
428	PLB_reqPri => PLB_reqPri,
429	PLB_TAttribute => PLB_TAttribute,
430	Sl_addrAck => Sl_addrAck,
431	Sl_SSize => Sl_SSize,
432	Sl_wait => Sl_wait,
433	Sl_rearbitrate => Sl_rearbitrate,
434	Sl_wrDAck => Sl_wrDAck,
435	Sl_wrComp => Sl_wrComp,
436	Sl_wrBTerm => Sl_wrBTerm,
437	Sl_rdDBus => Sl_rdDBus,
438	Sl_rdWdAddr => Sl_rdWdAddr,
439	Sl_rdDAck => Sl_rdDAck,
440	Sl_rdComp => Sl_rdComp,
441	Sl_rdBTerm => Sl_rdBTerm,
442	Sl_MBusy => Sl_MBusy,
443	Sl_MWrErr => Sl_MWrErr,
444	Sl_MRdErr => Sl_MRdErr,
445	Sl_MIRQ => Sl_MIRQ,
446	Bus2IP_Clk => ipif_Bus2IP_Clk,
447	Bus2IP_Reset => ipif_Bus2IP_Reset,
448	IP2Bus_Data => ipif_IP2Bus_Data,
449	IP2Bus_WrAck => ipif_IP2Bus_WrAck,
450	IP2Bus_RdAck => ipif_IP2Bus_RdAck,
451	IP2Bus_Error => ipif_IP2Bus_Error,
452	Bus2IP_Addr => ipif_Bus2IP_Addr,
453	Bus2IP_Data => ipif_Bus2IP_Data,
454	Bus2IP_RNW => ipif_Bus2IP_RNW,
455	Bus2IP_BE => ipif_Bus2IP_BE,
456	Bus2IP_CS => ipif_Bus2IP_CS,
457	Bus2IP_RdCE => ipif_Bus2IP_RdCE,
458	Bus2IP_WrCE => ipif_Bus2IP_WrCE
459	);
460
461	------------------------------------------
462	-- instantiate User Logic
463	------------------------------------------
464	USER_LOGIC_I : component user_logic
465	generic map
466	(
467	-- MAP USER GENERICS BELOW THIS LINE ---------------
468	--USER generics mapped here
469	-- MAP USER GENERICS ABOVE THIS LINE ---------------
470
471	C_SLV_DWIDTH => USER_SLV_DWIDTH,
472	C_NUM_REG => USER_NUM_REG
473	)
474	port map
475	(
476	-- MAP USER PORTS BELOW THIS LINE ------------------
477
478	at_boot_clk => at_boot_clk,
479	at_boot_config_sw => at_boot_config_sw,
480	at_boot_clocks_invalid => at_boot_clocks_invalid,
481
482	samp_spi_sclk => samp_spi_sclk,
483	samp_spi_mosi => samp_spi_mosi,
484	samp_spi_miso => samp_spi_miso,
485	samp_spi_cs_n => samp_spi_cs_n,
486	samp_func => samp_func,
487
488	rfref_spi_sclk => rfref_spi_sclk,
489	rfref_spi_mosi => rfref_spi_mosi,
490	rfref_spi_miso => rfref_spi_miso,
491	rfref_spi_cs_n => rfref_spi_cs_n,
492	rfref_func => rfref_func,
493	usr_reset0 => usr_reset0,
494	usr_reset1 => usr_reset1,
495	usr_reset2 => usr_reset2,
496	usr_reset3 => usr_reset3,
497	usr_status => usr_status,
498	-- MAP USER PORTS ABOVE THIS LINE ------------------
499
500	Bus2IP_Clk => ipif_Bus2IP_Clk,
501	Bus2IP_Reset => ipif_Bus2IP_Reset,
502	Bus2IP_Data => ipif_Bus2IP_Data,
503	Bus2IP_BE => ipif_Bus2IP_BE,
504	Bus2IP_RdCE => user_Bus2IP_RdCE,
505	Bus2IP_WrCE => user_Bus2IP_WrCE,
506	IP2Bus_Data => user_IP2Bus_Data,
507	IP2Bus_RdAck => user_IP2Bus_RdAck,
508	IP2Bus_WrAck => user_IP2Bus_WrAck,
509	IP2Bus_Error => user_IP2Bus_Error
510	);
511
512	------------------------------------------
513	-- connect internal signals
514	------------------------------------------
515	ipif_IP2Bus_Data <= user_IP2Bus_Data;
516	ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
517	ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
518	ipif_IP2Bus_Error <= user_IP2Bus_Error;
519
520	user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
521	user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
522
523	end IMP;

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source: PlatformSupport/CustomPeripherals/pcores/w3_clock_controller_v3_01_a/hdl/vhdl/w3_clock_controller.vhd

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