1 | ###################################################################
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2 | ##
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3 | ## Name : w3_iic_eeprom_axi
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4 | ## Desc : Microprocessor Peripheral Description
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5 | ## : Automatically generated by PsfUtility
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6 | ##
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7 | ###################################################################
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8 |
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9 | BEGIN w3_iic_eeprom_axi
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10 |
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11 | ## Peripheral Options
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12 | OPTION IPTYPE = PERIPHERAL
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13 | OPTION IMP_NETLIST = TRUE
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14 | OPTION HDL = MIXED
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15 | OPTION IP_GROUP = MICROBLAZE:USER
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16 | OPTION DESC = W3_IIC_EEPROM_AXI
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17 | OPTION ARCH_SUPPORT_MAP = (virtex6=DEVELOPMENT)
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18 | OPTION USAGE_LEVEL = BASE_USER
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19 |
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20 | OPTION DESC = WARP v3 IIC EEPROM
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21 | OPTION LONG_DESC = "Simple IIC master, based on the OpenCores I2C Master core, for accessing IIC EEPROM on WARP v3 board and Mango FMC modules."
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22 | OPTION IP_GROUP = USER
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23 |
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24 | IO_INTERFACE IO_IF = IIC, IO_TYPE = W3_IIC_EEPROM_V1
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25 |
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26 | ## Bus Interfaces
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27 | BUS_INTERFACE BUS = S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE
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28 |
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29 | ## Generics for VHDL or Parameters for Verilog
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30 | PARAMETER C_S_AXI_DATA_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
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31 | PARAMETER C_S_AXI_ADDR_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
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32 | PARAMETER C_S_AXI_MIN_SIZE = 0x000001ff, DT = std_logic_vector, BUS = S_AXI
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33 | PARAMETER C_USE_WSTRB = 0, DT = INTEGER
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34 | PARAMETER C_DPHASE_TIMEOUT = 8, DT = INTEGER
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35 | PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = S_AXI
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36 | PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = S_AXI
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37 | PARAMETER C_FAMILY = virtex6, DT = STRING
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38 | PARAMETER C_NUM_REG = 1, DT = INTEGER
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39 | PARAMETER C_NUM_MEM = 1, DT = INTEGER
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40 | PARAMETER C_SLV_AWIDTH = 32, DT = INTEGER
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41 | PARAMETER C_SLV_DWIDTH = 32, DT = INTEGER
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42 | PARAMETER C_S_AXI_PROTOCOL = AXI4LITE, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, DT = STRING, BUS = S_AXI
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43 |
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44 | ## Ports
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45 | PORT S_AXI_ACLK = "", DIR = I, SIGIS = CLK, BUS = S_AXI
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46 | PORT S_AXI_ARESETN = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI
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47 | PORT S_AXI_AWADDR = AWADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
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48 | PORT S_AXI_AWVALID = AWVALID, DIR = I, BUS = S_AXI
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49 | PORT S_AXI_WDATA = WDATA, DIR = I, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
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50 | PORT S_AXI_WSTRB = WSTRB, DIR = I, VEC = [((C_S_AXI_DATA_WIDTH/8)-1):0], ENDIAN = LITTLE, BUS = S_AXI
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51 | PORT S_AXI_WVALID = WVALID, DIR = I, BUS = S_AXI
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52 | PORT S_AXI_BREADY = BREADY, DIR = I, BUS = S_AXI
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53 | PORT S_AXI_ARADDR = ARADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
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54 | PORT S_AXI_ARVALID = ARVALID, DIR = I, BUS = S_AXI
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55 | PORT S_AXI_RREADY = RREADY, DIR = I, BUS = S_AXI
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56 | PORT S_AXI_ARREADY = ARREADY, DIR = O, BUS = S_AXI
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57 | PORT S_AXI_RDATA = RDATA, DIR = O, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
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58 | PORT S_AXI_RRESP = RRESP, DIR = O, VEC = [1:0], BUS = S_AXI
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59 | PORT S_AXI_RVALID = RVALID, DIR = O, BUS = S_AXI
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60 | PORT S_AXI_WREADY = WREADY, DIR = O, BUS = S_AXI
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61 | PORT S_AXI_BRESP = BRESP, DIR = O, VEC = [1:0], BUS = S_AXI
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62 | PORT S_AXI_BVALID = BVALID, DIR = O, BUS = S_AXI
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63 | PORT S_AXI_AWREADY = AWREADY, DIR = O, BUS = S_AXI
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64 |
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65 | PORT iic_scl = "", DIR = IO, THREE_STATE = FALSE, IO_IF = IIC, IO_IS = IIC_SCL
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66 | PORT iic_sda = "", DIR = IO, THREE_STATE = FALSE, IO_IF = IIC, IO_IS = IIC_SDA
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67 |
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68 | END
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