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Last change
on this file was
4298,
checked in by murphpo, 9 years ago
|
|
New boot_io_mux core (muxes IIC/UART between clock config core (pre-boot) and AXi peripherals (post-boot)) and eeprom core with explicit I/O/T signals for external IOBUTFs
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File size:
740 bytes
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| Line | |
|---|
| 1 | ############################################################################## |
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| 2 | ## Filename: S:/work/template_projects/ise_14p4_axi/w3_axi_template_test_v0/pcores/w3_iic_eeprom_axi_v1_01_a/data/w3_iic_eeprom_axi_v2_1_0.pao |
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| 3 | ## Description: Peripheral Analysis Order |
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| 4 | ## Date: Sat Feb 23 20:58:52 2013 (by Create and Import Peripheral Wizard) |
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| 5 | ############################################################################## |
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| 6 | |
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| 7 | lib proc_common_v3_00_a all |
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| 8 | lib axi_lite_ipif_v1_01_a all |
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| 9 | lib w3_iic_eeprom_axi_v1_01_a i2c_master_bit_ctrl verilog |
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| 10 | lib w3_iic_eeprom_axi_v1_01_a i2c_master_byte_ctrl verilog |
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| 11 | lib w3_iic_eeprom_axi_v1_01_a user_logic verilog |
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| 12 | lib w3_iic_eeprom_axi_v1_01_a w3_iic_eeprom_axi vhdl |
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