1 | //---------------------------------------------------------------------------- |
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2 | // user_logic.v - module |
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3 | //---------------------------------------------------------------------------- |
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4 | // |
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5 | // *************************************************************************** |
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6 | // ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. ** |
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7 | // ** ** |
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8 | // ** Xilinx, Inc. ** |
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9 | // ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** |
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10 | // ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** |
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11 | // ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** |
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12 | // ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** |
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13 | // ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** |
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14 | // ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** |
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15 | // ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** |
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16 | // ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** |
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17 | // ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** |
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18 | // ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** |
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19 | // ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** |
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20 | // ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** |
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21 | // ** FOR A PARTICULAR PURPOSE. ** |
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22 | // ** ** |
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23 | // *************************************************************************** |
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24 | // |
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25 | //---------------------------------------------------------------------------- |
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26 | // Filename: user_logic.v |
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27 | // Version: 1.00.b |
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28 | // Description: User logic module. |
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29 | // Date: Sat Feb 23 20:58:52 2013 (by Create and Import Peripheral Wizard) |
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30 | // Verilog Standard: Verilog-2001 |
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31 | //---------------------------------------------------------------------------- |
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32 | // Naming Conventions: |
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33 | // active low signals: "*_n" |
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34 | // clock signals: "clk", "clk_div#", "clk_#x" |
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35 | // reset signals: "rst", "rst_n" |
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36 | // generics: "C_*" |
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37 | // user defined types: "*_TYPE" |
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38 | // state machine next state: "*_ns" |
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39 | // state machine current state: "*_cs" |
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40 | // combinatorial signals: "*_com" |
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41 | // pipelined or register delay signals: "*_d#" |
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42 | // counter signals: "*cnt*" |
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43 | // clock enable signals: "*_ce" |
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44 | // internal version of output port: "*_i" |
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45 | // device pins: "*_pin" |
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46 | // ports: "- Names begin with Uppercase" |
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47 | // processes: "*_PROCESS" |
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48 | // component instantiations: "<ENTITY_>I_<#|FUNC>" |
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49 | //---------------------------------------------------------------------------- |
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50 | |
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51 | `uselib lib=unisims_ver |
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52 | `uselib lib=proc_common_v3_00_a |
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53 | |
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54 | module user_logic |
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55 | ( |
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56 | // -- ADD USER PORTS BELOW THIS LINE --------------- |
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57 | iic_sda_I, |
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58 | iic_sda_O, |
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59 | iic_sda_T, |
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60 | |
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61 | iic_scl_I, |
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62 | iic_scl_O, |
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63 | iic_scl_T, |
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64 | // -- ADD USER PORTS ABOVE THIS LINE --------------- |
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65 | |
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66 | // -- DO NOT EDIT BELOW THIS LINE ------------------ |
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67 | // -- Bus protocol ports, do not add to or delete |
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68 | Bus2IP_Clk, // Bus to IP clock |
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69 | Bus2IP_Resetn, // Bus to IP reset |
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70 | Bus2IP_Data, // Bus to IP data bus |
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71 | Bus2IP_BE, // Bus to IP byte enables |
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72 | Bus2IP_RdCE, // Bus to IP read chip enable |
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73 | Bus2IP_WrCE, // Bus to IP write chip enable |
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74 | IP2Bus_Data, // IP to Bus data bus |
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75 | IP2Bus_RdAck, // IP to Bus read transfer acknowledgement |
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76 | IP2Bus_WrAck, // IP to Bus write transfer acknowledgement |
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77 | IP2Bus_Error // IP to Bus error response |
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78 | // -- DO NOT EDIT ABOVE THIS LINE ------------------ |
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79 | ); // user_logic |
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80 | |
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81 | // -- ADD USER PARAMETERS BELOW THIS LINE ------------ |
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82 | // --USER parameters added here |
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83 | // -- ADD USER PARAMETERS ABOVE THIS LINE ------------ |
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84 | |
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85 | // -- DO NOT EDIT BELOW THIS LINE -------------------- |
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86 | // -- Bus protocol parameters, do not add to or delete |
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87 | parameter C_NUM_REG = 8; |
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88 | parameter C_SLV_DWIDTH = 32; |
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89 | // -- DO NOT EDIT ABOVE THIS LINE -------------------- |
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90 | |
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91 | // -- ADD USER PORTS BELOW THIS LINE ----------------- |
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92 | input iic_sda_I; |
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93 | output iic_sda_O; |
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94 | output iic_sda_T; |
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95 | |
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96 | input iic_scl_I; |
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97 | output iic_scl_O; |
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98 | output iic_scl_T; |
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99 | // -- ADD USER PORTS ABOVE THIS LINE ----------------- |
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100 | |
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101 | // -- DO NOT EDIT BELOW THIS LINE -------------------- |
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102 | // -- Bus protocol ports, do not add to or delete |
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103 | input Bus2IP_Clk; |
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104 | input Bus2IP_Resetn; |
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105 | input [C_SLV_DWIDTH-1 : 0] Bus2IP_Data; |
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106 | input [C_SLV_DWIDTH/8-1 : 0] Bus2IP_BE; |
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107 | input [C_NUM_REG-1 : 0] Bus2IP_RdCE; |
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108 | input [C_NUM_REG-1 : 0] Bus2IP_WrCE; |
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109 | output [C_SLV_DWIDTH-1 : 0] IP2Bus_Data; |
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110 | output IP2Bus_RdAck; |
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111 | output IP2Bus_WrAck; |
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112 | output IP2Bus_Error; |
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113 | // -- DO NOT EDIT ABOVE THIS LINE -------------------- |
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114 | |
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115 | //---------------------------------------------------------------------------- |
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116 | // Implementation |
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117 | //---------------------------------------------------------------------------- |
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118 | |
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119 | // --USER nets declarations added here, as needed for user logic |
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120 | |
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121 | // Nets for user logic slave model s/w accessible register example |
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122 | reg [C_SLV_DWIDTH-1 : 0] slv_reg0; |
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123 | reg [C_SLV_DWIDTH-1 : 0] slv_reg1; |
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124 | reg [C_SLV_DWIDTH-1 : 0] slv_reg2; |
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125 | reg [C_SLV_DWIDTH-1 : 0] slv_reg3; |
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126 | reg [C_SLV_DWIDTH-1 : 0] slv_reg4; |
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127 | reg [C_SLV_DWIDTH-1 : 0] slv_reg5; |
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128 | reg [C_SLV_DWIDTH-1 : 0] slv_reg6; |
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129 | reg [C_SLV_DWIDTH-1 : 0] slv_reg7; |
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130 | wire [7 : 0] slv_reg_write_sel; |
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131 | wire [7 : 0] slv_reg_read_sel; |
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132 | reg [C_SLV_DWIDTH-1 : 0] slv_ip2bus_data; |
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133 | wire slv_read_ack; |
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134 | wire slv_write_ack; |
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135 | integer byte_index, bit_index; |
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136 | |
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137 | // USER logic implementation added here |
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138 | |
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139 | // ------------------------------------------------------ |
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140 | // Example code to read/write user logic slave model s/w accessible registers |
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141 | // |
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142 | // Note: |
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143 | // The example code presented here is to show you one way of reading/writing |
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144 | // software accessible registers implemented in the user logic slave model. |
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145 | // Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond |
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146 | // to one software accessible register by the top level template. For example, |
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147 | // if you have four 32 bit software accessible registers in the user logic, |
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148 | // you are basically operating on the following memory mapped registers: |
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149 | // |
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150 | // Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register |
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151 | // "1000" C_BASEADDR + 0x0 |
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152 | // "0100" C_BASEADDR + 0x4 |
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153 | // "0010" C_BASEADDR + 0x8 |
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154 | // "0001" C_BASEADDR + 0xC |
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155 | // |
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156 | // ------------------------------------------------------ |
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157 | |
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158 | assign |
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159 | slv_reg_write_sel = Bus2IP_WrCE[7:0], |
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160 | slv_reg_read_sel = Bus2IP_RdCE[7:0], |
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161 | slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[1] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3] || Bus2IP_WrCE[4] || Bus2IP_WrCE[5] || Bus2IP_WrCE[6] || Bus2IP_WrCE[7], |
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162 | slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3] || Bus2IP_RdCE[4] || Bus2IP_RdCE[5] || Bus2IP_RdCE[6] || Bus2IP_RdCE[7]; |
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163 | |
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164 | // implement slave model register(s) |
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165 | always @( posedge Bus2IP_Clk ) |
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166 | begin |
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167 | |
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168 | if ( Bus2IP_Resetn == 1'b0 ) |
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169 | begin |
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170 | slv_reg0 <= 0; |
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171 | slv_reg1 <= 0; |
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172 | slv_reg2 <= 0; |
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173 | slv_reg3 <= 0; |
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174 | slv_reg4 <= 0; |
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175 | slv_reg5 <= 0; |
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176 | slv_reg6 <= 0; |
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177 | slv_reg7 <= 0; |
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178 | end |
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179 | else |
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180 | case ( slv_reg_write_sel ) |
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181 | 8'b10000000 : |
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182 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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183 | if ( Bus2IP_BE[byte_index] == 1 ) |
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184 | slv_reg0[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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185 | 8'b01000000 : |
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186 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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187 | if ( Bus2IP_BE[byte_index] == 1 ) |
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188 | slv_reg1[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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189 | 8'b00100000 : |
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190 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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191 | if ( Bus2IP_BE[byte_index] == 1 ) |
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192 | slv_reg2[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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193 | 8'b00010000 : |
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194 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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195 | if ( Bus2IP_BE[byte_index] == 1 ) |
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196 | slv_reg3[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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197 | 8'b00001000 : |
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198 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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199 | if ( Bus2IP_BE[byte_index] == 1 ) |
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200 | slv_reg4[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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201 | 8'b00000100 : |
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202 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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203 | if ( Bus2IP_BE[byte_index] == 1 ) |
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204 | slv_reg5[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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205 | 8'b00000010 : |
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206 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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207 | if ( Bus2IP_BE[byte_index] == 1 ) |
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208 | slv_reg6[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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209 | 8'b00000001 : |
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210 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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211 | if ( Bus2IP_BE[byte_index] == 1 ) |
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212 | slv_reg7[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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213 | default : begin |
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214 | slv_reg0 <= slv_reg0; |
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215 | slv_reg1 <= slv_reg1; |
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216 | slv_reg2 <= slv_reg2; |
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217 | slv_reg3 <= slv_reg3; |
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218 | slv_reg4 <= slv_reg4; |
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219 | slv_reg5 <= slv_reg5; |
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220 | slv_reg6 <= slv_reg6; |
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221 | slv_reg7 <= slv_reg7; |
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222 | end |
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223 | endcase |
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224 | |
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225 | end // SLAVE_REG_WRITE_PROC |
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226 | |
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227 | // implement slave model register read mux |
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228 | always @* |
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229 | begin |
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230 | case ( slv_reg_read_sel ) |
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231 | 8'b10000000 : slv_ip2bus_data <= slv_reg0_rd; |
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232 | 8'b01000000 : slv_ip2bus_data <= slv_reg1; |
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233 | 8'b00100000 : slv_ip2bus_data <= slv_reg2; |
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234 | 8'b00010000 : slv_ip2bus_data <= slv_reg3_rd; |
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235 | 8'b00001000 : slv_ip2bus_data <= slv_reg4; |
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236 | 8'b00000100 : slv_ip2bus_data <= slv_reg5; |
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237 | 8'b00000010 : slv_ip2bus_data <= slv_reg6; |
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238 | 8'b00000001 : slv_ip2bus_data <= slv_reg7; |
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239 | default : slv_ip2bus_data <= 0; |
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240 | endcase |
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241 | |
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242 | end // SLAVE_REG_READ_PROC |
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243 | |
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244 | // ------------------------------------------------------------ |
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245 | // Example code to drive IP to Bus signals |
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246 | // ------------------------------------------------------------ |
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247 | |
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248 | assign IP2Bus_Data = (slv_read_ack == 1'b1) ? slv_ip2bus_data : 0 ; |
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249 | assign IP2Bus_WrAck = slv_write_ack; |
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250 | assign IP2Bus_RdAck = slv_read_ack; |
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251 | assign IP2Bus_Error = 0; |
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252 | |
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253 | /* Address map: |
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254 | HDL is coded [MSB:LSB] = [31:0] |
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255 | regX[31] maps to 0x80000000 in C driver |
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256 | regX[0] maps to 0x00000001 in C driver |
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257 | |
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258 | 0: Config/Status[31:0]: |
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259 | [ 7: 0] clk divider (see comments below for interpretation) RW 0x000000FF |
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260 | [8] core enable (1=enabled, 0=disabled) RW 0x00000100 |
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261 | [15: 9] reserved 0x0000FE00 |
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262 | [16] RxACK: received ACK from slave (1=received ACK) RO 0x00010000 |
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263 | [17] Busy: IIC bus busy (1 between Start and Stop events) RO 0x00020000 |
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264 | [18] AL: Arbitration lost (1 when Stop detected but not requested) RO 0x00040000 |
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265 | [19] TIP: Transfer in progress (1 during transfer) RO 0x00080000 |
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266 | [31:20] Reserved |
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267 | |
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268 | 1: Command[31:0]: RW, self-clearing, uses local reg, not normal slv_reg1 |
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269 | [0] Start: generate IIC start 0x01 |
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270 | [1] Stop: generate IIC stop 0x02 |
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271 | [2] Read: execute IIC read 0x04 |
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272 | [3] Write: execute IIC write 0x08 |
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273 | [4] ACK: send ACK for current transaction 0x10 |
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274 | [31:5]: Reserved |
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275 | |
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276 | 2: Transmit[31:0]: {24'b0, txByte[7:0]} RW |
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277 | [ 7: 0]: Tx Byte ([31]=RNW during control word writes) |
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278 | [31: 8]: Reserved |
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279 | |
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280 | 3: Receive[31:0]: {24'b0, rxByte[7:0]} RO |
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281 | [ 7: 0]: Rx Byte |
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282 | [31: 8]: Reserved |
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283 | */ |
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284 | |
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285 | reg [4:0] cmd_reg; |
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286 | wire core_en; |
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287 | wire [15:0] clk_div; |
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288 | wire cmd_start, cmd_stop, cmd_read, cmd_write, cmd_ack; |
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289 | |
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290 | wire [7:0] iic_tx_byte; |
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291 | wire [7:0] iic_rx_byte; |
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292 | |
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293 | wire iic_rx_ack; |
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294 | wire iic_bus_busy; |
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295 | wire iic_al; |
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296 | wire iic_done; |
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297 | wire iic_tip; |
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298 | |
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299 | wire slv_reg1_WE; |
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300 | assign slv_reg1_WE = Bus2IP_WrCE[6]; //WrCE/RdCE[7:0] map to slv_reg[0:7] |
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301 | |
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302 | //Custom command register logic, implements self-clearing bits |
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303 | always @( posedge Bus2IP_Clk ) |
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304 | begin |
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305 | if ( Bus2IP_Resetn == 1'b0 ) |
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306 | cmd_reg <= 5'b0; |
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307 | else if(slv_reg1_WE == 1'b1) |
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308 | cmd_reg[4:0] <= Bus2IP_Data[4:0]; |
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309 | else if(iic_done | iic_al) |
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310 | begin |
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311 | //Clear start, stop, read, write bits on transfer completion or arbitration loss |
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312 | // cmd_reg[4:1] <= 4'b0; |
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313 | // cmd_reg[0] <= cmd_reg[0]; |
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314 | cmd_reg[3:0] <= 4'b0; |
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315 | cmd_reg[4] <= cmd_reg[4]; |
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316 | end |
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317 | else |
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318 | cmd_reg[4:0] <= cmd_reg[4:0]; |
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319 | end |
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320 | |
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321 | assign cmd_start = cmd_reg[0]; //0x01 from driver |
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322 | assign cmd_stop = cmd_reg[1]; //0x02 |
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323 | assign cmd_read = cmd_reg[2]; //0x04 |
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324 | assign cmd_write = cmd_reg[3]; //0x08 |
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325 | assign cmd_ack = cmd_reg[4]; //0x10 |
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326 | |
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327 | assign iic_tip = (cmd_read | cmd_write); //register bits self-clear on transfer completion |
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328 | |
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329 | |
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330 | //Construct 32-bit vectors for read access to mixed RW/RO registers |
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331 | wire [31:0] slv_reg0_rd; |
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332 | wire [31:0] slv_reg3_rd; |
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333 | assign slv_reg0_rd = {12'b0, iic_tip, iic_al, iic_bus_busy, iic_rx_ack, 7'b0, slv_reg0[8], slv_reg0[7:0]}; |
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334 | assign slv_reg3_rd = {24'b0, iic_rx_byte[7:0]}; |
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335 | |
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336 | |
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337 | //IIC master divides down master clock to generate SCL |
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338 | // SCL rate is (sys_clk / (5*clk_div[0:15])) |
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339 | // For 200MHz sys_clk and 100kHz SCL, clk_div = 400 = 0x190 |
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340 | // Interpret user-provided clock divider as bits[6:13] of clk_div |
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341 | assign clk_div[15:0] = {6'b0, slv_reg0[7:0], 2'b0}; |
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342 | assign core_en = slv_reg0[8]; |
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343 | |
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344 | |
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345 | assign iic_tx_byte = slv_reg2[7:0]; |
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346 | |
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347 | wire sda_pad_i, sda_pad_o, sda_pad_oe; |
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348 | wire scl_pad_i, scl_pad_o, scl_pad_oe; |
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349 | |
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350 | i2c_master_byte_ctrl byte_controller ( |
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351 | .clk ( Bus2IP_Clk ), //master clock |
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352 | .rst ( ~Bus2IP_Resetn ), //synchronous reset, active high |
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353 | .nReset ( 1'b1 ), //asynchronous reset, acvtive low |
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354 | .ena ( core_en ), //core enable, active high |
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355 | .clk_cnt ( clk_div ), //master-to-iic clock divider |
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356 | .start ( cmd_start ), //send iic start |
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357 | .stop ( cmd_stop ), //send iic stop |
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358 | .read ( cmd_read ), //perform iic read |
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359 | .write ( cmd_write ), //perform iic write |
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360 | .ack_in ( cmd_ack ), //send iic ack |
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361 | .din ( iic_tx_byte ), //byte to send |
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362 | .cmd_ack ( iic_done ), //xfer is done |
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363 | .ack_out ( iic_rx_ack ), //ack from slave |
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364 | .dout ( iic_rx_byte ), //byte read from slave |
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365 | .i2c_busy ( iic_bus_busy ), |
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366 | .i2c_al ( iic_al ), //arbitration lost output |
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367 | .scl_i ( iic_scl_I ), //iic scl input (pad -> logic) |
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368 | .scl_o ( iic_scl_O ), //iic scl output (logic -> pad) |
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369 | .scl_oen ( iic_scl_T ), //iic scl output enable (0=scl is logic-driven output) |
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370 | .sda_i ( iic_sda_I ), //iic sda input (pad -> logic) |
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371 | .sda_o ( iic_sda_O ), //iic sda output (logic -> pad) |
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372 | .sda_oen ( iic_sda_T ) //iic sda output enable (0=sda is logic-driven output) |
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373 | ); |
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374 | |
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375 | endmodule |
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