| 1 | /***************************************************************** |
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| 2 | * File: w3_iic_eeprom.h |
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| 3 | * Copyright (c) 2012 Mango Communications, all rights reseved |
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| 4 | * Released under the WARP License |
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| 5 | * See http://warp.rice.edu/license for details |
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| 6 | *****************************************************************/ |
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| 7 | |
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| 8 | /// @cond EXCLUDE_FROM_DOCS |
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| 9 | //User code never uses the #define's from this header, so exclude them from the API docs |
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| 10 | |
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| 11 | #ifndef W3_iic_eeprom_H |
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| 12 | #define W3_iic_eeprom_H |
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| 13 | |
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| 14 | #include "xil_io.h" |
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| 15 | |
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| 16 | // Address offset for each slave register; exclude from docs, as users never use these directly |
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| 17 | #define W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET (0x00000000) |
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| 18 | #define W3_IIC_EEPROM_SLV_REG0_OFFSET (W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET + 0x00000000) |
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| 19 | #define W3_IIC_EEPROM_SLV_REG1_OFFSET (W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET + 0x00000004) |
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| 20 | #define W3_IIC_EEPROM_SLV_REG2_OFFSET (W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET + 0x00000008) |
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| 21 | #define W3_IIC_EEPROM_SLV_REG3_OFFSET (W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET + 0x0000000C) |
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| 22 | #define W3_IIC_EEPROM_SLV_REG4_OFFSET (W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET + 0x00000010) |
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| 23 | #define W3_IIC_EEPROM_SLV_REG5_OFFSET (W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET + 0x00000014) |
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| 24 | #define W3_IIC_EEPROM_SLV_REG6_OFFSET (W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET + 0x00000018) |
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| 25 | #define W3_IIC_EEPROM_SLV_REG7_OFFSET (W3_IIC_EEPROM_USER_SLV_SPACE_OFFSET + 0x0000001C) |
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| 26 | |
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| 27 | #define IIC_EEPROM_REG_CONFIG_STATUS W3_IIC_EEPROM_SLV_REG0_OFFSET |
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| 28 | #define IIC_EEPROM_REG_CMD W3_IIC_EEPROM_SLV_REG1_OFFSET |
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| 29 | #define IIC_EEPROM_REG_TX W3_IIC_EEPROM_SLV_REG2_OFFSET |
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| 30 | #define IIC_EEPROM_REG_RX W3_IIC_EEPROM_SLV_REG3_OFFSET |
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| 31 | |
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| 32 | //Masks for config/status register |
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| 33 | #define IIC_EEPROM_REGMASK_CLKDIV 0x000000FF |
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| 34 | #define IIC_EEPROM_REGMASK_COREEN 0x00000100 |
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| 35 | #define IIC_EEPROM_REGMASK_RXACK 0x00010000 |
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| 36 | #define IIC_EEPROM_REGMASK_BUSY 0x00020000 |
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| 37 | #define IIC_EEPROM_REGMASK_AL 0x00040000 |
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| 38 | #define IIC_EEPROM_REGMASK_TIP 0x00080000 |
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| 39 | |
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| 40 | //Masks for command register |
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| 41 | #define IIC_EEPROM_REGMASK_START 0x00000001 |
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| 42 | #define IIC_EEPROM_REGMASK_STOP 0x00000002 |
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| 43 | #define IIC_EEPROM_REGMASK_READ 0x00000004 |
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| 44 | #define IIC_EEPROM_REGMASK_WRITE 0x00000008 |
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| 45 | #define IIC_EEPROM_REGMASK_ACK 0x00000010 |
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| 46 | |
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| 47 | #define IIC_EEPROM_CONTROL_WORD_RD 0xA1 |
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| 48 | #define IIC_EEPROM_CONTROL_WORD_WR 0xA0 |
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| 49 | |
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| 50 | void iic_eeprom_init(u32 ba, u8 clkDiv); |
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| 51 | inline int iic_eeprom_waitForRxACK(u32 ba); |
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| 52 | int iic_eeprom_writeByte(u32 ba, u16 addrToWrite, u8 byteToWrite); |
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| 53 | int iic_eeprom_readByte(u32 ba, u16 addrToRead); |
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| 54 | u32 w3_eeprom_readSerialNum(u32 ba); |
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| 55 | u32 w3_eeprom_read_fpga_dna(u32 ba, int lo_hi); |
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| 56 | void w3_eeprom_readEthAddr(u32 ba, u8 addrSel, u8* addrBuf); |
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| 57 | |
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| 58 | #endif /** W3_iic_eeprom_H */ |
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| 59 | /// @endcond |
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