|
Last change
on this file was
5058,
checked in by welsh, 8 years ago
|
|
EEPROM core v 1.02.a: Added support for multi-cpu environment; Caching of WARP data (SN, FPGA DNA, MAC addresses) on init.
|
|
File size:
740 bytes
|
| Line | |
|---|
| 1 | ############################################################################## |
|---|
| 2 | ## Filename: S:/work/template_projects/ise_14p4_axi/w3_axi_template_test_v0/pcores/w3_iic_eeprom_axi_v1_01_a/data/w3_iic_eeprom_axi_v2_1_0.pao |
|---|
| 3 | ## Description: Peripheral Analysis Order |
|---|
| 4 | ## Date: Sat Feb 23 20:58:52 2013 (by Create and Import Peripheral Wizard) |
|---|
| 5 | ############################################################################## |
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| 6 | |
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| 7 | lib proc_common_v3_00_a all |
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| 8 | lib axi_lite_ipif_v1_01_a all |
|---|
| 9 | lib w3_iic_eeprom_axi_v1_02_a i2c_master_bit_ctrl verilog |
|---|
| 10 | lib w3_iic_eeprom_axi_v1_02_a i2c_master_byte_ctrl verilog |
|---|
| 11 | lib w3_iic_eeprom_axi_v1_02_a user_logic verilog |
|---|
| 12 | lib w3_iic_eeprom_axi_v1_02_a w3_iic_eeprom_axi vhdl |
|---|
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