source: PlatformSupport/CustomPeripherals/pcores/w3_iic_eeprom_v1_00_b/opencores_src/rtl/verilog/i2c_master_defines.v

Last change on this file was 1766, checked in by murphpo, 12 years ago
File size: 2.9 KB
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1/////////////////////////////////////////////////////////////////////
2////                                                             ////
3////  WISHBONE rev.B2 compliant I2C Master controller defines    ////
4////                                                             ////
5////                                                             ////
6////  Author: Richard Herveille                                  ////
7////          richard@asics.ws                                   ////
8////          www.asics.ws                                       ////
9////                                                             ////
10////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
11////                                                             ////
12/////////////////////////////////////////////////////////////////////
13////                                                             ////
14//// Copyright (C) 2001 Richard Herveille                        ////
15////                    richard@asics.ws                         ////
16////                                                             ////
17//// This source file may be used and distributed without        ////
18//// restriction provided that this copyright statement is not   ////
19//// removed from the file and that any derivative work contains ////
20//// the original copyright notice and the associated disclaimer.////
21////                                                             ////
22////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
23//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
24//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
25//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
26//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
27//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
28//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
29//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
30//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
31//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
32//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
33//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
34//// POSSIBILITY OF SUCH DAMAGE.                                 ////
35////                                                             ////
36/////////////////////////////////////////////////////////////////////
37
38//  CVS Log
39//
40//  $Id: i2c_master_defines.v,v 1.3 2001-11-05 11:59:25 rherveille Exp $
41//
42//  $Date: 2001-11-05 11:59:25 $
43//  $Revision: 1.3 $
44//  $Author: rherveille $
45//  $Locker:  $
46//  $State: Exp $
47//
48// Change History:
49//               $Log: not supported by cvs2svn $
50
51
52// I2C registers wishbone addresses
53
54// bitcontroller states
55`define I2C_CMD_NOP   4'b0000
56`define I2C_CMD_START 4'b0001
57`define I2C_CMD_STOP  4'b0010
58`define I2C_CMD_WRITE 4'b0100
59`define I2C_CMD_READ  4'b1000
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