1 | --------------------------------------------------------------------- |
---|
2 | ---- ---- |
---|
3 | ---- WISHBONE revB2 I2C Master Core; bit-controller ---- |
---|
4 | ---- ---- |
---|
5 | ---- ---- |
---|
6 | ---- Author: Richard Herveille ---- |
---|
7 | ---- richard@asics.ws ---- |
---|
8 | ---- www.asics.ws ---- |
---|
9 | ---- ---- |
---|
10 | ---- Downloaded from: http://www.opencores.org/projects/i2c/ ---- |
---|
11 | ---- ---- |
---|
12 | --------------------------------------------------------------------- |
---|
13 | ---- ---- |
---|
14 | ---- Copyright (C) 2000 Richard Herveille ---- |
---|
15 | ---- richard@asics.ws ---- |
---|
16 | ---- ---- |
---|
17 | ---- This source file may be used and distributed without ---- |
---|
18 | ---- restriction provided that this copyright statement is not ---- |
---|
19 | ---- removed from the file and that any derivative work contains ---- |
---|
20 | ---- the original copyright notice and the associated disclaimer.---- |
---|
21 | ---- ---- |
---|
22 | ---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- |
---|
23 | ---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- |
---|
24 | ---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- |
---|
25 | ---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- |
---|
26 | ---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- |
---|
27 | ---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- |
---|
28 | ---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- |
---|
29 | ---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- |
---|
30 | ---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- |
---|
31 | ---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- |
---|
32 | ---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- |
---|
33 | ---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- |
---|
34 | ---- POSSIBILITY OF SUCH DAMAGE. ---- |
---|
35 | ---- ---- |
---|
36 | --------------------------------------------------------------------- |
---|
37 | |
---|
38 | -- CVS Log |
---|
39 | -- |
---|
40 | -- $Id: i2c_master_bit_ctrl.vhd,v 1.17 2009-02-04 20:17:34 rherveille Exp $ |
---|
41 | -- |
---|
42 | -- $Date: 2009-02-04 20:17:34 $ |
---|
43 | -- $Revision: 1.17 $ |
---|
44 | -- $Author: rherveille $ |
---|
45 | -- $Locker: $ |
---|
46 | -- $State: Exp $ |
---|
47 | -- |
---|
48 | -- Change History: |
---|
49 | -- $Log: not supported by cvs2svn $ |
---|
50 | -- Revision 1.16 2009/01/20 20:40:36 rherveille |
---|
51 | -- Fixed type iscl_oen instead of scl_oen |
---|
52 | -- |
---|
53 | -- Revision 1.15 2009/01/20 10:34:51 rherveille |
---|
54 | -- Added SCL clock synchronization logic |
---|
55 | -- Fixed slave_wait signal generation |
---|
56 | -- |
---|
57 | -- Revision 1.14 2006/10/11 12:10:13 rherveille |
---|
58 | -- Added missing semicolons ';' on endif |
---|
59 | -- |
---|
60 | -- Revision 1.13 2006/10/06 10:48:24 rherveille |
---|
61 | -- fixed short scl high pulse after clock stretch |
---|
62 | -- |
---|
63 | -- Revision 1.12 2004/05/07 11:53:31 rherveille |
---|
64 | -- Fixed previous fix :) Made a variable vs signal mistake. |
---|
65 | -- |
---|
66 | -- Revision 1.11 2004/05/07 11:04:00 rherveille |
---|
67 | -- Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. |
---|
68 | -- |
---|
69 | -- Revision 1.10 2004/02/27 07:49:43 rherveille |
---|
70 | -- Fixed a bug in the arbitration-lost signal generation. VHDL version only. |
---|
71 | -- |
---|
72 | -- Revision 1.9 2003/08/12 14:48:37 rherveille |
---|
73 | -- Forgot an 'end if' :-/ |
---|
74 | -- |
---|
75 | -- Revision 1.8 2003/08/09 07:01:13 rherveille |
---|
76 | -- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. |
---|
77 | -- Fixed a potential bug in the byte controller's host-acknowledge generation. |
---|
78 | -- |
---|
79 | -- Revision 1.7 2003/02/05 00:06:02 rherveille |
---|
80 | -- Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. |
---|
81 | -- |
---|
82 | -- Revision 1.6 2003/02/01 02:03:06 rherveille |
---|
83 | -- Fixed a few 'arbitration lost' bugs. VHDL version only. |
---|
84 | -- |
---|
85 | -- Revision 1.5 2002/12/26 16:05:47 rherveille |
---|
86 | -- Core is now a Multimaster I2C controller. |
---|
87 | -- |
---|
88 | -- Revision 1.4 2002/11/30 22:24:37 rherveille |
---|
89 | -- Cleaned up code |
---|
90 | -- |
---|
91 | -- Revision 1.3 2002/10/30 18:09:53 rherveille |
---|
92 | -- Fixed some reported minor start/stop generation timing issuess. |
---|
93 | -- |
---|
94 | -- Revision 1.2 2002/06/15 07:37:04 rherveille |
---|
95 | -- Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. |
---|
96 | -- |
---|
97 | -- Revision 1.1 2001/11/05 12:02:33 rherveille |
---|
98 | -- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. |
---|
99 | -- Code updated, is now up-to-date to doc. rev.0.4. |
---|
100 | -- Added headers. |
---|
101 | -- |
---|
102 | |
---|
103 | |
---|
104 | -- |
---|
105 | ------------------------------------- |
---|
106 | -- Bit controller section |
---|
107 | ------------------------------------ |
---|
108 | -- |
---|
109 | -- Translate simple commands into SCL/SDA transitions |
---|
110 | -- Each command has 5 states, A/B/C/D/idle |
---|
111 | -- |
---|
112 | -- start: SCL ~~~~~~~~~~~~~~\____ |
---|
113 | -- SDA XX/~~~~~~~\______ |
---|
114 | -- x | A | B | C | D | i |
---|
115 | -- |
---|
116 | -- repstart SCL ______/~~~~~~~\___ |
---|
117 | -- SDA __/~~~~~~~\______ |
---|
118 | -- x | A | B | C | D | i |
---|
119 | -- |
---|
120 | -- stop SCL _______/~~~~~~~~~~~ |
---|
121 | -- SDA ==\___________/~~~~~ |
---|
122 | -- x | A | B | C | D | i |
---|
123 | -- |
---|
124 | --- write SCL ______/~~~~~~~\____ |
---|
125 | -- SDA XXX===============XX |
---|
126 | -- x | A | B | C | D | i |
---|
127 | -- |
---|
128 | --- read SCL ______/~~~~~~~\____ |
---|
129 | -- SDA XXXXXXX=XXXXXXXXXXX |
---|
130 | -- x | A | B | C | D | i |
---|
131 | -- |
---|
132 | |
---|
133 | -- Timing: Normal mode Fast mode |
---|
134 | ----------------------------------------------------------------- |
---|
135 | -- Fscl 100KHz 400KHz |
---|
136 | -- Th_scl 4.0us 0.6us High period of SCL |
---|
137 | -- Tl_scl 4.7us 1.3us Low period of SCL |
---|
138 | -- Tsu:sta 4.7us 0.6us setup time for a repeated start condition |
---|
139 | -- Tsu:sto 4.0us 0.6us setup time for a stop conditon |
---|
140 | -- Tbuf 4.7us 1.3us Bus free time between a stop and start condition |
---|
141 | -- |
---|
142 | |
---|
143 | library ieee; |
---|
144 | use ieee.std_logic_1164.all; |
---|
145 | use ieee.numeric_std.all; |
---|
146 | |
---|
147 | entity i2c_master_bit_ctrl is |
---|
148 | port ( |
---|
149 | clk : in std_logic; |
---|
150 | rst : in std_logic; |
---|
151 | nReset : in std_logic; |
---|
152 | ena : in std_logic; -- core enable signal |
---|
153 | |
---|
154 | clk_cnt : in unsigned(15 downto 0); -- clock prescale value |
---|
155 | |
---|
156 | cmd : in std_logic_vector(3 downto 0); |
---|
157 | cmd_ack : out std_logic; -- command completed |
---|
158 | busy : out std_logic; -- i2c bus busy |
---|
159 | al : out std_logic; -- arbitration lost |
---|
160 | |
---|
161 | din : in std_logic; |
---|
162 | dout : out std_logic; |
---|
163 | |
---|
164 | -- i2c lines |
---|
165 | scl_i : in std_logic; -- i2c clock line input |
---|
166 | scl_o : out std_logic; -- i2c clock line output |
---|
167 | scl_oen : out std_logic; -- i2c clock line output enable, active low |
---|
168 | sda_i : in std_logic; -- i2c data line input |
---|
169 | sda_o : out std_logic; -- i2c data line output |
---|
170 | sda_oen : out std_logic -- i2c data line output enable, active low |
---|
171 | ); |
---|
172 | end entity i2c_master_bit_ctrl; |
---|
173 | |
---|
174 | architecture structural of i2c_master_bit_ctrl is |
---|
175 | constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000"; |
---|
176 | constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001"; |
---|
177 | constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010"; |
---|
178 | constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100"; |
---|
179 | constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000"; |
---|
180 | |
---|
181 | type states is (idle, start_a, start_b, start_c, start_d, start_e, |
---|
182 | stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d); |
---|
183 | signal c_state : states; |
---|
184 | |
---|
185 | signal iscl_oen, isda_oen : std_logic; -- internal I2C lines |
---|
186 | signal sda_chk : std_logic; -- check SDA status (multi-master arbitration) |
---|
187 | signal dscl_oen : std_logic; -- delayed scl_oen signals |
---|
188 | signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs |
---|
189 | signal dSCL, dSDA : std_logic; -- delayed versions ofsSCL and sSDA |
---|
190 | signal clk_en : std_logic; -- statemachine clock enable |
---|
191 | signal scl_sync, slave_wait : std_logic; -- clock generation signals |
---|
192 | signal ial : std_logic; -- internal arbitration lost signal |
---|
193 | signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis) |
---|
194 | |
---|
195 | begin |
---|
196 | -- whenever the slave is not ready it can delay the cycle by pulling SCL low |
---|
197 | -- delay scl_oen |
---|
198 | process (clk, nReset) |
---|
199 | begin |
---|
200 | if (nReset = '0') then |
---|
201 | dscl_oen <= '0'; |
---|
202 | elsif (clk'event and clk = '1') then |
---|
203 | dscl_oen <= iscl_oen; |
---|
204 | end if; |
---|
205 | end process; |
---|
206 | |
---|
207 | -- slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low |
---|
208 | -- slave_wait remains asserted until the slave releases SCL |
---|
209 | process (clk, nReset) |
---|
210 | begin |
---|
211 | if (nReset = '0') then |
---|
212 | slave_wait <= '0'; |
---|
213 | elsif (clk'event and clk = '1') then |
---|
214 | slave_wait <= (iscl_oen and not dscl_oen and not sSCL) or (slave_wait and not sSCL); |
---|
215 | end if; |
---|
216 | end process; |
---|
217 | |
---|
218 | -- master drives SCL high, but another master pulls it low |
---|
219 | -- master start counting down its low cycle now (clock synchronization) |
---|
220 | scl_sync <= dSCL and not sSCL and iscl_oen; |
---|
221 | |
---|
222 | -- generate clk enable signal |
---|
223 | gen_clken: process(clk, nReset) |
---|
224 | begin |
---|
225 | if (nReset = '0') then |
---|
226 | cnt <= (others => '0'); |
---|
227 | clk_en <= '1'; |
---|
228 | elsif (clk'event and clk = '1') then |
---|
229 | if ((rst = '1') or (cnt = 0) or (ena = '0') or (scl_sync = '1')) then |
---|
230 | cnt <= clk_cnt; |
---|
231 | clk_en <= '1'; |
---|
232 | elsif (slave_wait = '1') then |
---|
233 | cnt <= cnt; |
---|
234 | clk_en <= '0'; |
---|
235 | else |
---|
236 | cnt <= cnt -1; |
---|
237 | clk_en <= '0'; |
---|
238 | end if; |
---|
239 | end if; |
---|
240 | end process gen_clken; |
---|
241 | |
---|
242 | |
---|
243 | -- generate bus status controller |
---|
244 | bus_status_ctrl: block |
---|
245 | signal cSCL, cSDA : std_logic_vector( 1 downto 0); -- capture SDA and SCL |
---|
246 | signal fSCL, fSDA : std_logic_vector( 2 downto 0); -- filter inputs for SCL and SDA |
---|
247 | signal filter_cnt : unsigned(13 downto 0); -- clock divider for filter |
---|
248 | signal sta_condition : std_logic; -- start detected |
---|
249 | signal sto_condition : std_logic; -- stop detected |
---|
250 | signal cmd_stop : std_logic; -- STOP command |
---|
251 | signal ibusy : std_logic; -- internal busy signal |
---|
252 | begin |
---|
253 | -- capture SCL and SDA |
---|
254 | capture_scl_sda: process(clk, nReset) |
---|
255 | begin |
---|
256 | if (nReset = '0') then |
---|
257 | cSCL <= "00"; |
---|
258 | cSDA <= "00"; |
---|
259 | elsif (clk'event and clk = '1') then |
---|
260 | if (rst = '1') then |
---|
261 | cSCL <= "00"; |
---|
262 | cSDA <= "00"; |
---|
263 | else |
---|
264 | cSCL <= (cSCL(0) & scl_i); |
---|
265 | cSDA <= (cSDA(0) & sda_i); |
---|
266 | end if; |
---|
267 | end if; |
---|
268 | end process capture_scl_sda; |
---|
269 | |
---|
270 | -- filter SCL and SDA; (attempt to) remove glitches |
---|
271 | filter_divider: process(clk, nReset) |
---|
272 | begin |
---|
273 | if (nReset = '0') then |
---|
274 | filter_cnt <= (others => '0'); |
---|
275 | elsif (clk'event and clk = '1') then |
---|
276 | if ( (rst = '1') or (ena = '0') ) then |
---|
277 | filter_cnt <= (others => '0'); |
---|
278 | elsif (filter_cnt = 0) then |
---|
279 | filter_cnt <= clk_cnt(15 downto 2); |
---|
280 | else |
---|
281 | filter_cnt <= filter_cnt -1; |
---|
282 | end if; |
---|
283 | end if; |
---|
284 | end process filter_divider; |
---|
285 | |
---|
286 | filter_scl_sda: process(clk, nReset) |
---|
287 | begin |
---|
288 | if (nReset = '0') then |
---|
289 | fSCL <= (others => '1'); |
---|
290 | fSDA <= (others => '1'); |
---|
291 | elsif (clk'event and clk = '1') then |
---|
292 | if (rst = '1') then |
---|
293 | fSCL <= (others => '1'); |
---|
294 | fSDA <= (others => '1'); |
---|
295 | elsif (filter_cnt = 0) then |
---|
296 | fSCL <= (fSCL(1 downto 0) & cSCL(1)); |
---|
297 | fSDA <= (fSDA(1 downto 0) & cSDA(1)); |
---|
298 | end if; |
---|
299 | end if; |
---|
300 | end process filter_scl_sda; |
---|
301 | |
---|
302 | -- generate filtered SCL and SDA signals |
---|
303 | scl_sda: process(clk, nReset) |
---|
304 | begin |
---|
305 | if (nReset = '0') then |
---|
306 | sSCL <= '1'; |
---|
307 | sSDA <= '1'; |
---|
308 | |
---|
309 | dSCL <= '1'; |
---|
310 | dSDA <= '1'; |
---|
311 | elsif (clk'event and clk = '1') then |
---|
312 | if (rst = '1') then |
---|
313 | sSCL <= '1'; |
---|
314 | sSDA <= '1'; |
---|
315 | |
---|
316 | dSCL <= '1'; |
---|
317 | dSDA <= '1'; |
---|
318 | else |
---|
319 | sSCL <= (fSCL(2) and fSCL(1)) or |
---|
320 | (fSCL(2) and fSCL(0)) or |
---|
321 | (fSCL(1) and fSCL(0)); |
---|
322 | sSDA <= (fSDA(2) and fSDA(1)) or |
---|
323 | (fSDA(2) and fSDA(0)) or |
---|
324 | (fSDA(1) and fSDA(0)); |
---|
325 | |
---|
326 | dSCL <= sSCL; |
---|
327 | dSDA <= sSDA; |
---|
328 | end if; |
---|
329 | end if; |
---|
330 | end process scl_sda; |
---|
331 | |
---|
332 | |
---|
333 | -- detect start condition => detect falling edge on SDA while SCL is high |
---|
334 | -- detect stop condition => detect rising edge on SDA while SCL is high |
---|
335 | detect_sta_sto: process(clk, nReset) |
---|
336 | begin |
---|
337 | if (nReset = '0') then |
---|
338 | sta_condition <= '0'; |
---|
339 | sto_condition <= '0'; |
---|
340 | elsif (clk'event and clk = '1') then |
---|
341 | if (rst = '1') then |
---|
342 | sta_condition <= '0'; |
---|
343 | sto_condition <= '0'; |
---|
344 | else |
---|
345 | sta_condition <= (not sSDA and dSDA) and sSCL; |
---|
346 | sto_condition <= (sSDA and not dSDA) and sSCL; |
---|
347 | end if; |
---|
348 | end if; |
---|
349 | end process detect_sta_sto; |
---|
350 | |
---|
351 | |
---|
352 | -- generate i2c-bus busy signal |
---|
353 | gen_busy: process(clk, nReset) |
---|
354 | begin |
---|
355 | if (nReset = '0') then |
---|
356 | ibusy <= '0'; |
---|
357 | elsif (clk'event and clk = '1') then |
---|
358 | if (rst = '1') then |
---|
359 | ibusy <= '0'; |
---|
360 | else |
---|
361 | ibusy <= (sta_condition or ibusy) and not sto_condition; |
---|
362 | end if; |
---|
363 | end if; |
---|
364 | end process gen_busy; |
---|
365 | busy <= ibusy; |
---|
366 | |
---|
367 | |
---|
368 | -- generate arbitration lost signal |
---|
369 | -- aribitration lost when: |
---|
370 | -- 1) master drives SDA high, but the i2c bus is low |
---|
371 | -- 2) stop detected while not requested (detect during 'idle' state) |
---|
372 | gen_al: process(clk, nReset) |
---|
373 | begin |
---|
374 | if (nReset = '0') then |
---|
375 | cmd_stop <= '0'; |
---|
376 | ial <= '0'; |
---|
377 | elsif (clk'event and clk = '1') then |
---|
378 | if (rst = '1') then |
---|
379 | cmd_stop <= '0'; |
---|
380 | ial <= '0'; |
---|
381 | else |
---|
382 | if (clk_en = '1') then |
---|
383 | if (cmd = I2C_CMD_STOP) then |
---|
384 | cmd_stop <= '1'; |
---|
385 | else |
---|
386 | cmd_stop <= '0'; |
---|
387 | end if; |
---|
388 | end if; |
---|
389 | |
---|
390 | if (c_state = idle) then |
---|
391 | ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop); |
---|
392 | else |
---|
393 | ial <= (sda_chk and not sSDA and isda_oen); |
---|
394 | end if; |
---|
395 | end if; |
---|
396 | end if; |
---|
397 | end process gen_al; |
---|
398 | al <= ial; |
---|
399 | |
---|
400 | |
---|
401 | -- generate dout signal, store dout on rising edge of SCL |
---|
402 | gen_dout: process(clk, nReset) |
---|
403 | begin |
---|
404 | if (nReset = '0') then |
---|
405 | dout <= '0'; |
---|
406 | elsif (clk'event and clk = '1') then |
---|
407 | if (sSCL = '1' and dSCL = '0') then |
---|
408 | dout <= sSDA; |
---|
409 | end if; |
---|
410 | end if; |
---|
411 | end process gen_dout; |
---|
412 | end block bus_status_ctrl; |
---|
413 | |
---|
414 | |
---|
415 | -- generate statemachine |
---|
416 | nxt_state_decoder : process (clk, nReset) |
---|
417 | begin |
---|
418 | if (nReset = '0') then |
---|
419 | c_state <= idle; |
---|
420 | cmd_ack <= '0'; |
---|
421 | iscl_oen <= '1'; |
---|
422 | isda_oen <= '1'; |
---|
423 | sda_chk <= '0'; |
---|
424 | elsif (clk'event and clk = '1') then |
---|
425 | if (rst = '1' or ial = '1') then |
---|
426 | c_state <= idle; |
---|
427 | cmd_ack <= '0'; |
---|
428 | iscl_oen <= '1'; |
---|
429 | isda_oen <= '1'; |
---|
430 | sda_chk <= '0'; |
---|
431 | else |
---|
432 | cmd_ack <= '0'; -- default no acknowledge |
---|
433 | |
---|
434 | if (clk_en = '1') then |
---|
435 | case (c_state) is |
---|
436 | -- idle |
---|
437 | when idle => |
---|
438 | case cmd is |
---|
439 | when I2C_CMD_START => c_state <= start_a; |
---|
440 | when I2C_CMD_STOP => c_state <= stop_a; |
---|
441 | when I2C_CMD_WRITE => c_state <= wr_a; |
---|
442 | when I2C_CMD_READ => c_state <= rd_a; |
---|
443 | when others => c_state <= idle; -- NOP command |
---|
444 | end case; |
---|
445 | |
---|
446 | iscl_oen <= iscl_oen; -- keep SCL in same state |
---|
447 | isda_oen <= isda_oen; -- keep SDA in same state |
---|
448 | sda_chk <= '0'; -- don't check SDA |
---|
449 | |
---|
450 | -- start |
---|
451 | when start_a => |
---|
452 | c_state <= start_b; |
---|
453 | iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start) |
---|
454 | isda_oen <= '1'; -- set SDA high |
---|
455 | sda_chk <= '0'; -- don't check SDA |
---|
456 | |
---|
457 | when start_b => |
---|
458 | c_state <= start_c; |
---|
459 | iscl_oen <= '1'; -- set SCL high |
---|
460 | isda_oen <= '1'; -- keep SDA high |
---|
461 | sda_chk <= '0'; -- don't check SDA |
---|
462 | |
---|
463 | when start_c => |
---|
464 | c_state <= start_d; |
---|
465 | iscl_oen <= '1'; -- keep SCL high |
---|
466 | isda_oen <= '0'; -- set SDA low |
---|
467 | sda_chk <= '0'; -- don't check SDA |
---|
468 | |
---|
469 | when start_d => |
---|
470 | c_state <= start_e; |
---|
471 | iscl_oen <= '1'; -- keep SCL high |
---|
472 | isda_oen <= '0'; -- keep SDA low |
---|
473 | sda_chk <= '0'; -- don't check SDA |
---|
474 | |
---|
475 | when start_e => |
---|
476 | c_state <= idle; |
---|
477 | cmd_ack <= '1'; -- command completed |
---|
478 | iscl_oen <= '0'; -- set SCL low |
---|
479 | isda_oen <= '0'; -- keep SDA low |
---|
480 | sda_chk <= '0'; -- don't check SDA |
---|
481 | |
---|
482 | -- stop |
---|
483 | when stop_a => |
---|
484 | c_state <= stop_b; |
---|
485 | iscl_oen <= '0'; -- keep SCL low |
---|
486 | isda_oen <= '0'; -- set SDA low |
---|
487 | sda_chk <= '0'; -- don't check SDA |
---|
488 | |
---|
489 | when stop_b => |
---|
490 | c_state <= stop_c; |
---|
491 | iscl_oen <= '1'; -- set SCL high |
---|
492 | isda_oen <= '0'; -- keep SDA low |
---|
493 | sda_chk <= '0'; -- don't check SDA |
---|
494 | |
---|
495 | when stop_c => |
---|
496 | c_state <= stop_d; |
---|
497 | iscl_oen <= '1'; -- keep SCL high |
---|
498 | isda_oen <= '0'; -- keep SDA low |
---|
499 | sda_chk <= '0'; -- don't check SDA |
---|
500 | |
---|
501 | when stop_d => |
---|
502 | c_state <= idle; |
---|
503 | cmd_ack <= '1'; -- command completed |
---|
504 | iscl_oen <= '1'; -- keep SCL high |
---|
505 | isda_oen <= '1'; -- set SDA high |
---|
506 | sda_chk <= '0'; -- don't check SDA |
---|
507 | |
---|
508 | -- read |
---|
509 | when rd_a => |
---|
510 | c_state <= rd_b; |
---|
511 | iscl_oen <= '0'; -- keep SCL low |
---|
512 | isda_oen <= '1'; -- tri-state SDA |
---|
513 | sda_chk <= '0'; -- don't check SDA |
---|
514 | |
---|
515 | when rd_b => |
---|
516 | c_state <= rd_c; |
---|
517 | iscl_oen <= '1'; -- set SCL high |
---|
518 | isda_oen <= '1'; -- tri-state SDA |
---|
519 | sda_chk <= '0'; -- don't check SDA |
---|
520 | |
---|
521 | when rd_c => |
---|
522 | c_state <= rd_d; |
---|
523 | iscl_oen <= '1'; -- keep SCL high |
---|
524 | isda_oen <= '1'; -- tri-state SDA |
---|
525 | sda_chk <= '0'; -- don't check SDA |
---|
526 | |
---|
527 | when rd_d => |
---|
528 | c_state <= idle; |
---|
529 | cmd_ack <= '1'; -- command completed |
---|
530 | iscl_oen <= '0'; -- set SCL low |
---|
531 | isda_oen <= '1'; -- tri-state SDA |
---|
532 | sda_chk <= '0'; -- don't check SDA |
---|
533 | |
---|
534 | -- write |
---|
535 | when wr_a => |
---|
536 | c_state <= wr_b; |
---|
537 | iscl_oen <= '0'; -- keep SCL low |
---|
538 | isda_oen <= din; -- set SDA |
---|
539 | sda_chk <= '0'; -- don't check SDA (SCL low) |
---|
540 | |
---|
541 | when wr_b => |
---|
542 | c_state <= wr_c; |
---|
543 | iscl_oen <= '1'; -- set SCL high |
---|
544 | isda_oen <= din; -- keep SDA |
---|
545 | sda_chk <= '0'; -- don't check SDA yet |
---|
546 | -- Allow some more time for SDA and SCL to settle |
---|
547 | |
---|
548 | when wr_c => |
---|
549 | c_state <= wr_d; |
---|
550 | iscl_oen <= '1'; -- keep SCL high |
---|
551 | isda_oen <= din; -- keep SDA |
---|
552 | sda_chk <= '1'; -- check SDA |
---|
553 | |
---|
554 | when wr_d => |
---|
555 | c_state <= idle; |
---|
556 | cmd_ack <= '1'; -- command completed |
---|
557 | iscl_oen <= '0'; -- set SCL low |
---|
558 | isda_oen <= din; -- keep SDA |
---|
559 | sda_chk <= '0'; -- don't check SDA (SCL low) |
---|
560 | |
---|
561 | when others => |
---|
562 | |
---|
563 | end case; |
---|
564 | end if; |
---|
565 | end if; |
---|
566 | end if; |
---|
567 | end process nxt_state_decoder; |
---|
568 | |
---|
569 | |
---|
570 | -- assign outputs |
---|
571 | scl_o <= '0'; |
---|
572 | scl_oen <= iscl_oen; |
---|
573 | sda_o <= '0'; |
---|
574 | sda_oen <= isda_oen; |
---|
575 | end architecture structural; |
---|
576 | |
---|