1 | --------------------------------------------------------------------- |
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2 | ---- ---- |
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3 | ---- WISHBONE revB2 compl. I2C Master Core; top level ---- |
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4 | ---- ---- |
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5 | ---- ---- |
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6 | ---- Author: Richard Herveille ---- |
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7 | ---- richard@asics.ws ---- |
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8 | ---- www.asics.ws ---- |
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9 | ---- ---- |
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10 | ---- Downloaded from: http://www.opencores.org/projects/i2c/ ---- |
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11 | ---- ---- |
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12 | --------------------------------------------------------------------- |
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13 | ---- ---- |
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14 | ---- Copyright (C) 2000 Richard Herveille ---- |
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15 | ---- richard@asics.ws ---- |
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16 | ---- ---- |
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17 | ---- This source file may be used and distributed without ---- |
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18 | ---- restriction provided that this copyright statement is not ---- |
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19 | ---- removed from the file and that any derivative work contains ---- |
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20 | ---- the original copyright notice and the associated disclaimer.---- |
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21 | ---- ---- |
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22 | ---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- |
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23 | ---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- |
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24 | ---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- |
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25 | ---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- |
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26 | ---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- |
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27 | ---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- |
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28 | ---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- |
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29 | ---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- |
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30 | ---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- |
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31 | ---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- |
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32 | ---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- |
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33 | ---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- |
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34 | ---- POSSIBILITY OF SUCH DAMAGE. ---- |
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35 | ---- ---- |
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36 | --------------------------------------------------------------------- |
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37 | |
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38 | -- CVS Log |
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39 | -- |
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40 | -- $Id: i2c_master_top.vhd,v 1.8 2009-01-20 10:38:45 rherveille Exp $ |
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41 | -- |
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42 | -- $Date: 2009-01-20 10:38:45 $ |
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43 | -- $Revision: 1.8 $ |
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44 | -- $Author: rherveille $ |
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45 | -- $Locker: $ |
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46 | -- $State: Exp $ |
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47 | -- |
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48 | -- Change History: |
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49 | -- Revision 1.7 2004/03/14 10:17:03 rherveille |
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50 | -- Fixed simulation issue when writing to CR register |
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51 | -- |
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52 | -- Revision 1.6 2003/08/09 07:01:13 rherveille |
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53 | -- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. |
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54 | -- Fixed a potential bug in the byte controller's host-acknowledge generation. |
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55 | -- |
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56 | -- Revision 1.5 2003/02/01 02:03:06 rherveille |
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57 | -- Fixed a few 'arbitration lost' bugs. VHDL version only. |
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58 | -- |
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59 | -- Revision 1.4 2002/12/26 16:05:47 rherveille |
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60 | -- Core is now a Multimaster I2C controller. |
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61 | -- |
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62 | -- Revision 1.3 2002/11/30 22:24:37 rherveille |
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63 | -- Cleaned up code |
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64 | -- |
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65 | -- Revision 1.2 2001/11/10 10:52:44 rherveille |
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66 | -- Changed PRER reset value from 0x0000 to 0xffff, conform specs. |
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67 | -- |
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68 | |
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69 | |
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70 | library ieee; |
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71 | use ieee.std_logic_1164.all; |
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72 | |
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73 | entity i2c_master_top is |
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74 | generic( |
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75 | ARST_LVL : std_logic := '0' -- asynchronous reset level |
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76 | ); |
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77 | port ( |
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78 | -- wishbone signals |
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79 | wb_clk_i : in std_logic; -- master clock input |
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80 | wb_rst_i : in std_logic := '0'; -- synchronous active high reset |
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81 | arst_i : in std_logic := not ARST_LVL; -- asynchronous reset |
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82 | wb_adr_i : in std_logic_vector(2 downto 0); -- lower address bits |
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83 | wb_dat_i : in std_logic_vector(7 downto 0); -- Databus input |
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84 | wb_dat_o : out std_logic_vector(7 downto 0); -- Databus output |
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85 | wb_we_i : in std_logic; -- Write enable input |
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86 | wb_stb_i : in std_logic; -- Strobe signals / core select signal |
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87 | wb_cyc_i : in std_logic; -- Valid bus cycle input |
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88 | wb_ack_o : out std_logic; -- Bus cycle acknowledge output |
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89 | wb_inta_o : out std_logic; -- interrupt request output signal |
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90 | |
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91 | -- i2c lines |
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92 | scl_pad_i : in std_logic; -- i2c clock line input |
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93 | scl_pad_o : out std_logic; -- i2c clock line output |
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94 | scl_padoen_o : out std_logic; -- i2c clock line output enable, active low |
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95 | sda_pad_i : in std_logic; -- i2c data line input |
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96 | sda_pad_o : out std_logic; -- i2c data line output |
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97 | sda_padoen_o : out std_logic -- i2c data line output enable, active low |
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98 | ); |
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99 | end entity i2c_master_top; |
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100 | |
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101 | architecture structural of i2c_master_top is |
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102 | component i2c_master_byte_ctrl is |
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103 | port ( |
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104 | clk : in std_logic; |
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105 | rst : in std_logic; -- synchronous active high reset (WISHBONE compatible) |
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106 | nReset : in std_logic; -- asynchornous active low reset (FPGA compatible) |
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107 | ena : in std_logic; -- core enable signal |
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108 | |
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109 | clk_cnt : in unsigned(15 downto 0); -- 4x SCL |
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110 | |
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111 | -- input signals |
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112 | start, |
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113 | stop, |
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114 | read, |
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115 | write, |
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116 | ack_in : std_logic; |
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117 | din : in std_logic_vector(7 downto 0); |
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118 | |
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119 | -- output signals |
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120 | cmd_ack : out std_logic; |
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121 | ack_out : out std_logic; |
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122 | i2c_busy : out std_logic; |
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123 | i2c_al : out std_logic; |
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124 | dout : out std_logic_vector(7 downto 0); |
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125 | |
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126 | -- i2c lines |
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127 | scl_i : in std_logic; -- i2c clock line input |
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128 | scl_o : out std_logic; -- i2c clock line output |
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129 | scl_oen : out std_logic; -- i2c clock line output enable, active low |
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130 | sda_i : in std_logic; -- i2c data line input |
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131 | sda_o : out std_logic; -- i2c data line output |
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132 | sda_oen : out std_logic -- i2c data line output enable, active low |
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133 | ); |
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134 | end component i2c_master_byte_ctrl; |
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135 | |
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136 | -- registers |
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137 | signal prer : unsigned(15 downto 0); -- clock prescale register |
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138 | signal ctr : std_logic_vector(7 downto 0); -- control register |
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139 | signal txr : std_logic_vector(7 downto 0); -- transmit register |
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140 | signal rxr : std_logic_vector(7 downto 0); -- receive register |
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141 | signal cr : std_logic_vector(7 downto 0); -- command register |
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142 | signal sr : std_logic_vector(7 downto 0); -- status register |
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143 | |
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144 | -- internal reset signal |
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145 | signal rst_i : std_logic; |
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146 | |
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147 | -- wishbone write access |
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148 | signal wb_wacc : std_logic; |
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149 | |
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150 | -- internal acknowledge signal |
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151 | signal iack_o : std_logic; |
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152 | |
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153 | -- done signal: command completed, clear command register |
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154 | signal done : std_logic; |
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155 | |
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156 | -- command register signals |
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157 | signal sta, sto, rd, wr, ack, iack : std_logic; |
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158 | |
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159 | signal core_en : std_logic; -- core enable signal |
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160 | signal ien : std_logic; -- interrupt enable signal |
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161 | |
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162 | -- status register signals |
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163 | signal irxack, rxack : std_logic; -- received aknowledge from slave |
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164 | signal tip : std_logic; -- transfer in progress |
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165 | signal irq_flag : std_logic; -- interrupt pending flag |
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166 | signal i2c_busy : std_logic; -- i2c bus busy (start signal detected) |
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167 | signal i2c_al, al : std_logic; -- arbitration lost |
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168 | |
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169 | begin |
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170 | -- generate internal reset signal |
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171 | rst_i <= arst_i xor ARST_LVL; |
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172 | |
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173 | -- generate acknowledge output signal |
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174 | gen_ack_o : process(wb_clk_i) |
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175 | begin |
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176 | if (wb_clk_i'event and wb_clk_i = '1') then |
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177 | iack_o <= wb_cyc_i and wb_stb_i and not iack_o; -- because timing is always honored |
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178 | end if; |
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179 | end process gen_ack_o; |
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180 | wb_ack_o <= iack_o; |
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181 | |
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182 | -- generate wishbone write access signal |
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183 | wb_wacc <= wb_we_i and iack_o; |
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184 | |
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185 | -- assign wb_dat_o |
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186 | assign_dato : process(wb_clk_i) |
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187 | begin |
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188 | if (wb_clk_i'event and wb_clk_i = '1') then |
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189 | case wb_adr_i is |
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190 | when "000" => wb_dat_o <= std_logic_vector(prer( 7 downto 0)); |
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191 | when "001" => wb_dat_o <= std_logic_vector(prer(15 downto 8)); |
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192 | when "010" => wb_dat_o <= ctr; |
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193 | when "011" => wb_dat_o <= rxr; -- write is transmit register TxR |
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194 | when "100" => wb_dat_o <= sr; -- write is command register CR |
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195 | |
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196 | -- Debugging registers: |
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197 | -- These registers are not documented. |
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198 | -- Functionality could change in future releases |
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199 | when "101" => wb_dat_o <= txr; |
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200 | when "110" => wb_dat_o <= cr; |
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201 | when "111" => wb_dat_o <= (others => '0'); |
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202 | when others => wb_dat_o <= (others => 'X'); -- for simulation only |
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203 | end case; |
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204 | end if; |
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205 | end process assign_dato; |
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206 | |
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207 | |
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208 | -- generate registers (CR, SR see below) |
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209 | gen_regs: process(rst_i, wb_clk_i) |
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210 | begin |
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211 | if (rst_i = '0') then |
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212 | prer <= (others => '1'); |
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213 | ctr <= (others => '0'); |
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214 | txr <= (others => '0'); |
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215 | elsif (wb_clk_i'event and wb_clk_i = '1') then |
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216 | if (wb_rst_i = '1') then |
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217 | prer <= (others => '1'); |
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218 | ctr <= (others => '0'); |
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219 | txr <= (others => '0'); |
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220 | elsif (wb_wacc = '1') then |
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221 | case wb_adr_i is |
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222 | when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i); |
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223 | when "001" => prer(15 downto 8) <= unsigned(wb_dat_i); |
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224 | when "010" => ctr <= wb_dat_i; |
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225 | when "011" => txr <= wb_dat_i; |
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226 | when "100" => null; --write to CR, avoid executing the others clause |
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227 | |
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228 | -- illegal cases, for simulation only |
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229 | when others => |
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230 | report ("Illegal write address, setting all registers to unknown."); |
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231 | prer <= (others => 'X'); |
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232 | ctr <= (others => 'X'); |
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233 | txr <= (others => 'X'); |
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234 | end case; |
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235 | end if; |
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236 | end if; |
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237 | end process gen_regs; |
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238 | |
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239 | |
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240 | -- generate command register |
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241 | gen_cr: process(rst_i, wb_clk_i) |
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242 | begin |
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243 | if (rst_i = '0') then |
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244 | cr <= (others => '0'); |
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245 | elsif (wb_clk_i'event and wb_clk_i = '1') then |
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246 | if (wb_rst_i = '1') then |
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247 | cr <= (others => '0'); |
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248 | elsif (wb_wacc = '1') then |
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249 | if ( (core_en = '1') and (wb_adr_i = "100") ) then |
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250 | -- only take new commands when i2c core enabled |
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251 | -- pending commands are finished |
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252 | cr <= wb_dat_i; |
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253 | end if; |
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254 | else |
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255 | if (done = '1' or i2c_al = '1') then |
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256 | cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost |
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257 | end if; |
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258 | |
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259 | cr(2 downto 1) <= (others => '0'); -- reserved bits, always '0' |
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260 | cr(0) <= '0'; -- clear IRQ_ACK bit |
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261 | end if; |
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262 | end if; |
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263 | end process gen_cr; |
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264 | |
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265 | -- decode command register |
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266 | sta <= cr(7); |
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267 | sto <= cr(6); |
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268 | rd <= cr(5); |
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269 | wr <= cr(4); |
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270 | ack <= cr(3); |
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271 | iack <= cr(0); |
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272 | |
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273 | -- decode control register |
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274 | core_en <= ctr(7); |
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275 | ien <= ctr(6); |
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276 | |
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277 | -- hookup byte controller block |
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278 | byte_ctrl: i2c_master_byte_ctrl |
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279 | port map ( |
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280 | clk => wb_clk_i, |
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281 | rst => wb_rst_i, |
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282 | nReset => rst_i, |
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283 | ena => core_en, |
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284 | clk_cnt => prer, |
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285 | start => sta, |
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286 | stop => sto, |
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287 | read => rd, |
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288 | write => wr, |
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289 | ack_in => ack, |
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290 | i2c_busy => i2c_busy, |
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291 | i2c_al => i2c_al, |
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292 | din => txr, |
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293 | cmd_ack => done, |
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294 | ack_out => irxack, |
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295 | dout => rxr, |
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296 | scl_i => scl_pad_i, |
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297 | scl_o => scl_pad_o, |
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298 | scl_oen => scl_padoen_o, |
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299 | sda_i => sda_pad_i, |
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300 | sda_o => sda_pad_o, |
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301 | sda_oen => sda_padoen_o |
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302 | ); |
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303 | |
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304 | |
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305 | -- status register block + interrupt request signal |
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306 | st_irq_block : block |
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307 | begin |
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308 | -- generate status register bits |
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309 | gen_sr_bits: process (wb_clk_i, rst_i) |
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310 | begin |
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311 | if (rst_i = '0') then |
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312 | al <= '0'; |
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313 | rxack <= '0'; |
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314 | tip <= '0'; |
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315 | irq_flag <= '0'; |
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316 | elsif (wb_clk_i'event and wb_clk_i = '1') then |
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317 | if (wb_rst_i = '1') then |
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318 | al <= '0'; |
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319 | rxack <= '0'; |
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320 | tip <= '0'; |
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321 | irq_flag <= '0'; |
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322 | else |
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323 | al <= i2c_al or (al and not sta); |
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324 | rxack <= irxack; |
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325 | tip <= (rd or wr); |
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326 | |
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327 | -- interrupt request flag is always generated |
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328 | irq_flag <= (done or i2c_al or irq_flag) and not iack; |
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329 | end if; |
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330 | end if; |
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331 | end process gen_sr_bits; |
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332 | |
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333 | -- generate interrupt request signals |
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334 | gen_irq: process (wb_clk_i, rst_i) |
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335 | begin |
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336 | if (rst_i = '0') then |
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337 | wb_inta_o <= '0'; |
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338 | elsif (wb_clk_i'event and wb_clk_i = '1') then |
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339 | if (wb_rst_i = '1') then |
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340 | wb_inta_o <= '0'; |
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341 | else |
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342 | -- interrupt signal is only generated when IEN (interrupt enable bit) is set |
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343 | wb_inta_o <= irq_flag and ien; |
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344 | end if; |
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345 | end if; |
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346 | end process gen_irq; |
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347 | |
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348 | -- assign status register bits |
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349 | sr(7) <= rxack; |
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350 | sr(6) <= i2c_busy; |
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351 | sr(5) <= al; |
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352 | sr(4 downto 2) <= (others => '0'); -- reserved |
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353 | sr(1) <= tip; |
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354 | sr(0) <= irq_flag; |
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355 | end block; |
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356 | |
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357 | end architecture structural; |
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