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w3_userio_axi.vhd

Last change on this file was 1927, checked in by murphpo, 11 years ago
AXI versions of WARP v3 support cores
File size: 21.3 KB

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1	------------------------------------------------------------------------------
2	-- w3_userio_axi.vhd - entity/architecture pair
3	------------------------------------------------------------------------------
4	-- IMPORTANT:
5	-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
6	--
7	-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
8	--
9	-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
10	-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
11	-- OF THE USER_LOGIC ENTITY.
12	------------------------------------------------------------------------------
13	--
14	-- ***************************************************************************
15	-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
16	--
17	-- Xilinx, Inc.
18	-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
19	-- AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
20	-- SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
21	-- OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
22	-- APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
23	-- THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
24	-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
25	-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
26	-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
27	-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
28	-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
29	-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30	-- FOR A PARTICULAR PURPOSE.
31	--
32	-- ***************************************************************************
33	--
34	------------------------------------------------------------------------------
35	-- Filename: w3_userio_axi.vhd
36	-- Version: 1.00.a
37	-- Description: Top level design, instantiates library components and user logic.
38	-- Date: Fri Nov 09 20:37:15 2012 (by Create and Import Peripheral Wizard)
39	-- VHDL Standard: VHDL'93
40	------------------------------------------------------------------------------
41	-- Naming Conventions:
42	-- active low signals: "*_n"
43	-- clock signals: "clk", "clk_div#", "clk_#x"
44	-- reset signals: "rst", "rst_n"
45	-- generics: "C_*"
46	-- user defined types: "*_TYPE"
47	-- state machine next state: "*_ns"
48	-- state machine current state: "*_cs"
49	-- combinatorial signals: "*_com"
50	-- pipelined or register delay signals: "*_d#"
51	-- counter signals: "cnt"
52	-- clock enable signals: "*_ce"
53	-- internal version of output port: "*_i"
54	-- device pins: "*_pin"
55	-- ports: "- Names begin with Uppercase"
56	-- processes: "*_PROCESS"
57	-- component instantiations: "<ENTITY_>I_<#\|FUNC>"
58	------------------------------------------------------------------------------
59
60	library ieee;
61	use ieee.std_logic_1164.all;
62	use ieee.std_logic_arith.all;
63	use ieee.std_logic_unsigned.all;
64
65	library proc_common_v3_00_a;
66	use proc_common_v3_00_a.proc_common_pkg.all;
67	use proc_common_v3_00_a.ipif_pkg.all;
68
69	library axi_lite_ipif_v1_01_a;
70	use axi_lite_ipif_v1_01_a.axi_lite_ipif;
71
72	------------------------------------------------------------------------------
73	-- Entity section
74	------------------------------------------------------------------------------
75	-- Definition of Generics:
76	-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
77	-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
78	-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
79	-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
80	-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
81	-- C_BASEADDR -- AXI4LITE slave: base address
82	-- C_HIGHADDR -- AXI4LITE slave: high address
83	-- C_FAMILY -- FPGA Family
84	-- C_NUM_REG -- Number of software accessible registers
85	-- C_NUM_MEM -- Number of address-ranges
86	-- C_SLV_AWIDTH -- Slave interface address bus width
87	-- C_SLV_DWIDTH -- Slave interface data bus width
88	--
89	-- Definition of Ports:
90	-- S_AXI_ACLK -- AXI4LITE slave: Clock
91	-- S_AXI_ARESETN -- AXI4LITE slave: Reset
92	-- S_AXI_AWADDR -- AXI4LITE slave: Write address
93	-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
94	-- S_AXI_WDATA -- AXI4LITE slave: Write data
95	-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
96	-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
97	-- S_AXI_BREADY -- AXI4LITE slave: Response ready
98	-- S_AXI_ARADDR -- AXI4LITE slave: Read address
99	-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
100	-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
101	-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
102	-- S_AXI_RDATA -- AXI4LITE slave: Read data
103	-- S_AXI_RRESP -- AXI4LITE slave: Read data response
104	-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
105	-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
106	-- S_AXI_BRESP -- AXI4LITE slave: Response
107	-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
108	-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
109	------------------------------------------------------------------------------
110
111	entity w3_userio_axi is
112	generic
113	(
114	-- ADD USER GENERICS BELOW THIS LINE ---------------
115	HEXDISP_ACTIVE_HIGH : integer := 0;
116	INCLUDE_DNA_READ_LOGIC : integer := 1;
117	-- ADD USER GENERICS ABOVE THIS LINE ---------------
118
119	-- DO NOT EDIT BELOW THIS LINE ---------------------
120	-- Bus protocol parameters, do not add to or delete
121	C_S_AXI_DATA_WIDTH : integer := 32;
122	C_S_AXI_ADDR_WIDTH : integer := 32;
123	C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
124	C_USE_WSTRB : integer := 0;
125	C_DPHASE_TIMEOUT : integer := 8;
126	C_BASEADDR : std_logic_vector := X"FFFFFFFF";
127	C_HIGHADDR : std_logic_vector := X"00000000";
128	C_FAMILY : string := "virtex6";
129	C_NUM_REG : integer := 1;
130	C_NUM_MEM : integer := 1;
131	C_SLV_AWIDTH : integer := 32;
132	C_SLV_DWIDTH : integer := 32
133	-- DO NOT EDIT ABOVE THIS LINE ---------------------
134	);
135	port
136	(
137	-- ADD USER PORTS BELOW THIS LINE ------------------
138	hexdisp_left : out std_logic_vector(0 to 6);
139	hexdisp_left_dp : out std_logic;
140	hexdisp_right : out std_logic_vector(0 to 6);
141	hexdisp_right_dp : out std_logic;
142
143	leds_red : out std_logic_vector(0 to 3);
144	leds_green : out std_logic_vector(0 to 3);
145
146	rfa_led_red : out std_logic;
147	rfa_led_green : out std_logic;
148	rfb_led_red : out std_logic;
149	rfb_led_green : out std_logic;
150
151	dipsw : in std_logic_vector(0 to 3);
152	pb_u : in std_logic;
153	pb_m : in std_logic;
154	pb_d : in std_logic;
155
156
157	usr_hexdisp_left : in std_logic_vector(0 to 6);
158	usr_hexdisp_left_dp : in std_logic;
159	usr_hexdisp_right : in std_logic_vector(0 to 6);
160	usr_hexdisp_right_dp : in std_logic;
161
162	usr_leds_red : in std_logic_vector(0 to 3);
163	usr_leds_green : in std_logic_vector(0 to 3);
164
165	usr_rfa_led_red : in std_logic;
166	usr_rfa_led_green : in std_logic;
167	usr_rfb_led_red : in std_logic;
168	usr_rfb_led_green : in std_logic;
169
170	usr_dipsw : out std_logic_vector(0 to 3);
171	usr_pb_u : out std_logic;
172	usr_pb_m : out std_logic;
173	usr_pb_d : out std_logic;
174
175	DNA_Port_Clk : in std_logic;
176	-- ADD USER PORTS ABOVE THIS LINE ------------------
177
178	-- DO NOT EDIT BELOW THIS LINE ---------------------
179	-- Bus protocol ports, do not add to or delete
180	S_AXI_ACLK : in std_logic;
181	S_AXI_ARESETN : in std_logic;
182	S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
183	S_AXI_AWVALID : in std_logic;
184	S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
185	S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
186	S_AXI_WVALID : in std_logic;
187	S_AXI_BREADY : in std_logic;
188	S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
189	S_AXI_ARVALID : in std_logic;
190	S_AXI_RREADY : in std_logic;
191	S_AXI_ARREADY : out std_logic;
192	S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
193	S_AXI_RRESP : out std_logic_vector(1 downto 0);
194	S_AXI_RVALID : out std_logic;
195	S_AXI_WREADY : out std_logic;
196	S_AXI_BRESP : out std_logic_vector(1 downto 0);
197	S_AXI_BVALID : out std_logic;
198	S_AXI_AWREADY : out std_logic
199	-- DO NOT EDIT ABOVE THIS LINE ---------------------
200	);
201
202	attribute MAX_FANOUT : string;
203	attribute SIGIS : string;
204	attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
205	attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
206	attribute SIGIS of S_AXI_ACLK : signal is "Clk";
207	attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
208	end entity w3_userio_axi;
209
210	------------------------------------------------------------------------------
211	-- Architecture section
212	------------------------------------------------------------------------------
213
214	architecture IMP of w3_userio_axi is
215
216	constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
217
218	constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
219
220	constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
221	constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
222	constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
223
224	constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
225	(
226	ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
227	ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
228	);
229
230	constant USER_SLV_NUM_REG : integer := 12;
231	constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
232	constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
233
234	constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
235	(
236	0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
237	);
238
239	------------------------------------------
240	-- Index for CS/CE
241	------------------------------------------
242	constant USER_SLV_CS_INDEX : integer := 0;
243	constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
244
245	constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
246
247	------------------------------------------
248	-- IP Interconnect (IPIC) signal declarations
249	------------------------------------------
250	signal ipif_Bus2IP_Clk : std_logic;
251	signal ipif_Bus2IP_Resetn : std_logic;
252	signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
253	signal ipif_Bus2IP_RNW : std_logic;
254	signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
255	signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
256	signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
257	signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
258	signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
259	signal ipif_IP2Bus_WrAck : std_logic;
260	signal ipif_IP2Bus_RdAck : std_logic;
261	signal ipif_IP2Bus_Error : std_logic;
262	signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
263	signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
264	signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
265	signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
266	signal user_IP2Bus_RdAck : std_logic;
267	signal user_IP2Bus_WrAck : std_logic;
268	signal user_IP2Bus_Error : std_logic;
269
270	------------------------------------------
271	-- Component declaration for verilog user logic
272	------------------------------------------
273	component user_logic is
274	generic
275	(
276	-- ADD USER GENERICS BELOW THIS LINE ---------------
277	HEXDISP_ACTIVE_HIGH : integer := 0;
278	INCLUDE_DNA_READ_LOGIC : integer := 1;
279	-- ADD USER GENERICS ABOVE THIS LINE ---------------
280
281	-- DO NOT EDIT BELOW THIS LINE ---------------------
282	-- Bus protocol parameters, do not add to or delete
283	C_NUM_REG : integer := 12;
284	C_SLV_DWIDTH : integer := 32
285	-- DO NOT EDIT ABOVE THIS LINE ---------------------
286	);
287	port
288	(
289	-- ADD USER PORTS BELOW THIS LINE ------------------
290	hexdisp_left : out std_logic_vector(0 to 6);
291	hexdisp_left_dp : out std_logic;
292	hexdisp_right : out std_logic_vector(0 to 6);
293	hexdisp_right_dp : out std_logic;
294
295	leds_red : out std_logic_vector(0 to 3);
296	leds_green : out std_logic_vector(0 to 3);
297
298	rfa_led_red : out std_logic;
299	rfa_led_green : out std_logic;
300	rfb_led_red : out std_logic;
301	rfb_led_green : out std_logic;
302
303	dipsw : in std_logic_vector(0 to 3);
304	pb_u : in std_logic;
305	pb_m : in std_logic;
306	pb_d : in std_logic;
307
308
309	usr_hexdisp_left : in std_logic_vector(0 to 6);
310	usr_hexdisp_left_dp : in std_logic;
311	usr_hexdisp_right : in std_logic_vector(0 to 6);
312	usr_hexdisp_right_dp : in std_logic;
313
314	usr_leds_red : in std_logic_vector(0 to 3);
315	usr_leds_green : in std_logic_vector(0 to 3);
316
317	usr_rfa_led_red : in std_logic;
318	usr_rfa_led_green : in std_logic;
319	usr_rfb_led_red : in std_logic;
320	usr_rfb_led_green : in std_logic;
321
322	usr_dipsw : out std_logic_vector(0 to 3);
323	usr_pb_u : out std_logic;
324	usr_pb_m : out std_logic;
325	usr_pb_d : out std_logic;
326	DNA_Port_Clk : in std_logic;
327	-- ADD USER PORTS ABOVE THIS LINE ------------------
328
329	-- DO NOT EDIT BELOW THIS LINE ---------------------
330	-- Bus protocol ports, do not add to or delete
331	Bus2IP_Clk : in std_logic;
332	Bus2IP_Resetn : in std_logic;
333	Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
334	Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
335	Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
336	Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
337	IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
338	IP2Bus_RdAck : out std_logic;
339	IP2Bus_WrAck : out std_logic;
340	IP2Bus_Error : out std_logic
341	-- DO NOT EDIT ABOVE THIS LINE ---------------------
342	);
343	end component user_logic;
344
345	begin
346
347	------------------------------------------
348	-- instantiate axi_lite_ipif
349	------------------------------------------
350	AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
351	generic map
352	(
353	C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
354	C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
355	C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
356	C_USE_WSTRB => C_USE_WSTRB,
357	C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
358	C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
359	C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
360	C_FAMILY => C_FAMILY
361	)
362	port map
363	(
364	S_AXI_ACLK => S_AXI_ACLK,
365	S_AXI_ARESETN => S_AXI_ARESETN,
366	S_AXI_AWADDR => S_AXI_AWADDR,
367	S_AXI_AWVALID => S_AXI_AWVALID,
368	S_AXI_WDATA => S_AXI_WDATA,
369	S_AXI_WSTRB => S_AXI_WSTRB,
370	S_AXI_WVALID => S_AXI_WVALID,
371	S_AXI_BREADY => S_AXI_BREADY,
372	S_AXI_ARADDR => S_AXI_ARADDR,
373	S_AXI_ARVALID => S_AXI_ARVALID,
374	S_AXI_RREADY => S_AXI_RREADY,
375	S_AXI_ARREADY => S_AXI_ARREADY,
376	S_AXI_RDATA => S_AXI_RDATA,
377	S_AXI_RRESP => S_AXI_RRESP,
378	S_AXI_RVALID => S_AXI_RVALID,
379	S_AXI_WREADY => S_AXI_WREADY,
380	S_AXI_BRESP => S_AXI_BRESP,
381	S_AXI_BVALID => S_AXI_BVALID,
382	S_AXI_AWREADY => S_AXI_AWREADY,
383	Bus2IP_Clk => ipif_Bus2IP_Clk,
384	Bus2IP_Resetn => ipif_Bus2IP_Resetn,
385	Bus2IP_Addr => ipif_Bus2IP_Addr,
386	Bus2IP_RNW => ipif_Bus2IP_RNW,
387	Bus2IP_BE => ipif_Bus2IP_BE,
388	Bus2IP_CS => ipif_Bus2IP_CS,
389	Bus2IP_RdCE => ipif_Bus2IP_RdCE,
390	Bus2IP_WrCE => ipif_Bus2IP_WrCE,
391	Bus2IP_Data => ipif_Bus2IP_Data,
392	IP2Bus_WrAck => ipif_IP2Bus_WrAck,
393	IP2Bus_RdAck => ipif_IP2Bus_RdAck,
394	IP2Bus_Error => ipif_IP2Bus_Error,
395	IP2Bus_Data => ipif_IP2Bus_Data
396	);
397
398	------------------------------------------
399	-- instantiate User Logic
400	------------------------------------------
401	USER_LOGIC_I : component user_logic
402	generic map
403	(
404	-- MAP USER GENERICS BELOW THIS LINE ---------------
405	HEXDISP_ACTIVE_HIGH => HEXDISP_ACTIVE_HIGH,
406	INCLUDE_DNA_READ_LOGIC => INCLUDE_DNA_READ_LOGIC,
407	-- MAP USER GENERICS ABOVE THIS LINE ---------------
408
409	C_NUM_REG => USER_NUM_REG,
410	C_SLV_DWIDTH => USER_SLV_DWIDTH
411	)
412	port map
413	(
414	-- MAP USER PORTS BELOW THIS LINE ------------------
415	hexdisp_left => hexdisp_left,
416	hexdisp_left_dp => hexdisp_left_dp,
417	hexdisp_right => hexdisp_right,
418	hexdisp_right_dp => hexdisp_right_dp,
419	leds_red => leds_red,
420	leds_green => leds_green,
421	rfa_led_red => rfa_led_red,
422	rfa_led_green => rfa_led_green,
423	rfb_led_red => rfb_led_red,
424	rfb_led_green => rfb_led_green,
425	dipsw => dipsw,
426	pb_u => pb_u,
427	pb_m => pb_m,
428	pb_d => pb_d,
429	usr_hexdisp_left => usr_hexdisp_left,
430	usr_hexdisp_left_dp => usr_hexdisp_left_dp,
431	usr_hexdisp_right => usr_hexdisp_right,
432	usr_hexdisp_right_dp => usr_hexdisp_right_dp,
433	usr_leds_red => usr_leds_red,
434	usr_leds_green => usr_leds_green,
435	usr_rfa_led_red => usr_rfa_led_red,
436	usr_rfa_led_green => usr_rfa_led_green,
437	usr_rfb_led_red => usr_rfb_led_red,
438	usr_rfb_led_green => usr_rfb_led_green,
439	usr_dipsw => usr_dipsw,
440	usr_pb_u => usr_pb_u,
441	usr_pb_m => usr_pb_m,
442	usr_pb_d => usr_pb_d,
443	DNA_Port_Clk => DNA_Port_Clk,
444	-- MAP USER PORTS ABOVE THIS LINE ------------------
445
446	Bus2IP_Clk => ipif_Bus2IP_Clk,
447	Bus2IP_Resetn => ipif_Bus2IP_Resetn,
448	Bus2IP_Data => ipif_Bus2IP_Data,
449	Bus2IP_BE => ipif_Bus2IP_BE,
450	Bus2IP_RdCE => user_Bus2IP_RdCE,
451	Bus2IP_WrCE => user_Bus2IP_WrCE,
452	IP2Bus_Data => user_IP2Bus_Data,
453	IP2Bus_RdAck => user_IP2Bus_RdAck,
454	IP2Bus_WrAck => user_IP2Bus_WrAck,
455	IP2Bus_Error => user_IP2Bus_Error
456	);
457
458	------------------------------------------
459	-- connect internal signals
460	------------------------------------------
461	ipif_IP2Bus_Data <= user_IP2Bus_Data;
462	ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
463	ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
464	ipif_IP2Bus_Error <= user_IP2Bus_Error;
465
466	user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
467	user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
468
469	end IMP;

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source: PlatformSupport/CustomPeripherals/pcores/w3_userio_axi_v1_00_a/hdl/vhdl/w3_userio_axi.vhd

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