source: PlatformSupport/CustomPeripherals/pcores/w3_userio_axi_v1_00_a/src/w3_userio.h

Last change on this file was 1927, checked in by murphpo, 11 years ago

AXI versions of WARP v3 support cores
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1/*****************************************************************
2* File: w3_userio.h
3* Copyright (c) 2012 Mango Communications, all rights reseved
4* Released under the WARP License
5* See http://warp.rice.edu/license for details
6*****************************************************************/
7
8/*! \file w3_userio.h
9
10\mainpage
11This is the driver for the w3_userio core, which provides access to all the user IO resources on WARP v3 boards. These resources include
12user LEDs, RF LEDs, hex displays, push buttons and a DIP switch.
13
14This driver only implements macros for reading/writing registers in the w3_userio core hardware. Macros are also provided to read the Virtex-6 device DNA.
15
16@version 1.00.a
17@author Patrick Murphy
18@copyright (c) 2012 Mango Communications, Inc. All rights reserved.<br>
19Released under the WARP open source license (see http://warp.rice.edu/license)
20
21*/
22
23    /* Address map:
24        HDL is coded [31:0], adopting Xilinx's convention for AXI IPIF cores
25        All registers are 32-bits
26            regX[31]  maps to 0x80000000 in C driver
27            regX[0]   maps to 0x00000001 in C driver
28
29    0: Control RW
30        [31:30] = Reserved
31        [   29] = Left hex data mode (0=user supplies bit-per-segment; 1=user supplies 4-bit hex)   0x20000000
32        [   28] = Right hex data mode (0=user supplies bit-per-segment; 1=user supplies 4-bit hex)  0x10000000
33      Control source for LEDs: 0=software controlled, 1=usr_ port controlled
34        [27:24] = {rfb_red rfb_green rfa_red rfa_green} 0x0F000000
35        [23:16] = {leds_red leds_green}                 0x00FF0000
36        [15: 8] = {hexdisp_left{a b c d e f g dp}}      0x0000FF00
37        [ 7: 0] = {hexdisp_right{a b c d e f g dp}}     0x000000FF
38    1: Left hex display RW
39        [31: 9] = reserved
40        [    8] = DP (controlled directly; doesn't depend on data mode) 0x100
41        [ 6: 0] = Data value ([6:4] ignored when data mode = 1)         0x03F
42    2: Right hex display RW
43        [31: 9] = reserved
44        [    8] = DP (controlled directly; doesn't depend on data mode) 0x100
45        [ 6: 0] = Data value ([6:4] ignored when data mode = 1)         0x03F
46    3: Red user LEDs RW
47        [31: 4] = reserved
48        [ 3: 0] = Data value (1=LED illuminated) 0xF, with 0x1 mapped to lowest LED
49    4: Green user LEDs RW
50        [31: 4] = reserved
51        [ 3: 0] = Data value (1=LED illuminated) 0xF, with 0x1 mapped to lowest LED
52    5: RF LEDs RW
53        [31: 4] = reserved
54        [    3] = rfb_red   0x8
55        [    2] = rfb_green 0x4
56        [    1] = rfa_red   0x2
57        [    0] = rfa_green 0x1
58    6: Switch/button inputs RO
59        [31: 7] = reserved
60        [    6] = pb_up         0x40
61        [    5] = pb_mid        0x20
62        [    4] = pb_down       0x10
63        [ 3: 0] = DIP switch    0x0F (with 0x1 mapped to right-most switch)
64
65  */
66
67#ifndef W3_USERIO_H
68#define W3_USERIO_H
69
70#include "xil_io.h"
71
72/// @cond EXCLUDE_FROM_DOCS
73// Address offset for each slave register; exclude from docs, as users never use these directly
74#define W3_USERIO_USER_SLV_SPACE_OFFSET (0x00000000)
75#define W3_USERIO_SLV_REG0_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000000)
76#define W3_USERIO_SLV_REG1_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000004)
77#define W3_USERIO_SLV_REG2_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000008)
78#define W3_USERIO_SLV_REG3_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x0000000C)
79#define W3_USERIO_SLV_REG4_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000010)
80#define W3_USERIO_SLV_REG5_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000014)
81#define W3_USERIO_SLV_REG6_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000018)
82#define W3_USERIO_SLV_REG7_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x0000001C)
83#define W3_USERIO_SLV_REG8_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000020)
84#define W3_USERIO_SLV_REG9_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000024)
85#define W3_USERIO_SLV_REG10_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000028)
86#define W3_USERIO_SLV_REG11_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x0000002C)
87/// @endcond
88
89/** \defgroup control_reg Control register
90 *  \addtogroup control_reg
91<b>Hardware vs. software control</b>:
92Every LED and hex display segment can be controlled either via software or hardware:
93<ul>
94<li>Software: user code sets LED state by writing a 1 to the corresponding register bit
95<li>Hardware: LED state is controlled by corresponding usr_* port
96</ul>
97
98The WARP reference designs use hardware control for the RF LEDs (to indicate real-time Tx/Rx state of each RF interface) and software control
99for all other LED/hex display outputs.
100
101The control source (hw or sw) for each output bit is set by the control register described below.
102
103Examples:
104\code{.c}
105//Assumes user code sets USERIO_BASEADDR to base address of w3_userio core, as set in xparameters.h
106
107//Set both hex dipslays to map 4-bit to 7-segment values automatically
108userio_write_control(USERIO_BASEADDR, (W3_USERIO_HEXDISP_L_MAPMODE | W3_USERIO_HEXDISP_R_MAPMODE));
109
110//Select software control of all outputs
111userio_set_ctrlSrc_sw(USERIO_BASEADDR, (W3_USERIO_CTRLSRC_LEDS_RF | W3_USERIO_CTRLSRC_LEDS | W3_USERIO_CTRLSRC_HEXDISPS));
112
113//Select hardware control of RF LEDs
114userio_set_ctrlSrc_hw(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_RF);
115
116//Enable hardware control of green user LEDs, software control of red user LEDs
117userio_set_ctrlSrc_hw(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_GREEN);
118userio_set_ctrlSrc_sw(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_RED);
119\endcode
120
121 * @{
122 */
123
124#define userio_read_control(baseaddr)       Xil_In32(baseaddr+W3_USERIO_SLV_REG0_OFFSET) //!< Returns the value of the control register
125#define userio_write_control(baseaddr, x)       Xil_Out32(baseaddr+W3_USERIO_SLV_REG0_OFFSET, x) //!< Sets the control register to x
126
127#define userio_set_ctrlSrc_hw(baseaddr, ioMask) Xil_Out32(baseaddr+W3_USERIO_SLV_REG0_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG0_OFFSET) | (ioMask))) //!< Sets selected outputs to hardware control (usr_ ports)
128#define userio_set_ctrlSrc_sw(baseaddr, ioMask) Xil_Out32(baseaddr+W3_USERIO_SLV_REG0_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG0_OFFSET) & ~(ioMask)))//!< Sets selected outputs to software control (register writes)
129
130//reg0 masks
131#define W3_USERIO_HEXDISP_L_MAPMODE     0x20000000 //!< Enables 4-bit to 7-segment mapping for left hex display
132#define W3_USERIO_HEXDISP_R_MAPMODE     0x10000000 //!< Enables 4-bit to 7-segment mapping for right hex display
133#define W3_USERIO_CTRLSRC_LED_RFB_RED   0x08000000 //!< Control source selection mask for red LED near RF B
134#define W3_USERIO_CTRLSRC_LED_RFB_GREEN 0x04000000 //!< Control source selection mask for green LED near RF B
135#define W3_USERIO_CTRLSRC_LED_RFA_RED   0x02000000 //!< Control source selection mask for red LED near RF A
136#define W3_USERIO_CTRLSRC_LED_RFA_GREEN 0x01000000 //!< Control source selection mask for green LED near RF A
137#define W3_USERIO_CTRLSRC_LEDS_RED      0x000F0000 //!< Control source selection mask for the red user LEDs
138#define W3_USERIO_CTRLSRC_LEDS_GREEN    0x00F00000 //!< Control source selection mask for the green user LEDs
139#define W3_USERIO_CTRLSRC_HEXDISP_L     0x0000FF00 //!< Control source selection mask for the left hex display
140#define W3_USERIO_CTRLSRC_HEXDISP_R     0x000000FF //!< Control source selection mask for the right hex display
141
142#define W3_USERIO_CTRLSRC_LEDS_RFA      (W3_USERIO_CTRLSRC_LED_RFA_RED | W3_USERIO_CTRLSRC_LED_RFA_GREEN) //!< Control source selection masks for both LEDs near RF A
143#define W3_USERIO_CTRLSRC_LEDS_RFB      (W3_USERIO_CTRLSRC_LED_RFB_RED | W3_USERIO_CTRLSRC_LED_RFB_GREEN) //!< Control source selection masks for both LEDs near RF B
144#define W3_USERIO_CTRLSRC_LEDS_RF       (W3_USERIO_CTRLSRC_LEDS_RFA | W3_USERIO_CTRLSRC_LEDS_RFB) //!< Control source selection masks for all RF LEDs
145#define W3_USERIO_CTRLSRC_LEDS          (W3_USERIO_CTRLSRC_LEDS_RED | W3_USERIO_CTRLSRC_LEDS_GREEN) //!< Control source selection masks for all user LEDs
146#define W3_USERIO_CTRLSRC_HEXDISPS      (W3_USERIO_CTRLSRC_HEXDISP_L | W3_USERIO_CTRLSRC_HEXDISP_R) //!< Control source selection masks for both hex displays
147/** @}*/
148
149
150/** \defgroup userio_read Reading user IO
151<b>Note on output state</b>: The macros for reading the current state of user outputs (LEDs, hex displays) can only access outputs configured for software control. Attempts to read the state
152of outputs configured for hardware control (i.e. outputs with corresponding CTRLSRC_* asserted in control reg) will not reflect actual output state.
153
154Examples:
155\code{.c}
156//Assumes user code sets USERIO_BASEADDR to base address of w3_userio core, as set in xparameters.h
157
158//Check if middle push button is being pressed
159if(userio_read_inputs(USERIO_BASEADDR) & W3_USERIO_PB_M) {...}
160
161//Read 4-bit DIP switch value
162u8 x = userio_read_inputs(USERIO_BASEADDR) & W3_USERIO_DIPSW;
163\endcode
164
165 *  \addtogroup userio_read
166 * @{
167 */
168#define userio_read_inputs(baseaddr)        Xil_In32(baseaddr+W3_USERIO_SLV_REG6_OFFSET) //!< Returns the current state of the user inputs (buttons and DIP switch)
169#define userio_read_hexdisp_left(baseaddr)  Xil_In32(baseaddr+W3_USERIO_SLV_REG1_OFFSET) //!< Returns the current state of the left hex display outputs
170#define userio_read_hexdisp_right(baseaddr) Xil_In32(baseaddr+W3_USERIO_SLV_REG2_OFFSET) //!< Returns the current state of the right hex display outputs
171#define userio_read_leds_red(baseaddr)      Xil_In32(baseaddr+W3_USERIO_SLV_REG3_OFFSET) //!< Returns the current state of the red user LEDs
172#define userio_read_leds_green(baseaddr)    Xil_In32(baseaddr+W3_USERIO_SLV_REG4_OFFSET) //!< Returns the current state of the green user LEDs
173#define userio_read_leds_rf(baseaddr)       Xil_In32(baseaddr+W3_USERIO_SLV_REG5_OFFSET) //!< Returns the current state of the RF LEDs
174/** @}*/
175
176/** \defgroup userio_write Setting user outputs
177
178<b>Hex display notes:</b>
179The w3_userio core implements logic to map 4-bit values to the 7-segment representation of the corresponding hex value. When this mode
180is enabled via the control register (W3_USERIO_HEXDISP_x_MAPMODE is asserte), user code should write 4-bit values via the hex display macros below. When map
181mode is disabled, the user value is driven directly to the 7-segments of the hex display.
182
183The decimal point on each hex dipslay is controlled by OR'ing 4 bit (in map mode) or 7 bit (in non-map mode) value with W3_USERIO_HEXDISP_DP.
184
185Examples:
186\code{.c}
187//Assumes user code sets USERIO_BASEADDR to base address of w3_userio core, as set in xparameters.h
188
189//Display "B" on the left hex dipslay (assumes map mode is enabled; see control register docs)
190userio_write_hexdisp_left(USERIO_ADDR, 0xB);
191
192//Display "4" on the right hex dipslay and light the decimal point (assumes map mode is enabled; see control register docs)
193userio_write_hexdisp_right(USERIO_ADDR, (0x4 | W3_USERIO_HEXDISP_DP) );
194
195//Turn off all four green user LEDs
196userio_write_leds_green(USERIO_ADDR, 0);
197
198//Toggle the 2 LSB of the red user LEDs
199userio_toggle_leds_red(USERIO_ADDR, 0x3);
200
201\endcode
202 *  \addtogroup userio_write
203 * @{
204 */
205#define userio_write_hexdisp_left(baseaddr, x)  Xil_Out32(baseaddr+W3_USERIO_SLV_REG1_OFFSET, x) //!< Sets the left hex dispaly
206#define userio_write_hexdisp_right(baseaddr, x) Xil_Out32(baseaddr+W3_USERIO_SLV_REG2_OFFSET, x) //!< Sets the right hex dispaly
207#define userio_write_leds_red(baseaddr, x)      Xil_Out32(baseaddr+W3_USERIO_SLV_REG3_OFFSET, x) //!< Sets the 4 red LEDs when configured for software control (software control is default)
208#define userio_write_leds_green(baseaddr, x)    Xil_Out32(baseaddr+W3_USERIO_SLV_REG4_OFFSET, x) //!< Sets the 4 green LEDs when configured for software control (software control is default)
209#define userio_write_leds_rf(baseaddr, x)       Xil_Out32(baseaddr+W3_USERIO_SLV_REG5_OFFSET, x) //!< Sets the 4 RF LEDs when configured for software control (hardware control is default)
210#define userio_toggle_hexdisp_left(baseaddr, mask)  Xil_Out32(baseaddr+W3_USERIO_SLV_REG1_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG1_OFFSET) ^ mask)) //!< Toggles the state of bits selected by mask on left hex display
211#define userio_toggle_hexdisp_right(baseaddr, mask) Xil_Out32(baseaddr+W3_USERIO_SLV_REG2_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG2_OFFSET) ^ mask)) //!< Toggles the state of bits selected by mask on right hex display
212#define userio_toggle_leds_red(baseaddr, mask)      Xil_Out32(baseaddr+W3_USERIO_SLV_REG3_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG3_OFFSET) ^ mask)) //!< Toggles the state of bits selected by mask in red LEDs
213#define userio_toggle_leds_green(baseaddr, mask)    Xil_Out32(baseaddr+W3_USERIO_SLV_REG4_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG4_OFFSET) ^ mask)) //!< Toggles the state of bits selected by mask in green LEDs
214#define userio_toggle_leds_rf(baseaddr, mask)       Xil_Out32(baseaddr+W3_USERIO_SLV_REG5_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG5_OFFSET) ^ mask)) //!< Toggles the state of bits selected by mask in RF LEDs
215/** @}*/
216
217/** \defgroup userio_masks Masks for user IO elements
218 *  \addtogroup userio_masks
219 * @{
220 */
221
222//reg1/reg2 masks
223#define W3_USERIO_HEXDISP_DP            0x100 //!< Mask for decimal point LEDs on hex displays
224
225//reg5 masks
226#define W3_USERIO_RFA_LED_GREEN         0x1 //!< Mask for green LED near RF A
227#define W3_USERIO_RFA_LED_RED           0x2 //!< Mask for red LED near RF A
228#define W3_USERIO_RFB_LED_GREEN         0x4 //!< Mask for green LED near RF B
229#define W3_USERIO_RFB_LED_RED           0x8 //!< Mask for red LED near RF B
230
231//reg6 masks
232#define W3_USERIO_PB_U  0x40 //!< Mask for up push button
233#define W3_USERIO_PB_M  0x20 //!< Mask for middle push button
234#define W3_USERIO_PB_D  0x10 //!< Mask for down push button
235#define W3_USERIO_DIPSW 0x0F //!< Mask for 4 positions of DIP switch
236/** @}*/
237
238/** \defgroup dna_read Reading FPGA DNA
239Every Virtex-6 FPGA has a unique "DNA" value embedded in the device. The w3_userio core implements logic to read this value into software-accessible registers. The
240DNA value is 56 bits, so two 32-bit registers are used to store the full value.
241
242<b>Hardware requirements:</b>
243<ul>
244<li>A clock signal slower than 100MHz must be connected to the w3_userio core DNA_Port_Clk port
245<li>The w3_userio core parameter INCLUDE_DNA_READ_LOGIC must be enabled
246</ul>
247If both requirements aren't met the DNA register values are undefined.
248
249The FPGA DNA value is also stored in the WARP v3 board EEPROM. Refer to the user guide EEPROM page for details.
250 *  \addtogroup dna_read
251 * @{
252 */
253#define userio_read_fpga_dna_lsb(baseaddr)  Xil_In32(baseaddr+W3_USERIO_SLV_REG10_OFFSET) //!< Returns the 32 LSB of the FPGA DNA
254#define userio_read_fpga_dna_msb(baseaddr)  Xil_In32(baseaddr+W3_USERIO_SLV_REG11_OFFSET) //!< Returns the 24 MSB of the FPGA DNA
255/** @}*/
256
257#endif /** W3_USERIO_H */
258
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