1 | //---------------------------------------------------------------------------- |
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2 | // user_logic.v - module |
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3 | //---------------------------------------------------------------------------- |
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4 | // |
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5 | // *************************************************************************** |
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6 | // ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. ** |
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7 | // ** ** |
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8 | // ** Xilinx, Inc. ** |
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9 | // ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** |
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10 | // ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** |
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11 | // ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** |
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12 | // ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** |
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13 | // ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** |
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14 | // ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** |
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15 | // ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** |
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16 | // ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** |
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17 | // ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** |
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18 | // ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** |
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19 | // ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** |
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20 | // ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** |
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21 | // ** FOR A PARTICULAR PURPOSE. ** |
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22 | // ** ** |
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23 | // *************************************************************************** |
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24 | // |
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25 | //---------------------------------------------------------------------------- |
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26 | // Filename: user_logic.v |
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27 | // Version: 1.00.a |
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28 | // Description: User logic module. |
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29 | // Date: Fri Nov 09 20:37:15 2012 (by Create and Import Peripheral Wizard) |
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30 | // Verilog Standard: Verilog-2001 |
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31 | //---------------------------------------------------------------------------- |
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32 | // Naming Conventions: |
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33 | // active low signals: "*_n" |
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34 | // clock signals: "clk", "clk_div#", "clk_#x" |
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35 | // reset signals: "rst", "rst_n" |
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36 | // generics: "C_*" |
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37 | // user defined types: "*_TYPE" |
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38 | // state machine next state: "*_ns" |
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39 | // state machine current state: "*_cs" |
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40 | // combinatorial signals: "*_com" |
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41 | // pipelined or register delay signals: "*_d#" |
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42 | // counter signals: "*cnt*" |
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43 | // clock enable signals: "*_ce" |
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44 | // internal version of output port: "*_i" |
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45 | // device pins: "*_pin" |
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46 | // ports: "- Names begin with Uppercase" |
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47 | // processes: "*_PROCESS" |
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48 | // component instantiations: "<ENTITY_>I_<#|FUNC>" |
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49 | //---------------------------------------------------------------------------- |
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50 | |
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51 | `uselib lib=unisims_ver |
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52 | `uselib lib=proc_common_v3_00_a |
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53 | |
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54 | module user_logic |
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55 | ( |
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56 | // -- ADD USER PORTS BELOW THIS LINE --------------- |
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57 | //I/O tied to top-level pins, connected to devices on board |
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58 | output [6:0] hexdisp_left, |
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59 | output hexdisp_left_dp, |
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60 | output [6:0] hexdisp_right, |
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61 | output hexdisp_right_dp, |
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62 | |
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63 | output [3:0] leds_red, |
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64 | output [3:0] leds_green, |
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65 | output rfa_led_red, |
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66 | output rfa_led_green, |
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67 | output rfb_led_red, |
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68 | output rfb_led_green, |
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69 | |
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70 | input [3:0] dipsw, |
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71 | input pb_u, |
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72 | input pb_m, |
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73 | input pb_d, |
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74 | |
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75 | //I/O optionally connected to internal signals for non-software access to user I/O |
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76 | input [6:0] usr_hexdisp_left, |
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77 | input usr_hexdisp_left_dp, |
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78 | input [6:0] usr_hexdisp_right, |
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79 | input usr_hexdisp_right_dp, |
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80 | |
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81 | input [3:0] usr_leds_red, |
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82 | input [3:0] usr_leds_green, |
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83 | |
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84 | input usr_rfa_led_red, |
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85 | input usr_rfa_led_green, |
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86 | input usr_rfb_led_red, |
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87 | input usr_rfb_led_green, |
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88 | |
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89 | output [3:0] usr_dipsw, |
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90 | output usr_pb_u, |
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91 | output usr_pb_m, |
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92 | output usr_pb_d, |
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93 | |
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94 | //Clock signal for DNA_PORT.CLK port (must be <100MHz) |
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95 | input DNA_Port_Clk, |
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96 | // -- ADD USER PORTS ABOVE THIS LINE --------------- |
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97 | |
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98 | // -- DO NOT EDIT BELOW THIS LINE ------------------ |
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99 | // -- Bus protocol ports, do not add to or delete |
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100 | input Bus2IP_Clk, |
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101 | input Bus2IP_Resetn, |
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102 | input [C_SLV_DWIDTH-1 : 0] Bus2IP_Data, |
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103 | input [C_SLV_DWIDTH/8-1 : 0] Bus2IP_BE, |
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104 | input [C_NUM_REG-1 : 0] Bus2IP_RdCE, |
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105 | input [C_NUM_REG-1 : 0] Bus2IP_WrCE, |
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106 | output [C_SLV_DWIDTH-1 : 0] IP2Bus_Data, |
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107 | output IP2Bus_RdAck, |
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108 | output IP2Bus_WrAck, |
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109 | output IP2Bus_Error |
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110 | // -- DO NOT EDIT ABOVE THIS LINE ------------------ |
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111 | ); // user_logic |
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112 | |
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113 | // -- ADD USER PARAMETERS BELOW THIS LINE ------------ |
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114 | parameter HEXDISP_ACTIVE_HIGH = 0; |
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115 | parameter INCLUDE_DNA_READ_LOGIC = 1; |
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116 | // -- ADD USER PARAMETERS ABOVE THIS LINE ------------ |
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117 | |
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118 | // -- DO NOT EDIT BELOW THIS LINE -------------------- |
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119 | // -- Bus protocol parameters, do not add to or delete |
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120 | parameter C_NUM_REG = 13; |
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121 | parameter C_SLV_DWIDTH = 32; |
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122 | // -- DO NOT EDIT ABOVE THIS LINE -------------------- |
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123 | |
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124 | //---------------------------------------------------------------------------- |
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125 | // Implementation |
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126 | //---------------------------------------------------------------------------- |
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127 | |
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128 | // --USER nets declarations added here, as needed for user logic |
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129 | |
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130 | // Nets for user logic slave model s/w accessible register example |
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131 | reg [C_SLV_DWIDTH-1 : 0] slv_reg0; |
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132 | reg [C_SLV_DWIDTH-1 : 0] slv_reg1; |
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133 | reg [C_SLV_DWIDTH-1 : 0] slv_reg2; |
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134 | reg [C_SLV_DWIDTH-1 : 0] slv_reg3; |
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135 | reg [C_SLV_DWIDTH-1 : 0] slv_reg4; |
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136 | reg [C_SLV_DWIDTH-1 : 0] slv_reg5; |
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137 | reg [C_SLV_DWIDTH-1 : 0] slv_reg6; |
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138 | reg [C_SLV_DWIDTH-1 : 0] slv_reg7; |
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139 | reg [C_SLV_DWIDTH-1 : 0] slv_reg8; |
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140 | reg [C_SLV_DWIDTH-1 : 0] slv_reg9; |
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141 | reg [C_SLV_DWIDTH-1 : 0] slv_reg10; |
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142 | reg [C_SLV_DWIDTH-1 : 0] slv_reg11; |
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143 | reg [C_SLV_DWIDTH-1 : 0] slv_reg12; |
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144 | wire [12 : 0] slv_reg_write_sel; |
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145 | wire [12 : 0] slv_reg_read_sel; |
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146 | reg [C_SLV_DWIDTH-1 : 0] slv_ip2bus_data; |
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147 | wire slv_read_ack; |
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148 | wire slv_write_ack; |
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149 | integer byte_index, bit_index; |
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150 | |
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151 | // USER logic implementation added here |
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152 | |
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153 | // ------------------------------------------------------ |
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154 | // Example code to read/write user logic slave model s/w accessible registers |
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155 | // |
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156 | // Note: |
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157 | // The example code presented here is to show you one way of reading/writing |
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158 | // software accessible registers implemented in the user logic slave model. |
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159 | // Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond |
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160 | // to one software accessible register by the top level template. For example, |
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161 | // if you have four 32 bit software accessible registers in the user logic, |
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162 | // you are basically operating on the following memory mapped registers: |
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163 | // |
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164 | // Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register |
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165 | // "1000" C_BASEADDR + 0x0 |
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166 | // "0100" C_BASEADDR + 0x4 |
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167 | // "0010" C_BASEADDR + 0x8 |
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168 | // "0001" C_BASEADDR + 0xC |
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169 | // |
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170 | // ------------------------------------------------------ |
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171 | |
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172 | assign |
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173 | slv_reg_write_sel = Bus2IP_WrCE[12:0], |
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174 | slv_reg_read_sel = Bus2IP_RdCE[12:0], |
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175 | slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[1] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3] || Bus2IP_WrCE[4] || Bus2IP_WrCE[5] || Bus2IP_WrCE[6] || Bus2IP_WrCE[7] || Bus2IP_WrCE[8] || Bus2IP_WrCE[9] || Bus2IP_WrCE[10] || Bus2IP_WrCE[11] || Bus2IP_WrCE[12], |
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176 | slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3] || Bus2IP_RdCE[4] || Bus2IP_RdCE[5] || Bus2IP_RdCE[6] || Bus2IP_RdCE[7] || Bus2IP_RdCE[8] || Bus2IP_RdCE[9] || Bus2IP_RdCE[10] || Bus2IP_RdCE[11] || Bus2IP_RdCE[12]; |
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177 | |
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178 | // implement slave model register(s) |
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179 | always @( posedge Bus2IP_Clk ) |
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180 | begin |
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181 | |
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182 | if ( Bus2IP_Resetn == 1'b0 ) |
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183 | begin |
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184 | slv_reg0 <= 32'h3F000000; //Defaults: hex map mode on for both displays, RF LEDs controlled by usr_ ports |
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185 | slv_reg1 <= 0; |
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186 | slv_reg2 <= 0; |
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187 | slv_reg3 <= 0; |
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188 | slv_reg4 <= 0; |
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189 | slv_reg5 <= 0; |
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190 | slv_reg6 <= 0; |
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191 | slv_reg7 <= 0; |
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192 | slv_reg8 <= 0; |
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193 | slv_reg9 <= 0; |
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194 | slv_reg10 <= 0; |
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195 | slv_reg11 <= 0; |
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196 | slv_reg12 <= 0; |
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197 | end |
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198 | else |
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199 | case ( slv_reg_write_sel ) |
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200 | 13'b1000000000000 : |
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201 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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202 | if ( Bus2IP_BE[byte_index] == 1 ) |
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203 | slv_reg0[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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204 | 13'b0100000000000 : |
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205 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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206 | if ( Bus2IP_BE[byte_index] == 1 ) |
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207 | slv_reg1[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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208 | 13'b0010000000000 : |
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209 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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210 | if ( Bus2IP_BE[byte_index] == 1 ) |
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211 | slv_reg2[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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212 | 13'b0001000000000 : |
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213 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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214 | if ( Bus2IP_BE[byte_index] == 1 ) |
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215 | slv_reg3[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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216 | 13'b0000100000000 : |
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217 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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218 | if ( Bus2IP_BE[byte_index] == 1 ) |
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219 | slv_reg4[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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220 | 13'b0000010000000 : |
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221 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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222 | if ( Bus2IP_BE[byte_index] == 1 ) |
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223 | slv_reg5[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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224 | 13'b0000001000000 : |
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225 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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226 | if ( Bus2IP_BE[byte_index] == 1 ) |
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227 | slv_reg6[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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228 | 13'b0000000100000 : |
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229 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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230 | if ( Bus2IP_BE[byte_index] == 1 ) |
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231 | slv_reg7[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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232 | 13'b0000000010000 : |
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233 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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234 | if ( Bus2IP_BE[byte_index] == 1 ) |
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235 | slv_reg8[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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236 | 13'b0000000001000 : |
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237 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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238 | if ( Bus2IP_BE[byte_index] == 1 ) |
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239 | slv_reg9[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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240 | 13'b0000000000100 : |
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241 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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242 | if ( Bus2IP_BE[byte_index] == 1 ) |
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243 | slv_reg10[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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244 | 13'b0000000000010 : |
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245 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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246 | if ( Bus2IP_BE[byte_index] == 1 ) |
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247 | slv_reg11[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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248 | 13'b0000000000001 : |
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249 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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250 | if ( Bus2IP_BE[byte_index] == 1 ) |
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251 | slv_reg12[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; |
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252 | default : begin |
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253 | slv_reg0 <= slv_reg0; |
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254 | slv_reg1 <= slv_reg1; |
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255 | slv_reg2 <= slv_reg2; |
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256 | slv_reg3 <= slv_reg3; |
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257 | slv_reg4 <= slv_reg4; |
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258 | slv_reg5 <= slv_reg5; |
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259 | slv_reg6 <= slv_reg6; |
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260 | slv_reg7 <= slv_reg7; |
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261 | slv_reg8 <= slv_reg8; |
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262 | slv_reg9 <= slv_reg9; |
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263 | slv_reg10 <= slv_reg10; |
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264 | slv_reg11 <= slv_reg11; |
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265 | slv_reg12 <= slv_reg12; |
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266 | end |
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267 | endcase |
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268 | |
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269 | end // SLAVE_REG_WRITE_PROC |
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270 | |
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271 | wire pb_u_db; |
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272 | wire pb_m_db; |
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273 | wire pb_d_db; |
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274 | wire [3:0] dipsw_db; |
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275 | reg [56:0] fpga_dna_value = 57'b0; |
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276 | |
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277 | // implement slave model register read mux |
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278 | always @* |
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279 | begin |
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280 | |
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281 | case ( slv_reg_read_sel ) |
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282 | 13'b1000000000000 : slv_ip2bus_data <= slv_reg0; |
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283 | 13'b0100000000000 : slv_ip2bus_data <= slv_reg1; |
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284 | 13'b0010000000000 : slv_ip2bus_data <= slv_reg2; |
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285 | 13'b0001000000000 : slv_ip2bus_data <= slv_reg3; |
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286 | 13'b0000100000000 : slv_ip2bus_data <= slv_reg4; |
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287 | 13'b0000010000000 : slv_ip2bus_data <= slv_reg5; |
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288 | 13'b0000001000000 : slv_ip2bus_data <= {25'b0, pb_u_db, pb_m_db, pb_d_db, dipsw_db}; |
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289 | 13'b0000000100000 : slv_ip2bus_data <= slv_reg7; |
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290 | 13'b0000000010000 : slv_ip2bus_data <= slv_reg8; |
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291 | 13'b0000000001000 : slv_ip2bus_data <= slv_reg9; |
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292 | 13'b0000000000100 : slv_ip2bus_data <= slv_reg10; |
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293 | 13'b0000000000010 : slv_ip2bus_data <= fpga_dna_value[56:25];//25:56]; //32 LSB |
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294 | 13'b0000000000001 : slv_ip2bus_data <= {7'b0, fpga_dna_value[24:0]};//0:24]}; //25 MSB |
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295 | default : slv_ip2bus_data <= 0; |
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296 | endcase |
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297 | |
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298 | end // SLAVE_REG_READ_PROC |
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299 | |
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300 | // ------------------------------------------------------------ |
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301 | // Example code to drive IP to Bus signals |
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302 | // ------------------------------------------------------------ |
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303 | |
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304 | assign IP2Bus_Data = (slv_read_ack == 1'b1) ? slv_ip2bus_data : 0 ; |
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305 | assign IP2Bus_WrAck = slv_write_ack; |
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306 | assign IP2Bus_RdAck = slv_read_ack; |
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307 | assign IP2Bus_Error = 0; |
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308 | |
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309 | //User IO Implementation |
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310 | /* Address map: |
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311 | HDL is coded [31:0], adopting Xilinx's convention for AXI IPIF cores |
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312 | All registers are 32-bits |
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313 | regX[31] maps to 0x80000000 in C driver |
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314 | regX[0] maps to 0x00000001 in C driver |
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315 | |
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316 | 0: Control RW |
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317 | [31:30] = Reserved |
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318 | [ 29] = Left hex data mode (0=user supplies bit-per-segment; 1=user supplies 4-bit hex) 0x20000000 |
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319 | [ 28] = Right hex data mode (0=user supplies bit-per-segment; 1=user supplies 4-bit hex) 0x10000000 |
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320 | Control source for LEDs: 0=software controlled, 1=usr_ port controlled |
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321 | [27:24] = {rfb_red rfb_green rfa_red rfa_green} 0x0F000000 |
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322 | [23:16] = {leds_red leds_green} 0x00FF0000 |
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323 | [15: 8] = {hexdisp_left{a b c d e f g dp}} 0x0000FF00 |
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324 | [ 7: 0] = {hexdisp_right{a b c d e f g dp}} 0x000000FF |
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325 | 1: Left hex display RW |
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326 | [31: 9] = reserved |
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327 | [ 8] = DP (controlled directly; doesn't depend on data mode) 0x100 |
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328 | [ 6: 0] = Data value ([6:4] ignored when data mode = 1) 0x03F |
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329 | 2: Right hex display RW |
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330 | [31: 9] = reserved |
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331 | [ 8] = DP (controlled directly; doesn't depend on data mode) 0x100 |
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332 | [ 6: 0] = Data value ([6:4] ignored when data mode = 1) 0x03F |
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333 | 3: Red user LEDs RW |
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334 | [31: 4] = reserved |
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335 | [ 3: 0] = Data value (1=LED illuminated) 0xF, with 0x1 mapped to lowest LED |
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336 | 4: Green user LEDs RW |
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337 | [31: 4] = reserved |
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338 | [ 3: 0] = Data value (1=LED illuminated) 0xF, with 0x1 mapped to lowest LED |
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339 | 5: RF LEDs RW |
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340 | [31: 4] = reserved |
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341 | [ 3] = rfb_red 0x8 |
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342 | [ 2] = rfb_green 0x4 |
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343 | [ 1] = rfa_red 0x2 |
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344 | [ 0] = rfa_green 0x1 |
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345 | 6: Switch/button inputs RO |
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346 | [31: 7] = reserved |
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347 | [ 6] = pb_up 0x40 |
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348 | [ 5] = pb_mid 0x20 |
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349 | [ 4] = pb_down 0x10 |
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350 | [ 3: 0] = DIP switch 0x0F (with 0x1 mapped to right-most switch) |
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351 | |
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352 | 7: PWM Gen Param: PWM period RW |
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353 | [31:16] = PWN period |
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354 | [15: 0] = PWM output deassert thresh |
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355 | |
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356 | 8: PWM Gen Param: PWM output deassert thresh RW |
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357 | [31:29] = reserved |
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358 | [28: 0] = |
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359 | |
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360 | 9: PWM Gen Param: PWM ramp step RW |
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361 | [31] = ramp enabled |
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362 | [30:16] = pwm_param_ramp_min |
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363 | [15: 0] = pwm_param_ramp_max |
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364 | |
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365 | 10: HW Output control sel RW |
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366 | [31:28] = Reserved |
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367 | HW Control source for LEDs: 0=usr_ ports, 1=pwm gen (same ctrlSrc masks as reg0) |
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368 | [27:24] = {rfb_red rfb_green rfa_red rfa_green} 0x0F000000 |
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369 | [23:16] = {leds_red leds_green} 0x00FF0000 |
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370 | [15: 8] = {hexdisp_left{a b c d e f g dp}} 0x0000FF00 |
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371 | [ 7: 0] = {hexdisp_right{a b c d e f g dp}} 0x000000FF |
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372 | |
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373 | 11: FPGA DNA LSB |
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374 | [31: 0] = 32LSB of FPGA DNA |
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375 | |
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376 | 12: FPGA DNA MSB |
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377 | [31:25] = reserved |
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378 | [24: 0] = FPGA DNA 25MSB |
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379 | |
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380 | |
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381 | */ |
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382 | integer ii; |
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383 | |
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384 | wire [27:0] all_outputs_ctrl_source; |
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385 | wire [27:0] all_outputs_hw_ctrl_source; |
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386 | wire [27:0] all_outputs_sw_val; |
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387 | wire [27:0] all_outputs_hw_val; |
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388 | reg [27:0] all_outputs; |
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389 | reg [27:0] all_outputs_d1; |
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390 | |
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391 | reg [27:0] all_outputs_d2; |
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392 | |
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393 | wire [6:0] leftHex_mapped; |
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394 | wire [6:0] rightHex_mapped; |
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395 | |
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396 | wire [6:0] leftHex_sw_val; |
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397 | wire [6:0] rightHex_sw_val; |
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398 | |
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399 | reg [7:0] pb_u_d = 0; |
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400 | reg [7:0] pb_m_d = 0; |
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401 | reg [7:0] pb_d_d = 0; |
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402 | reg [7:0] dipsw_d0 = 0; |
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403 | reg [7:0] dipsw_d1 = 0; |
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404 | reg [7:0] dipsw_d2 = 0; |
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405 | reg [7:0] dipsw_d3 = 0; |
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406 | |
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407 | |
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408 | //PWM generator |
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409 | reg [9:0] pwm_clock_counter = 0; |
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410 | wire pwm_clock_en; |
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411 | assign pwm_clock_en = (pwm_clock_counter == 0); |
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412 | |
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413 | wire [15:0] pwm_param_period; |
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414 | wire [15:0] pwm_param_thresh_sw; |
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415 | wire [15:0] pwm_param_thresh; |
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416 | reg [15:0] pwm_param_thresh_d; |
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417 | |
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418 | wire pwm_param_ramp_en; |
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419 | |
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420 | wire [14:0] pwm_param_ramp_min; |
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421 | wire [15:0] pwm_param_ramp_max; |
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422 | |
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423 | wire pwm_ramp_count_dir_toggle; |
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424 | reg pwm_ramp_count_dir_toggle_d = 0; |
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425 | |
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426 | reg pwm_ramp_count_dir = 0; |
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427 | |
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428 | assign pwm_ramp_count_dir_toggle = (((pwm_ramp_counter > pwm_param_ramp_max) | (pwm_ramp_counter < pwm_param_ramp_min))); |
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429 | |
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430 | assign pwm_param_period = slv_reg7[31:16]; |
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431 | assign pwm_param_thresh_sw = slv_reg7[15:0]; |
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432 | |
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433 | assign pwm_param_ramp_en = slv_reg9[31]; |
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434 | assign pwm_param_ramp_min = slv_reg9[30:16]; |
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435 | assign pwm_param_ramp_max = slv_reg9[15:0]; |
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436 | |
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437 | assign pwm_param_thresh = pwm_param_ramp_en ? pwm_ramp_counter : pwm_param_thresh_sw; |
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438 | |
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439 | reg [15:0] pwm_period_counter = 0; |
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440 | reg [15:0] pwm_ramp_counter = 0; |
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441 | |
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442 | reg pwm_out = 0; |
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443 | |
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444 | always @(posedge Bus2IP_Clk) |
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445 | begin |
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446 | pwm_clock_counter <= pwm_clock_counter + 1; |
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447 | |
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448 | if(pwm_period_counter >= pwm_param_period) |
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449 | pwm_period_counter <= 0; |
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450 | else if(pwm_clock_en) |
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451 | pwm_period_counter <= pwm_period_counter + 1; |
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452 | |
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453 | pwm_param_thresh_d <= pwm_param_thresh; |
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454 | |
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455 | pwm_out <= (pwm_period_counter < pwm_param_thresh_d); |
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456 | end |
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457 | |
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458 | always @(posedge Bus2IP_Clk) |
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459 | begin |
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460 | pwm_ramp_count_dir_toggle_d <= pwm_ramp_count_dir_toggle; |
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461 | |
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462 | //pwm_ramp_count_dir=0 counts up |
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463 | if(~pwm_param_ramp_en) |
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464 | pwm_ramp_counter <= {1'b0,pwm_param_ramp_min}; |
---|
465 | else if(pwm_clock_en & (pwm_period_counter==0)) |
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466 | if(pwm_ramp_count_dir) |
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467 | pwm_ramp_counter <= pwm_ramp_counter + 16'hFFFE; |
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468 | else |
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469 | pwm_ramp_counter <= pwm_ramp_counter + 1'b1; |
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470 | |
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471 | if(~pwm_param_ramp_en) |
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472 | pwm_ramp_count_dir <= 0; |
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473 | else if(pwm_ramp_count_dir_toggle & ~pwm_ramp_count_dir_toggle_d) |
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474 | pwm_ramp_count_dir <= ~pwm_ramp_count_dir; |
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475 | |
---|
476 | end |
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477 | |
---|
478 | |
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479 | //Shift registers for debouncing mechanical inputs |
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480 | always @(posedge Bus2IP_Clk) |
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481 | begin |
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482 | pb_u_d[7:0] <= {pb_u_d[6:0], pb_u}; |
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483 | pb_m_d[7:0] <= {pb_m_d[6:0], pb_m}; |
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484 | pb_d_d[7:0] <= {pb_d_d[6:0], pb_d}; |
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485 | dipsw_d0[7:0] <= {dipsw_d0[6:0], dipsw[0]}; |
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486 | dipsw_d1[7:0] <= {dipsw_d1[6:0], dipsw[1]}; |
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487 | dipsw_d2[7:0] <= {dipsw_d2[6:0], dipsw[2]}; |
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488 | dipsw_d3[7:0] <= {dipsw_d3[6:0], dipsw[3]}; |
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489 | end |
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490 | |
---|
491 | //Assert debounced signals only if inputs are high 8 consecutive cycles |
---|
492 | assign pb_u_db = (pb_u_d == 8'hff); |
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493 | assign pb_m_db = (pb_m_d == 8'hff); |
---|
494 | assign pb_d_db = (pb_d_d == 8'hff); |
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495 | |
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496 | //Swap MSB:LSB here, to undo endian swaps relative to schematic labels |
---|
497 | assign dipsw_db = {(dipsw_d0==8'hff), (dipsw_d1==8'hff), (dipsw_d2==8'hff), (dipsw_d3==8'hff)}; |
---|
498 | |
---|
499 | //Logic to map 4-bit hex value to 7-bit value for hex display |
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500 | sevenSegmentMap leftHexMap (.data(slv_reg1[3:0]), .disp(leftHex_mapped)); |
---|
501 | sevenSegmentMap rightHexMap (.data(slv_reg2[3:0]), .disp(rightHex_mapped)); |
---|
502 | |
---|
503 | //Select which 7-bit value is used as the software-supplied value for hex displays |
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504 | // User either supplies 4-bit value to be interpretted as hex value |
---|
505 | // or raw 7-bit (bit-per-diode) value |
---|
506 | assign leftHex_sw_val = slv_reg0[29] ? leftHex_mapped : slv_reg1[6:0]; |
---|
507 | assign rightHex_sw_val = slv_reg0[28] ? rightHex_mapped : slv_reg2[6:0]; |
---|
508 | |
---|
509 | //Extract the mux control values from the software register |
---|
510 | assign all_outputs_ctrl_source = slv_reg0[27:0]; |
---|
511 | assign all_outputs_hw_ctrl_source = slv_reg10[27:0]; |
---|
512 | |
---|
513 | //Extract and concatenate the software-controlled output values |
---|
514 | assign all_outputs_sw_val[27:0] = { |
---|
515 | slv_reg5[3], //[27] rgb_red LED |
---|
516 | slv_reg5[2], //[26] rgb_green LED |
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517 | slv_reg5[1], //[25] rga_red LED |
---|
518 | slv_reg5[0], //[24] rga_green LED |
---|
519 | slv_reg4[3:0], //[23:20] green LEDs |
---|
520 | slv_reg3[3:0], //[19:16] red LEDs |
---|
521 | slv_reg2[8], //[15] right hex DP |
---|
522 | rightHex_sw_val[6:0], //[14:8] right hex mapped |
---|
523 | slv_reg1[8], //[7] left hex DP |
---|
524 | leftHex_sw_val[6:0] //[6:0] left hex mapped |
---|
525 | }; |
---|
526 | |
---|
527 | //Concatenate the top-level inputs for hardware-controlled output values |
---|
528 | assign all_outputs_hw_val[27:24] = {usr_rfb_led_red, usr_rfb_led_green, usr_rfa_led_red, usr_rfa_led_green}; |
---|
529 | assign all_outputs_hw_val[23:16] = {usr_leds_green, usr_leds_red}; |
---|
530 | assign all_outputs_hw_val[15:8] = {usr_hexdisp_right_dp, usr_hexdisp_right}; |
---|
531 | assign all_outputs_hw_val[7:0] = {usr_hexdisp_left_dp, usr_hexdisp_left}; |
---|
532 | |
---|
533 | //Mux between hardware and software control for each output |
---|
534 | // Source control = 0 -> Software register bit controls output |
---|
535 | // Source control = 1 -> Hardware control |
---|
536 | // Hardware control mode = 0 -> usr_ port controls |
---|
537 | // Hardware control mode = 1 -> pwm module controls |
---|
538 | always @* |
---|
539 | begin |
---|
540 | for(ii=0; ii<28; ii=ii+1) |
---|
541 | all_outputs[ii] = all_outputs_ctrl_source[ii] ? (all_outputs_hw_ctrl_source[ii] ? pwm_out : all_outputs_hw_val[ii]) : all_outputs_sw_val[ii]; |
---|
542 | end |
---|
543 | |
---|
544 | always @(posedge Bus2IP_Clk) |
---|
545 | begin |
---|
546 | all_outputs_d1 <= all_outputs; |
---|
547 | |
---|
548 | // HDL parameter HEXDISP_ACTIVE_HIGH defines the type at build-time |
---|
549 | // User values are always interpreted as 1==illuminated |
---|
550 | // Mux on active high/low here so _d2 DFFs can be packed into IOBs |
---|
551 | all_outputs_d2[15:0] <= HEXDISP_ACTIVE_HIGH ? all_outputs_d1[15:0] : ~all_outputs_d1[15:0]; |
---|
552 | all_outputs_d2[27:16] <= all_outputs_d1[27:16]; |
---|
553 | end |
---|
554 | |
---|
555 | //Map the mux outputs to the top-level outputs |
---|
556 | assign {rfb_led_red, rfb_led_green, rfa_led_red, rfa_led_green} = all_outputs_d2[27:24]; |
---|
557 | |
---|
558 | assign leds_green[3:0] = all_outputs_d2[23:20]; |
---|
559 | assign leds_red[3:0] = all_outputs_d2[19:16]; |
---|
560 | |
---|
561 | assign hexdisp_left_dp = all_outputs_d2[7]; |
---|
562 | assign hexdisp_left[6:0] = all_outputs_d2[6:0]; |
---|
563 | |
---|
564 | assign hexdisp_right_dp = all_outputs_d2[15]; |
---|
565 | assign hexdisp_right[6:0] = all_outputs_d2[14:8]; |
---|
566 | |
---|
567 | //Assign the usr_ output ports to the de-bounced top-level inputs |
---|
568 | assign usr_dipsw[3:0] = dipsw_db[3:0]; |
---|
569 | assign usr_pb_u = pb_u_db; |
---|
570 | assign usr_pb_m = pb_m_db; |
---|
571 | assign usr_pb_d = pb_d_db; |
---|
572 | |
---|
573 | generate |
---|
574 | if(INCLUDE_DNA_READ_LOGIC) begin |
---|
575 | wire dna_port_read, dna_port_shift, dna_port_clk_gated, dna_port_dout; |
---|
576 | //Instantiate the DNA_PORT module, for reading the FPGA's unique ID |
---|
577 | // Two MSB are always [1 0]? Accordint to isim at least |
---|
578 | DNA_PORT #(.SIM_DNA_VALUE(57'h123456789abcdef)) dna_port_inst ( |
---|
579 | .DIN(1'b0), |
---|
580 | .READ(dna_port_read), |
---|
581 | .SHIFT(dna_port_shift), |
---|
582 | .CLK(dna_port_clk_gated), |
---|
583 | .DOUT(dna_port_dout) |
---|
584 | ); |
---|
585 | |
---|
586 | reg [6:0] dna_read_counter = 7'b0; |
---|
587 | |
---|
588 | //Only clock the DNA_PORT primitive while actively shifting data out |
---|
589 | assign dna_port_clk_gated = (DNA_Port_Clk & (dna_read_counter>7'd60) & (dna_read_counter<7'h7f)); |
---|
590 | |
---|
591 | //Count-limited counter, that starts at configuration and runs exactly once |
---|
592 | always @(posedge DNA_Port_Clk) |
---|
593 | begin |
---|
594 | if(dna_read_counter == 7'h7f) |
---|
595 | dna_read_counter <= 7'h7f; |
---|
596 | else |
---|
597 | dna_read_counter <= dna_read_counter + 1; |
---|
598 | end |
---|
599 | |
---|
600 | //dna read states, as function of dna_read_counter value: |
---|
601 | // 0-63: Do nothing (just in case things needs to settle before DNA_PORT is accessible) |
---|
602 | // 64: Toggle READ signal (loads DNA value into DNA_PORT 57-bit shift register) |
---|
603 | // 65: Read DNA[0] from shift register DOUT; assert SHIFT |
---|
604 | //66-121: Read DNA[1:56] from shif register DOUT; SHIFT stays asserted |
---|
605 | // 122: De-assert SHIFT and READ |
---|
606 | |
---|
607 | assign dna_port_read = (dna_read_counter == 7'd63); |
---|
608 | assign dna_port_shift = ((dna_read_counter>= 7'd65) && (dna_read_counter<=122)); |
---|
609 | |
---|
610 | //Capture the shift register output in a single big register |
---|
611 | wire dna_capt; |
---|
612 | assign dna_capt = ((dna_read_counter>= 7'd65) && (dna_read_counter<=121)); |
---|
613 | always @(posedge DNA_Port_Clk) |
---|
614 | begin |
---|
615 | if (dna_capt) |
---|
616 | fpga_dna_value[dna_read_counter-7'd65] = dna_port_dout; |
---|
617 | end |
---|
618 | end |
---|
619 | endgenerate |
---|
620 | |
---|
621 | endmodule |
---|
622 | |
---|
623 | |
---|
624 | module sevenSegmentMap |
---|
625 | ( |
---|
626 | input [3:0] data, |
---|
627 | output reg [6:0] disp |
---|
628 | ); |
---|
629 | |
---|
630 | always @(data[3:0]) |
---|
631 | case (data[3:0]) |
---|
632 | 4'b0000 : disp <= ~(7'b1000000); // 0 |
---|
633 | 4'b0001 : disp <= ~(7'b1111001); // 1 |
---|
634 | 4'b0010 : disp <= ~(7'b0100100); // 2 |
---|
635 | 4'b0011 : disp <= ~(7'b0110000); // 3 |
---|
636 | 4'b0100 : disp <= ~(7'b0011001); // 4 |
---|
637 | 4'b0101 : disp <= ~(7'b0010010); // 5 |
---|
638 | 4'b0110 : disp <= ~(7'b0000010); // 6 |
---|
639 | 4'b0111 : disp <= ~(7'b1111000); // 7 |
---|
640 | 4'b1000 : disp <= ~(7'b0000000); // 8 |
---|
641 | 4'b1001 : disp <= ~(7'b0010000); // 9 |
---|
642 | 4'b1010 : disp <= ~(7'b0001000); // A |
---|
643 | 4'b1011 : disp <= ~(7'b0000011); // b |
---|
644 | 4'b1100 : disp <= ~(7'b1000110); // C |
---|
645 | 4'b1101 : disp <= ~(7'b0100001); // d |
---|
646 | 4'b1110 : disp <= ~(7'b0000110); // E |
---|
647 | 4'b1111 : disp <= ~(7'b0001110); // F |
---|
648 | default : disp <= (7'b0000000); |
---|
649 | endcase |
---|
650 | |
---|
651 | endmodule |
---|