source: PlatformSupport/CustomPeripherals/pcores/w3_userio_axi_v1_02_a/hdl/verilog/user_logic.v

//----------------------------------------------------------------------------
// user_logic.v - module
//----------------------------------------------------------------------------
//
// ***************************************************************************
// ** Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.            **
// **                                                                       **
// ** Xilinx, Inc.                                                          **
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// ** SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,        **
// ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,        **
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// ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE               **
// ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR        **
// ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF       **
// ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS       **
// ** FOR A PARTICULAR PURPOSE.                                             **
// **                                                                       **
// ***************************************************************************
//
//----------------------------------------------------------------------------
// Filename:          user_logic.v
// Version:           1.00.a
// Description:       User logic module.
// Date:              Fri Nov 09 20:37:15 2012 (by Create and Import Peripheral Wizard)
// Verilog Standard:  Verilog-2001
//----------------------------------------------------------------------------
// Naming Conventions:
//   active low signals:                    "*_n"
//   clock signals:                         "clk", "clk_div#", "clk_#x"
//   reset signals:                         "rst", "rst_n"
//   generics:                              "C_*"
//   user defined types:                    "*_TYPE"
//   state machine next state:              "*_ns"
//   state machine current state:           "*_cs"
//   combinatorial signals:                 "*_com"
//   pipelined or register delay signals:   "*_d#"
//   counter signals:                       "*cnt*"
//   clock enable signals:                  "*_ce"
//   internal version of output port:       "*_i"
//   device pins:                           "*_pin"
//   ports:                                 "- Names begin with Uppercase"
//   processes:                             "*_PROCESS"
//   component instantiations:              "<ENTITY_>I_<#|FUNC>"
//----------------------------------------------------------------------------

`uselib lib=unisims_ver
`uselib lib=proc_common_v3_00_a

module user_logic
(
  // -- ADD USER PORTS BELOW THIS LINE ---------------
    //I/O tied to top-level pins, connected to devices on board
    output [6:0]    hexdisp_left,
    output          hexdisp_left_dp,
    output [6:0]    hexdisp_right,
    output          hexdisp_right_dp,

    output [3:0]    leds_red,
    output [3:0]    leds_green,
    output          rfa_led_red,
    output          rfa_led_green,
    output          rfb_led_red,
    output          rfb_led_green,

    input [3:0]     dipsw,
    input           pb_u,
    input           pb_m,
    input           pb_d,
    
    inout [(C_DBG_HDR_WIDTH-1):0] dbg_hdr,

    //I/O optionally connected to internal signals for non-software access to user I/O
    input [6:0]     usr_hexdisp_left,
    input           usr_hexdisp_left_dp,
    input [6:0]     usr_hexdisp_right,
    input           usr_hexdisp_right_dp,

    input [3:0]     usr_leds_red,
    input [3:0]     usr_leds_green,

    input           usr_rfa_led_red,
    input           usr_rfa_led_green,
    input           usr_rfb_led_red,
    input           usr_rfb_led_green,

    output [3:0]    usr_dipsw,
    output          usr_pb_u,
    output          usr_pb_m,
    output          usr_pb_d,

    //Clock signal for DNA_PORT.CLK port (must be <100MHz)
    input           DNA_Port_Clk,
  // -- ADD USER PORTS ABOVE THIS LINE ---------------

  // -- DO NOT EDIT BELOW THIS LINE ------------------
  // -- Bus protocol ports, do not add to or delete 
input                                     Bus2IP_Clk,
input                                     Bus2IP_Resetn,
input      [C_SLV_DWIDTH-1 : 0]           Bus2IP_Data,
input      [C_SLV_DWIDTH/8-1 : 0]         Bus2IP_BE,
input      [C_NUM_REG-1 : 0]              Bus2IP_RdCE,
input      [C_NUM_REG-1 : 0]              Bus2IP_WrCE,
output     [C_SLV_DWIDTH-1 : 0]           IP2Bus_Data,
output                                    IP2Bus_RdAck,
output                                    IP2Bus_WrAck,
output                                    IP2Bus_Error
  // -- DO NOT EDIT ABOVE THIS LINE ------------------
); // user_logic

// -- ADD USER PARAMETERS BELOW THIS LINE ------------
parameter HEXDISP_ACTIVE_HIGH = 0;
parameter INCLUDE_DNA_READ_LOGIC = 1;
parameter C_DBG_HDR_WIDTH = 4;
// -- ADD USER PARAMETERS ABOVE THIS LINE ------------

// -- DO NOT EDIT BELOW THIS LINE --------------------
// -- Bus protocol parameters, do not add to or delete
parameter C_NUM_REG                      = 14;
parameter C_SLV_DWIDTH                   = 32;
// -- DO NOT EDIT ABOVE THIS LINE --------------------

//----------------------------------------------------------------------------
// Implementation
//----------------------------------------------------------------------------

  // --USER nets declarations added here, as needed for user logic

  // Nets for user logic slave model s/w accessible register example
  reg        [C_SLV_DWIDTH-1 : 0]           slv_reg0;
  reg        [C_SLV_DWIDTH-1 : 0]           slv_reg1;
  reg        [C_SLV_DWIDTH-1 : 0]           slv_reg2;
  reg        [C_SLV_DWIDTH-1 : 0]           slv_reg3;
  reg        [C_SLV_DWIDTH-1 : 0]           slv_reg4;
  reg        [C_SLV_DWIDTH-1 : 0]           slv_reg5;
  reg        [C_SLV_DWIDTH-1 : 0]           slv_reg6;
  reg        [C_SLV_DWIDTH-1 : 0]           slv_reg7;
  reg        [C_SLV_DWIDTH-1 : 0]           slv_reg8;
  reg        [C_SLV_DWIDTH-1 : 0]           slv_reg9;
  reg        [C_SLV_DWIDTH-1 : 0]           slv_reg10;
  reg        [C_SLV_DWIDTH-1 : 0]           slv_reg11;
  reg        [C_SLV_DWIDTH-1 : 0]           slv_reg12;
  reg        [C_SLV_DWIDTH-1 : 0]           slv_reg13;
  wire       [13 : 0]                       slv_reg_write_sel;
  wire       [13 : 0]                       slv_reg_read_sel;
  reg        [C_SLV_DWIDTH-1 : 0]           slv_ip2bus_data;
  wire                                      slv_read_ack;
  wire                                      slv_write_ack;
  integer                                   byte_index, bit_index;

  // USER logic implementation added here

  // ------------------------------------------------------
  // Example code to read/write user logic slave model s/w accessible registers
  // 
  // Note:
  // The example code presented here is to show you one way of reading/writing
  // software accessible registers implemented in the user logic slave model.
  // Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
  // to one software accessible register by the top level template. For example,
  // if you have four 32 bit software accessible registers in the user logic,
  // you are basically operating on the following memory mapped registers:
  // 
  //    Bus2IP_WrCE/Bus2IP_RdCE   Memory Mapped Register
  //                     "1000"   C_BASEADDR + 0x0
  //                     "0100"   C_BASEADDR + 0x4
  //                     "0010"   C_BASEADDR + 0x8
  //                     "0001"   C_BASEADDR + 0xC
  // 
  // ------------------------------------------------------

  assign
    slv_reg_write_sel = Bus2IP_WrCE[13:0],
    slv_reg_read_sel  = Bus2IP_RdCE[13:0],
    slv_write_ack     = Bus2IP_WrCE[0] || Bus2IP_WrCE[1] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3] || Bus2IP_WrCE[4] || Bus2IP_WrCE[5] || Bus2IP_WrCE[6] || Bus2IP_WrCE[7] || Bus2IP_WrCE[8] || Bus2IP_WrCE[9] || Bus2IP_WrCE[10] || Bus2IP_WrCE[11] || Bus2IP_WrCE[12] || Bus2IP_WrCE[13],
    slv_read_ack      = Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3] || Bus2IP_RdCE[4] || Bus2IP_RdCE[5] || Bus2IP_RdCE[6] || Bus2IP_RdCE[7] || Bus2IP_RdCE[8] || Bus2IP_RdCE[9] || Bus2IP_RdCE[10] || Bus2IP_RdCE[11] || Bus2IP_RdCE[12] || Bus2IP_RdCE[13];

  // implement slave model register(s)
  always @( posedge Bus2IP_Clk )
    begin

      if ( Bus2IP_Resetn == 1'b0 )
        begin
          slv_reg0 <= 32'h3F000000; //Defaults: hex map mode on for both displays, RF LEDs controlled by usr_ ports
          slv_reg1 <= 0;
          slv_reg2 <= 0;
          slv_reg3 <= 0;
          slv_reg4 <= 0;
          slv_reg5 <= 0;
          slv_reg6 <= 0;
          slv_reg7 <= 0;
          slv_reg8 <= 0;
          slv_reg9 <= 0;
          slv_reg10 <= 0;
          slv_reg11 <= 0;
          slv_reg12 <= 0;
          slv_reg13 <= 0;
        end
      else
        case ( slv_reg_write_sel )
          14'b10000000000000 :
            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
              if ( Bus2IP_BE[byte_index] == 1 )
                slv_reg0[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
          14'b01000000000000 :
            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
              if ( Bus2IP_BE[byte_index] == 1 )
                slv_reg1[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
          14'b00100000000000 :
            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
              if ( Bus2IP_BE[byte_index] == 1 )
                slv_reg2[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
          14'b00010000000000 :
            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
              if ( Bus2IP_BE[byte_index] == 1 )
                slv_reg3[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
          14'b00001000000000 :
            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
              if ( Bus2IP_BE[byte_index] == 1 )
                slv_reg4[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
          14'b00000100000000 :
            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
              if ( Bus2IP_BE[byte_index] == 1 )
                slv_reg5[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
          14'b00000010000000 :
            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
              if ( Bus2IP_BE[byte_index] == 1 )
                slv_reg6[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
          14'b00000001000000 :
            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
              if ( Bus2IP_BE[byte_index] == 1 )
                slv_reg7[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
          14'b00000000100000 :
            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
              if ( Bus2IP_BE[byte_index] == 1 )
                slv_reg8[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
          14'b00000000010000 :
            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
              if ( Bus2IP_BE[byte_index] == 1 )
                slv_reg9[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
          14'b00000000001000 :
            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
              if ( Bus2IP_BE[byte_index] == 1 )
                slv_reg10[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
          14'b00000000000100 :
            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
              if ( Bus2IP_BE[byte_index] == 1 )
                slv_reg11[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
          14'b00000000000010 :
            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
              if ( Bus2IP_BE[byte_index] == 1 )
                slv_reg12[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
          14'b00000000000001 :
            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
              if ( Bus2IP_BE[byte_index] == 1 )
                slv_reg13[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8];
          default : begin
            slv_reg0 <= slv_reg0;
            slv_reg1 <= slv_reg1;
            slv_reg2 <= slv_reg2;
            slv_reg3 <= slv_reg3;
            slv_reg4 <= slv_reg4;
            slv_reg5 <= slv_reg5;
            slv_reg6 <= slv_reg6;
            slv_reg7 <= slv_reg7;
            slv_reg8 <= slv_reg8;
            slv_reg9 <= slv_reg9;
            slv_reg10 <= slv_reg10;
            slv_reg11 <= slv_reg11;
            slv_reg12 <= slv_reg12;
            slv_reg13 <= slv_reg13;
                    end
        endcase

    end // SLAVE_REG_WRITE_PROC

    wire pb_u_db;
    wire pb_m_db;
    wire pb_d_db;
    wire [3:0] dipsw_db;
    reg [56:0] fpga_dna_value = 57'b0;

    wire [15:0] dbg_hdr_read_val;
    wire [15:0] dbg_hdr_dir;
    
  // implement slave model register read mux
  always @*
    begin 

      case ( slv_reg_read_sel )
        14'b10000000000000 : slv_ip2bus_data <= slv_reg0;
        14'b01000000000000 : slv_ip2bus_data <= slv_reg1;
        14'b00100000000000 : slv_ip2bus_data <= slv_reg2;
        14'b00010000000000 : slv_ip2bus_data <= slv_reg3;
        14'b00001000000000 : slv_ip2bus_data <= slv_reg4;
        14'b00000100000000 : slv_ip2bus_data <= slv_reg5;
        14'b00000010000000 : slv_ip2bus_data <= {25'b0, pb_u_db, pb_m_db, pb_d_db, dipsw_db};
        14'b00000001000000 : slv_ip2bus_data <= slv_reg7;
        14'b00000000100000 : slv_ip2bus_data <= slv_reg8;
        14'b00000000010000 : slv_ip2bus_data <= slv_reg9;
        14'b00000000001000 : slv_ip2bus_data <= slv_reg10;
        14'b00000000000100 : slv_ip2bus_data <= fpga_dna_value[56:25];//25:56]; //32 LSB
        14'b00000000000010 : slv_ip2bus_data <= {7'b0, fpga_dna_value[24:0]};//0:24]}; //25 MSB
        14'b00000000000001 : slv_ip2bus_data <= {slv_reg13[31:16], dbg_hdr_read_val};
        default : slv_ip2bus_data <= 0;
      endcase

    end // SLAVE_REG_READ_PROC

  // ------------------------------------------------------------
  // Example code to drive IP to Bus signals
  // ------------------------------------------------------------

assign IP2Bus_Data = (slv_read_ack == 1'b1) ? slv_ip2bus_data :  0 ;
  assign IP2Bus_WrAck = slv_write_ack;
  assign IP2Bus_RdAck = slv_read_ack;
  assign IP2Bus_Error = 0;

//User IO Implementation
    /* Address map:
        HDL is coded [31:0], adopting Xilinx's convention for AXI IPIF cores
        All registers are 32-bits
            regX[31]  maps to 0x80000000 in C driver
            regX[0]   maps to 0x00000001 in C driver

    0: Control RW
        [31:30] = Reserved
        [   29] = Left hex data mode (0=user supplies bit-per-segment; 1=user supplies 4-bit hex)   0x20000000
        [   28] = Right hex data mode (0=user supplies bit-per-segment; 1=user supplies 4-bit hex)  0x10000000
      Control source for LEDs: 0=software controlled, 1=usr_ port controlled
        [27:24] = {rfb_red rfb_green rfa_red rfa_green} 0x0F000000
        [23:16] = {leds_red leds_green}                 0x00FF0000
        [15: 8] = {hexdisp_left{a b c d e f g dp}}      0x0000FF00
        [ 7: 0] = {hexdisp_right{a b c d e f g dp}}     0x000000FF
    1: Left hex display RW
        [31: 9] = reserved
        [    8] = DP (controlled directly; doesn't depend on data mode) 0x100
        [ 6: 0] = Data value ([6:4] ignored when data mode = 1)         0x03F
    2: Right hex display RW
        [31: 9] = reserved
        [    8] = DP (controlled directly; doesn't depend on data mode) 0x100
        [ 6: 0] = Data value ([6:4] ignored when data mode = 1)         0x03F
    3: Red user LEDs RW
        [31: 4] = reserved
        [ 3: 0] = Data value (1=LED illuminated) 0xF, with 0x1 mapped to lowest LED
    4: Green user LEDs RW
        [31: 4] = reserved
        [ 3: 0] = Data value (1=LED illuminated) 0xF, with 0x1 mapped to lowest LED
    5: RF LEDs RW
        [31: 4] = reserved
        [    3] = rfb_red   0x8
        [    2] = rfb_green 0x4
        [    1] = rfa_red   0x2
        [    0] = rfa_green 0x1
    6: Switch/button inputs RO
        [31: 7] = reserved
        [    6] = pb_up         0x40
        [    5] = pb_mid        0x20
        [    4] = pb_down       0x10
        [ 3: 0] = DIP switch    0x0F (with 0x1 mapped to right-most switch)

    7: PWM Gen Param: PWM period RW
        [31:16] = PWN period
        [15: 0] = PWM output deassert thresh

    8: PWM Gen Param: PWM output deassert thresh RW
        [31:29] = reserved
        [28: 0] = 
        
    9: PWM Gen Param: PWM ramp step RW
        [31]    = ramp enabled
        [30:16] = pwm_param_ramp_min
        [15: 0] = pwm_param_ramp_max

    10: HW Output control sel RW
        [31:28] = Reserved
      HW Control source for LEDs: 0=usr_ ports, 1=pwm gen (same ctrlSrc masks as reg0)
        [27:24] = {rfb_red rfb_green rfa_red rfa_green} 0x0F000000
        [23:16] = {leds_red leds_green}                 0x00FF0000
        [15: 8] = {hexdisp_left{a b c d e f g dp}}      0x0000FF00
        [ 7: 0] = {hexdisp_right{a b c d e f g dp}}     0x000000FF

    11: FPGA DNA LSB
        [31: 0] = 32LSB of FPGA DNA

    12: FPGA DNA MSB
        [31:25] = reserved
        [24: 0] = FPGA DNA 25MSB
        
    13: Debug Header IO
        [31:16] = IOB direction control, 1 bit per pin; only C_DBG_HDR_WIDTH LSB are used
        [15: 0] = IOB data. Bits corresponding to inputs contain input values. Bits
                   corresponding to outputs contain output values. Bits corresponding to
                   unused pins contain would-be output values (whatever software last wrote).
        */
    integer ii;

    wire [27:0] all_outputs_ctrl_source;
    wire [27:0] all_outputs_hw_ctrl_source;
    wire [27:0] all_outputs_sw_val;
    wire [27:0] all_outputs_hw_val;
    reg  [27:0] all_outputs;
    reg  [27:0] all_outputs_d1;

    reg  [27:0] all_outputs_d2;     

    wire [6:0] leftHex_mapped;
    wire [6:0] rightHex_mapped;

    wire [6:0] leftHex_sw_val;
    wire [6:0] rightHex_sw_val;

    reg [7:0] pb_u_d = 0;
    reg [7:0] pb_m_d = 0;
    reg [7:0] pb_d_d = 0;
    reg [7:0] dipsw_d0 = 0;
    reg [7:0] dipsw_d1 = 0;
    reg [7:0] dipsw_d2 = 0;
    reg [7:0] dipsw_d3 = 0;


    //PWM generator
    reg [9:0] pwm_clock_counter = 0;
    wire      pwm_clock_en;
    assign pwm_clock_en = (pwm_clock_counter == 0);
    
    wire [15:0] pwm_param_period;
    wire [15:0] pwm_param_thresh_sw;
    wire [15:0] pwm_param_thresh;
    reg  [15:0] pwm_param_thresh_d;

    wire        pwm_param_ramp_en;

    wire [14:0] pwm_param_ramp_min;
    wire [15:0] pwm_param_ramp_max;

    wire        pwm_ramp_count_dir_toggle;
    reg pwm_ramp_count_dir_toggle_d = 0;

    reg         pwm_ramp_count_dir = 0;
    
    assign pwm_ramp_count_dir_toggle = (((pwm_ramp_counter > pwm_param_ramp_max) | (pwm_ramp_counter < pwm_param_ramp_min)));
    
    assign pwm_param_period     = slv_reg7[31:16];
    assign pwm_param_thresh_sw  = slv_reg7[15:0];

    assign pwm_param_ramp_en    = slv_reg9[31];
    assign pwm_param_ramp_min   = slv_reg9[30:16];
    assign pwm_param_ramp_max   = slv_reg9[15:0];
    
    assign pwm_param_thresh = pwm_param_ramp_en ? pwm_ramp_counter : pwm_param_thresh_sw;
    
    reg [15:0] pwm_period_counter = 0;
    reg [15:0] pwm_ramp_counter = 0;

    reg pwm_out = 0;
    
    reg [C_DBG_HDR_WIDTH-1:0] dbg_hdr_dir_d1;
    reg [C_DBG_HDR_WIDTH-1:0] dbg_hdr_dir_d2;
    reg [C_DBG_HDR_WIDTH-1:0] dbg_hdr_dout_d1;
    reg [C_DBG_HDR_WIDTH-1:0] dbg_hdr_dout_d2;

    wire [15:0] dbg_hdr_din;
    wire [C_DBG_HDR_WIDTH-1:0] dbg_hdr_pin_in;
    reg [15:0] dbg_hdr_din_d1;
    reg [15:0] dbg_hdr_din_d2;
    
    // Debug header logic
    assign dbg_hdr_dir = slv_reg13[16+C_DBG_HDR_WIDTH-1 : 16];
    assign dbg_hdr_read_val = dbg_hdr_din_d2;
  
    // Pipeline regs for register bits. These registers reduce timing challenge in routing
    //  signals between WARP v3 debug header and the shared AXI interconnect data bus
    always @(posedge Bus2IP_Clk)
    begin
        dbg_hdr_dir_d1 <= dbg_hdr_dir;
        dbg_hdr_dir_d2 <= dbg_hdr_dir_d1;
        
        dbg_hdr_dout_d1 <= slv_reg13[C_DBG_HDR_WIDTH-1:0];
        dbg_hdr_dout_d2 <= dbg_hdr_dout_d1;
        
        dbg_hdr_din_d1 <= dbg_hdr_din;
        dbg_hdr_din_d2 <= dbg_hdr_din_d1;
    end
    
    genvar idx;
    generate
        for(idx=0; idx<C_DBG_HDR_WIDTH; idx=idx+1) begin: DBG_HDR_IOBS
            // Treat pin as input if hdr_dir == 1
            //  For inputs tri-state IOB (assign output = Z) and capture input in slv_reg13
            //  For outputs enable IOB (drive output from slv_reg13), and return output value
            IOBUF iob_dbg_hdr (
                .IO(dbg_hdr[idx]),  //Top-level pin
                .O(dbg_hdr_pin_in[idx]), //IOB -> Fabric (when IOB is input)
                .I(dbg_hdr_dout_d2[idx]), //Fabric -> IOB (when IOB is output)
                .T(dbg_hdr_dir_d2[idx])   //Tri-state (1=use IOB as input)
            );
            
            // Software accessible register captures input value for inputs and output value for outputs
            assign dbg_hdr_din[idx] = dbg_hdr_dir_d2[idx] ? dbg_hdr_pin_in[idx] : dbg_hdr_dout_d2[idx];
        end
    endgenerate 
    generate
        for(idx=C_DBG_HDR_WIDTH; idx<16; idx=idx+1) begin: DBG_HDR_UNUSED
            // Data register is always 16 bits wide
            //  For non-IOB bits ignore data direction, return data register value
            assign dbg_hdr_din[idx] = slv_reg13[idx];
        end
    endgenerate 

    always @(posedge Bus2IP_Clk)
    begin
        pwm_clock_counter <= pwm_clock_counter + 1;

        if(pwm_period_counter >= pwm_param_period)
            pwm_period_counter <= 0;
        else if(pwm_clock_en)
            pwm_period_counter <= pwm_period_counter + 1;

        pwm_param_thresh_d <= pwm_param_thresh;
        
        pwm_out <= (pwm_period_counter < pwm_param_thresh_d);
    end

    always @(posedge Bus2IP_Clk)
    begin
        pwm_ramp_count_dir_toggle_d <= pwm_ramp_count_dir_toggle;

        //pwm_ramp_count_dir=0 counts up
        if(~pwm_param_ramp_en)
            pwm_ramp_counter <= {1'b0,pwm_param_ramp_min};
        else if(pwm_clock_en & (pwm_period_counter==0))
            if(pwm_ramp_count_dir)
                pwm_ramp_counter <= pwm_ramp_counter + 16'hFFFE;
            else
                pwm_ramp_counter <= pwm_ramp_counter + 1'b1;

        if(~pwm_param_ramp_en)
            pwm_ramp_count_dir <= 0;
        else if(pwm_ramp_count_dir_toggle & ~pwm_ramp_count_dir_toggle_d)
            pwm_ramp_count_dir <= ~pwm_ramp_count_dir;

    end

    
    //Shift registers for debouncing mechanical inputs
    always @(posedge Bus2IP_Clk)
    begin
        pb_u_d[7:0] <= {pb_u_d[6:0], pb_u};
        pb_m_d[7:0] <= {pb_m_d[6:0], pb_m};
        pb_d_d[7:0] <= {pb_d_d[6:0], pb_d};
        dipsw_d0[7:0] <= {dipsw_d0[6:0], dipsw[0]};
        dipsw_d1[7:0] <= {dipsw_d1[6:0], dipsw[1]};
        dipsw_d2[7:0] <= {dipsw_d2[6:0], dipsw[2]};
        dipsw_d3[7:0] <= {dipsw_d3[6:0], dipsw[3]};
    end
    
    //Assert debounced signals only if inputs are high 8 consecutive cycles
    assign pb_u_db = (pb_u_d == 8'hff);
    assign pb_m_db = (pb_m_d == 8'hff);
    assign pb_d_db = (pb_d_d == 8'hff);

    //Swap MSB:LSB here, to undo endian swaps relative to schematic labels
    assign dipsw_db = {(dipsw_d0==8'hff), (dipsw_d1==8'hff), (dipsw_d2==8'hff), (dipsw_d3==8'hff)};
    
    //Logic to map 4-bit hex value to 7-bit value for hex display
    sevenSegmentMap leftHexMap  (.data(slv_reg1[3:0]), .disp(leftHex_mapped));
    sevenSegmentMap rightHexMap (.data(slv_reg2[3:0]), .disp(rightHex_mapped));

    //Select which 7-bit value is used as the software-supplied value for hex displays
    // User either supplies 4-bit value to be interpretted as hex value
    //  or raw 7-bit (bit-per-diode) value
    assign leftHex_sw_val =  slv_reg0[29] ? leftHex_mapped :  slv_reg1[6:0];
    assign rightHex_sw_val = slv_reg0[28] ? rightHex_mapped : slv_reg2[6:0];

    //Extract the mux control values from the software register
    assign all_outputs_ctrl_source    = slv_reg0[27:0];
    assign all_outputs_hw_ctrl_source = slv_reg10[27:0];

    //Extract and concatenate the software-controlled output values
    assign all_outputs_sw_val[27:0] = {
        slv_reg5[3],            //[27]      rgb_red LED
        slv_reg5[2],            //[26]      rgb_green LED
        slv_reg5[1],            //[25]      rga_red LED
        slv_reg5[0],            //[24]      rga_green LED
        slv_reg4[3:0],          //[23:20]   green LEDs
        slv_reg3[3:0],          //[19:16]   red LEDs
        slv_reg2[8],            //[15]      right hex DP
        rightHex_sw_val[6:0],   //[14:8]    right hex mapped
        slv_reg1[8],            //[7]       left hex DP
        leftHex_sw_val[6:0]     //[6:0]     left hex mapped
    };

    //Concatenate the top-level inputs for hardware-controlled output values
    assign all_outputs_hw_val[27:24] = {usr_rfb_led_red, usr_rfb_led_green, usr_rfa_led_red, usr_rfa_led_green};
    assign all_outputs_hw_val[23:16] = {usr_leds_green, usr_leds_red};
    assign all_outputs_hw_val[15:8] = {usr_hexdisp_right_dp, usr_hexdisp_right};
    assign all_outputs_hw_val[7:0] = {usr_hexdisp_left_dp, usr_hexdisp_left};

    //Mux between hardware and software control for each output
    // Source control = 0 -> Software register bit controls output
    // Source control = 1 -> Hardware control
    //   Hardware control mode = 0 -> usr_ port controls
    //   Hardware control mode = 1 -> pwm module controls
    always @*
    begin
    for(ii=0; ii<28; ii=ii+1)
        all_outputs[ii] = all_outputs_ctrl_source[ii] ? (all_outputs_hw_ctrl_source[ii] ? pwm_out : all_outputs_hw_val[ii]) : all_outputs_sw_val[ii];
    end

    always @(posedge Bus2IP_Clk)
    begin
        all_outputs_d1 <= all_outputs;
        
        // HDL parameter HEXDISP_ACTIVE_HIGH defines the type at build-time
        // User values are always interpreted as 1==illuminated
        // Mux on active high/low here so _d2 DFFs can be packed into IOBs
        all_outputs_d2[15:0] <= HEXDISP_ACTIVE_HIGH ? all_outputs_d1[15:0] : ~all_outputs_d1[15:0];
        all_outputs_d2[27:16] <= all_outputs_d1[27:16];
    end
    
    //Map the mux outputs to the top-level outputs
    assign {rfb_led_red, rfb_led_green, rfa_led_red, rfa_led_green} = all_outputs_d2[27:24];

    assign leds_green[3:0] = all_outputs_d2[23:20];
    assign leds_red[3:0] =   all_outputs_d2[19:16];

    assign hexdisp_left_dp   = all_outputs_d2[7];
    assign hexdisp_left[6:0] = all_outputs_d2[6:0];

    assign hexdisp_right_dp   = all_outputs_d2[15];
    assign hexdisp_right[6:0] = all_outputs_d2[14:8];

    //Assign the usr_ output ports to the de-bounced top-level inputs
    assign usr_dipsw[3:0] = dipsw_db[3:0];
    assign usr_pb_u = pb_u_db;
    assign usr_pb_m = pb_m_db;
    assign usr_pb_d = pb_d_db;

    generate
    if(INCLUDE_DNA_READ_LOGIC) begin
        wire dna_port_read, dna_port_shift, dna_port_clk_gated, dna_port_dout;
        //Instantiate the DNA_PORT module, for reading the FPGA's unique ID
        // Two MSB are always [1 0]? Accordint to isim at least
        DNA_PORT #(.SIM_DNA_VALUE(57'h123456789abcdef)) dna_port_inst (
            .DIN(1'b0),
            .READ(dna_port_read),
            .SHIFT(dna_port_shift),
            .CLK(dna_port_clk_gated),
            .DOUT(dna_port_dout)
        );
        
        reg [6:0] dna_read_counter = 7'b0;

        //Only clock the DNA_PORT primitive while actively shifting data out
        assign dna_port_clk_gated = (DNA_Port_Clk & (dna_read_counter>7'd60) & (dna_read_counter<7'h7f));

        //Count-limited counter, that starts at configuration and runs exactly once
        always @(posedge DNA_Port_Clk)
        begin
            if(dna_read_counter == 7'h7f)
                dna_read_counter <= 7'h7f;
            else
                dna_read_counter <= dna_read_counter + 1;
        end

        //dna read states, as function of dna_read_counter value:
        //  0-63: Do nothing (just in case things needs to settle before DNA_PORT is accessible)
        //    64: Toggle READ signal (loads DNA value into DNA_PORT 57-bit shift register)
        //    65: Read DNA[0] from shift register DOUT; assert SHIFT
        //66-121: Read DNA[1:56] from shif register DOUT; SHIFT stays asserted
        //   122: De-assert SHIFT and READ
        
        assign dna_port_read = (dna_read_counter == 7'd63);
        assign dna_port_shift = ((dna_read_counter>= 7'd65) && (dna_read_counter<=122));
        
        //Capture the shift register output in a single big register
        wire dna_capt;
        assign dna_capt = ((dna_read_counter>= 7'd65) && (dna_read_counter<=121));
        always @(posedge DNA_Port_Clk)
        begin
            if (dna_capt)
                fpga_dna_value[dna_read_counter-7'd65] = dna_port_dout;
        end
    end
    endgenerate
  
endmodule


module sevenSegmentMap
(
    input       [3:0]   data,
    output  reg [6:0]   disp
);

always @(data[3:0])
    case (data[3:0])
    4'b0000 : disp <= ~(7'b1000000);   // 0
    4'b0001 : disp <= ~(7'b1111001);   // 1
    4'b0010 : disp <= ~(7'b0100100);   // 2
    4'b0011 : disp <= ~(7'b0110000);   // 3
    4'b0100 : disp <= ~(7'b0011001);   // 4
    4'b0101 : disp <= ~(7'b0010010);   // 5
    4'b0110 : disp <= ~(7'b0000010);   // 6
    4'b0111 : disp <= ~(7'b1111000);   // 7
    4'b1000 : disp <= ~(7'b0000000);   // 8
    4'b1001 : disp <= ~(7'b0010000);   // 9
    4'b1010 : disp <= ~(7'b0001000);   // A
    4'b1011 : disp <= ~(7'b0000011);   // b
    4'b1100 : disp <= ~(7'b1000110);   // C
    4'b1101 : disp <= ~(7'b0100001);   // d
    4'b1110 : disp <= ~(7'b0000110);   // E
    4'b1111 : disp <= ~(7'b0001110);   // F
    default : disp <=  (7'b0000000);
    endcase

endmodule