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w3_userio_axi.vhd

Last change on this file was 5539, checked in by murphpo, 8 years ago
Working version of updated userio core+driver with debug header IO support
File size: 21.6 KB

Line
1	------------------------------------------------------------------------------
2	-- w3_userio_axi.vhd - entity/architecture pair
3	------------------------------------------------------------------------------
4	-- IMPORTANT:
5	-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
6	--
7	-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
8	--
9	-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
10	-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
11	-- OF THE USER_LOGIC ENTITY.
12	------------------------------------------------------------------------------
13	--
14	-- ***************************************************************************
15	-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
16	--
17	-- Xilinx, Inc.
18	-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
19	-- AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
20	-- SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
21	-- OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
22	-- APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
23	-- THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
24	-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
25	-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
26	-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
27	-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
28	-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
29	-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30	-- FOR A PARTICULAR PURPOSE.
31	--
32	-- ***************************************************************************
33	--
34	------------------------------------------------------------------------------
35	-- Filename: w3_userio_axi.vhd
36	-- Version: 1.00.a
37	-- Description: Top level design, instantiates library components and user logic.
38	-- Date: Fri Nov 09 20:37:15 2012 (by Create and Import Peripheral Wizard)
39	-- VHDL Standard: VHDL'93
40	------------------------------------------------------------------------------
41	-- Naming Conventions:
42	-- active low signals: "*_n"
43	-- clock signals: "clk", "clk_div#", "clk_#x"
44	-- reset signals: "rst", "rst_n"
45	-- generics: "C_*"
46	-- user defined types: "*_TYPE"
47	-- state machine next state: "*_ns"
48	-- state machine current state: "*_cs"
49	-- combinatorial signals: "*_com"
50	-- pipelined or register delay signals: "*_d#"
51	-- counter signals: "cnt"
52	-- clock enable signals: "*_ce"
53	-- internal version of output port: "*_i"
54	-- device pins: "*_pin"
55	-- ports: "- Names begin with Uppercase"
56	-- processes: "*_PROCESS"
57	-- component instantiations: "<ENTITY_>I_<#\|FUNC>"
58	------------------------------------------------------------------------------
59
60	library ieee;
61	use ieee.std_logic_1164.all;
62	use ieee.std_logic_arith.all;
63	use ieee.std_logic_unsigned.all;
64
65	library proc_common_v3_00_a;
66	use proc_common_v3_00_a.proc_common_pkg.all;
67	use proc_common_v3_00_a.ipif_pkg.all;
68
69	library axi_lite_ipif_v1_01_a;
70	use axi_lite_ipif_v1_01_a.axi_lite_ipif;
71
72	------------------------------------------------------------------------------
73	-- Entity section
74	------------------------------------------------------------------------------
75	-- Definition of Generics:
76	-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
77	-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
78	-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
79	-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
80	-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
81	-- C_BASEADDR -- AXI4LITE slave: base address
82	-- C_HIGHADDR -- AXI4LITE slave: high address
83	-- C_FAMILY -- FPGA Family
84	-- C_NUM_REG -- Number of software accessible registers
85	-- C_NUM_MEM -- Number of address-ranges
86	-- C_SLV_AWIDTH -- Slave interface address bus width
87	-- C_SLV_DWIDTH -- Slave interface data bus width
88	--
89	-- Definition of Ports:
90	-- S_AXI_ACLK -- AXI4LITE slave: Clock
91	-- S_AXI_ARESETN -- AXI4LITE slave: Reset
92	-- S_AXI_AWADDR -- AXI4LITE slave: Write address
93	-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
94	-- S_AXI_WDATA -- AXI4LITE slave: Write data
95	-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
96	-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
97	-- S_AXI_BREADY -- AXI4LITE slave: Response ready
98	-- S_AXI_ARADDR -- AXI4LITE slave: Read address
99	-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
100	-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
101	-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
102	-- S_AXI_RDATA -- AXI4LITE slave: Read data
103	-- S_AXI_RRESP -- AXI4LITE slave: Read data response
104	-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
105	-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
106	-- S_AXI_BRESP -- AXI4LITE slave: Response
107	-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
108	-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
109	------------------------------------------------------------------------------
110
111	entity w3_userio_axi is
112	generic
113	(
114	-- ADD USER GENERICS BELOW THIS LINE ---------------
115	HEXDISP_ACTIVE_HIGH : integer := 0;
116	INCLUDE_DNA_READ_LOGIC : integer := 1;
117	C_DBG_HDR_WIDTH : integer := 4;
118	-- ADD USER GENERICS ABOVE THIS LINE ---------------
119
120	-- DO NOT EDIT BELOW THIS LINE ---------------------
121	-- Bus protocol parameters, do not add to or delete
122	C_S_AXI_DATA_WIDTH : integer := 32;
123	C_S_AXI_ADDR_WIDTH : integer := 32;
124	C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
125	C_USE_WSTRB : integer := 0;
126	C_DPHASE_TIMEOUT : integer := 8;
127	C_BASEADDR : std_logic_vector := X"FFFFFFFF";
128	C_HIGHADDR : std_logic_vector := X"00000000";
129	C_FAMILY : string := "virtex6";
130	C_NUM_REG : integer := 1;
131	C_NUM_MEM : integer := 1;
132	C_SLV_AWIDTH : integer := 32;
133	C_SLV_DWIDTH : integer := 32
134	-- DO NOT EDIT ABOVE THIS LINE ---------------------
135	);
136	port
137	(
138	-- ADD USER PORTS BELOW THIS LINE ------------------
139	hexdisp_left : out std_logic_vector(0 to 6);
140	hexdisp_left_dp : out std_logic;
141	hexdisp_right : out std_logic_vector(0 to 6);
142	hexdisp_right_dp : out std_logic;
143
144	leds_red : out std_logic_vector(0 to 3);
145	leds_green : out std_logic_vector(0 to 3);
146
147	rfa_led_red : out std_logic;
148	rfa_led_green : out std_logic;
149	rfb_led_red : out std_logic;
150	rfb_led_green : out std_logic;
151
152	dipsw : in std_logic_vector(0 to 3);
153	pb_u : in std_logic;
154	pb_m : in std_logic;
155	pb_d : in std_logic;
156
157	dbg_hdr : inout std_logic_vector(0 to C_DBG_HDR_WIDTH-1);
158
159	usr_hexdisp_left : in std_logic_vector(0 to 6);
160	usr_hexdisp_left_dp : in std_logic;
161	usr_hexdisp_right : in std_logic_vector(0 to 6);
162	usr_hexdisp_right_dp : in std_logic;
163
164	usr_leds_red : in std_logic_vector(0 to 3);
165	usr_leds_green : in std_logic_vector(0 to 3);
166
167	usr_rfa_led_red : in std_logic;
168	usr_rfa_led_green : in std_logic;
169	usr_rfb_led_red : in std_logic;
170	usr_rfb_led_green : in std_logic;
171
172	usr_dipsw : out std_logic_vector(0 to 3);
173	usr_pb_u : out std_logic;
174	usr_pb_m : out std_logic;
175	usr_pb_d : out std_logic;
176
177	DNA_Port_Clk : in std_logic;
178	-- ADD USER PORTS ABOVE THIS LINE ------------------
179
180	-- DO NOT EDIT BELOW THIS LINE ---------------------
181	-- Bus protocol ports, do not add to or delete
182	S_AXI_ACLK : in std_logic;
183	S_AXI_ARESETN : in std_logic;
184	S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
185	S_AXI_AWVALID : in std_logic;
186	S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
187	S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
188	S_AXI_WVALID : in std_logic;
189	S_AXI_BREADY : in std_logic;
190	S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
191	S_AXI_ARVALID : in std_logic;
192	S_AXI_RREADY : in std_logic;
193	S_AXI_ARREADY : out std_logic;
194	S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
195	S_AXI_RRESP : out std_logic_vector(1 downto 0);
196	S_AXI_RVALID : out std_logic;
197	S_AXI_WREADY : out std_logic;
198	S_AXI_BRESP : out std_logic_vector(1 downto 0);
199	S_AXI_BVALID : out std_logic;
200	S_AXI_AWREADY : out std_logic
201	-- DO NOT EDIT ABOVE THIS LINE ---------------------
202	);
203
204	attribute MAX_FANOUT : string;
205	attribute SIGIS : string;
206	attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
207	attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
208	attribute SIGIS of S_AXI_ACLK : signal is "Clk";
209	attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
210	end entity w3_userio_axi;
211
212	------------------------------------------------------------------------------
213	-- Architecture section
214	------------------------------------------------------------------------------
215
216	architecture IMP of w3_userio_axi is
217
218	constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
219
220	constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
221
222	constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
223	constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
224	constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
225
226	constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
227	(
228	ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
229	ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
230	);
231
232	constant USER_SLV_NUM_REG : integer := 14;
233	constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
234	constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
235
236	constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
237	(
238	0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
239	);
240
241	------------------------------------------
242	-- Index for CS/CE
243	------------------------------------------
244	constant USER_SLV_CS_INDEX : integer := 0;
245	constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
246
247	constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
248
249	------------------------------------------
250	-- IP Interconnect (IPIC) signal declarations
251	------------------------------------------
252	signal ipif_Bus2IP_Clk : std_logic;
253	signal ipif_Bus2IP_Resetn : std_logic;
254	signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
255	signal ipif_Bus2IP_RNW : std_logic;
256	signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
257	signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
258	signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
259	signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
260	signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
261	signal ipif_IP2Bus_WrAck : std_logic;
262	signal ipif_IP2Bus_RdAck : std_logic;
263	signal ipif_IP2Bus_Error : std_logic;
264	signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
265	signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
266	signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
267	signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
268	signal user_IP2Bus_RdAck : std_logic;
269	signal user_IP2Bus_WrAck : std_logic;
270	signal user_IP2Bus_Error : std_logic;
271
272	------------------------------------------
273	-- Component declaration for verilog user logic
274	------------------------------------------
275	component user_logic is
276	generic
277	(
278	-- ADD USER GENERICS BELOW THIS LINE ---------------
279	HEXDISP_ACTIVE_HIGH : integer := 0;
280	INCLUDE_DNA_READ_LOGIC : integer := 1;
281	-- ADD USER GENERICS ABOVE THIS LINE ---------------
282
283	-- DO NOT EDIT BELOW THIS LINE ---------------------
284	-- Bus protocol parameters, do not add to or delete
285	C_NUM_REG : integer := 14;
286	C_SLV_DWIDTH : integer := 32;
287	C_DBG_HDR_WIDTH : integer := 4
288	-- DO NOT EDIT ABOVE THIS LINE ---------------------
289	);
290	port
291	(
292	-- ADD USER PORTS BELOW THIS LINE ------------------
293	hexdisp_left : out std_logic_vector(0 to 6);
294	hexdisp_left_dp : out std_logic;
295	hexdisp_right : out std_logic_vector(0 to 6);
296	hexdisp_right_dp : out std_logic;
297
298	leds_red : out std_logic_vector(0 to 3);
299	leds_green : out std_logic_vector(0 to 3);
300
301	rfa_led_red : out std_logic;
302	rfa_led_green : out std_logic;
303	rfb_led_red : out std_logic;
304	rfb_led_green : out std_logic;
305
306	dipsw : in std_logic_vector(0 to 3);
307	pb_u : in std_logic;
308	pb_m : in std_logic;
309	pb_d : in std_logic;
310
311	dbg_hdr : inout std_logic_vector(0 to C_DBG_HDR_WIDTH-1);
312
313	usr_hexdisp_left : in std_logic_vector(0 to 6);
314	usr_hexdisp_left_dp : in std_logic;
315	usr_hexdisp_right : in std_logic_vector(0 to 6);
316	usr_hexdisp_right_dp : in std_logic;
317
318	usr_leds_red : in std_logic_vector(0 to 3);
319	usr_leds_green : in std_logic_vector(0 to 3);
320
321	usr_rfa_led_red : in std_logic;
322	usr_rfa_led_green : in std_logic;
323	usr_rfb_led_red : in std_logic;
324	usr_rfb_led_green : in std_logic;
325
326	usr_dipsw : out std_logic_vector(0 to 3);
327	usr_pb_u : out std_logic;
328	usr_pb_m : out std_logic;
329	usr_pb_d : out std_logic;
330	DNA_Port_Clk : in std_logic;
331	-- ADD USER PORTS ABOVE THIS LINE ------------------
332
333	-- DO NOT EDIT BELOW THIS LINE ---------------------
334	-- Bus protocol ports, do not add to or delete
335	Bus2IP_Clk : in std_logic;
336	Bus2IP_Resetn : in std_logic;
337	Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
338	Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
339	Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
340	Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
341	IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
342	IP2Bus_RdAck : out std_logic;
343	IP2Bus_WrAck : out std_logic;
344	IP2Bus_Error : out std_logic
345	-- DO NOT EDIT ABOVE THIS LINE ---------------------
346	);
347	end component user_logic;
348
349	begin
350
351	------------------------------------------
352	-- instantiate axi_lite_ipif
353	------------------------------------------
354	AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
355	generic map
356	(
357	C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
358	C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
359	C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
360	C_USE_WSTRB => C_USE_WSTRB,
361	C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
362	C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
363	C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
364	C_FAMILY => C_FAMILY
365	)
366	port map
367	(
368	S_AXI_ACLK => S_AXI_ACLK,
369	S_AXI_ARESETN => S_AXI_ARESETN,
370	S_AXI_AWADDR => S_AXI_AWADDR,
371	S_AXI_AWVALID => S_AXI_AWVALID,
372	S_AXI_WDATA => S_AXI_WDATA,
373	S_AXI_WSTRB => S_AXI_WSTRB,
374	S_AXI_WVALID => S_AXI_WVALID,
375	S_AXI_BREADY => S_AXI_BREADY,
376	S_AXI_ARADDR => S_AXI_ARADDR,
377	S_AXI_ARVALID => S_AXI_ARVALID,
378	S_AXI_RREADY => S_AXI_RREADY,
379	S_AXI_ARREADY => S_AXI_ARREADY,
380	S_AXI_RDATA => S_AXI_RDATA,
381	S_AXI_RRESP => S_AXI_RRESP,
382	S_AXI_RVALID => S_AXI_RVALID,
383	S_AXI_WREADY => S_AXI_WREADY,
384	S_AXI_BRESP => S_AXI_BRESP,
385	S_AXI_BVALID => S_AXI_BVALID,
386	S_AXI_AWREADY => S_AXI_AWREADY,
387	Bus2IP_Clk => ipif_Bus2IP_Clk,
388	Bus2IP_Resetn => ipif_Bus2IP_Resetn,
389	Bus2IP_Addr => ipif_Bus2IP_Addr,
390	Bus2IP_RNW => ipif_Bus2IP_RNW,
391	Bus2IP_BE => ipif_Bus2IP_BE,
392	Bus2IP_CS => ipif_Bus2IP_CS,
393	Bus2IP_RdCE => ipif_Bus2IP_RdCE,
394	Bus2IP_WrCE => ipif_Bus2IP_WrCE,
395	Bus2IP_Data => ipif_Bus2IP_Data,
396	IP2Bus_WrAck => ipif_IP2Bus_WrAck,
397	IP2Bus_RdAck => ipif_IP2Bus_RdAck,
398	IP2Bus_Error => ipif_IP2Bus_Error,
399	IP2Bus_Data => ipif_IP2Bus_Data
400	);
401
402	------------------------------------------
403	-- instantiate User Logic
404	------------------------------------------
405	USER_LOGIC_I : component user_logic
406	generic map
407	(
408	-- MAP USER GENERICS BELOW THIS LINE ---------------
409	HEXDISP_ACTIVE_HIGH => HEXDISP_ACTIVE_HIGH,
410	INCLUDE_DNA_READ_LOGIC => INCLUDE_DNA_READ_LOGIC,
411	C_DBG_HDR_WIDTH => C_DBG_HDR_WIDTH,
412	-- MAP USER GENERICS ABOVE THIS LINE ---------------
413
414	C_NUM_REG => USER_NUM_REG,
415	C_SLV_DWIDTH => USER_SLV_DWIDTH
416	)
417	port map
418	(
419	-- MAP USER PORTS BELOW THIS LINE ------------------
420	hexdisp_left => hexdisp_left,
421	hexdisp_left_dp => hexdisp_left_dp,
422	hexdisp_right => hexdisp_right,
423	hexdisp_right_dp => hexdisp_right_dp,
424	leds_red => leds_red,
425	leds_green => leds_green,
426	rfa_led_red => rfa_led_red,
427	rfa_led_green => rfa_led_green,
428	rfb_led_red => rfb_led_red,
429	rfb_led_green => rfb_led_green,
430	dipsw => dipsw,
431	pb_u => pb_u,
432	pb_m => pb_m,
433	pb_d => pb_d,
434	dbg_hdr => dbg_hdr,
435	usr_hexdisp_left => usr_hexdisp_left,
436	usr_hexdisp_left_dp => usr_hexdisp_left_dp,
437	usr_hexdisp_right => usr_hexdisp_right,
438	usr_hexdisp_right_dp => usr_hexdisp_right_dp,
439	usr_leds_red => usr_leds_red,
440	usr_leds_green => usr_leds_green,
441	usr_rfa_led_red => usr_rfa_led_red,
442	usr_rfa_led_green => usr_rfa_led_green,
443	usr_rfb_led_red => usr_rfb_led_red,
444	usr_rfb_led_green => usr_rfb_led_green,
445	usr_dipsw => usr_dipsw,
446	usr_pb_u => usr_pb_u,
447	usr_pb_m => usr_pb_m,
448	usr_pb_d => usr_pb_d,
449	DNA_Port_Clk => DNA_Port_Clk,
450	-- MAP USER PORTS ABOVE THIS LINE ------------------
451
452	Bus2IP_Clk => ipif_Bus2IP_Clk,
453	Bus2IP_Resetn => ipif_Bus2IP_Resetn,
454	Bus2IP_Data => ipif_Bus2IP_Data,
455	Bus2IP_BE => ipif_Bus2IP_BE,
456	Bus2IP_RdCE => user_Bus2IP_RdCE,
457	Bus2IP_WrCE => user_Bus2IP_WrCE,
458	IP2Bus_Data => user_IP2Bus_Data,
459	IP2Bus_RdAck => user_IP2Bus_RdAck,
460	IP2Bus_WrAck => user_IP2Bus_WrAck,
461	IP2Bus_Error => user_IP2Bus_Error
462	);
463
464	------------------------------------------
465	-- connect internal signals
466	------------------------------------------
467	ipif_IP2Bus_Data <= user_IP2Bus_Data;
468	ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
469	ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
470	ipif_IP2Bus_Error <= user_IP2Bus_Error;
471
472	user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
473	user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
474
475	end IMP;

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source: PlatformSupport/CustomPeripherals/pcores/w3_userio_axi_v1_02_a/hdl/vhdl/w3_userio_axi.vhd

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