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Last change
on this file was
5565,
checked in by murphpo, 8 years ago
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Updated w3_userio pcore with hw/sw control source logic for debug header. This allows all 16 pins of the debug header to be connected to the userio core. Software configures each pin's value as sw (set by C via a register) or hw (driven by an on-chip debug signals).
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File size:
563 bytes
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| 1 | ############################################################################## |
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| 2 | ## Filename: C:/TEMP/MyProcessorIPLib/pcores/w3_userio_axi_v1_00_a/data/w3_userio_axi_v2_1_0.pao |
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| 3 | ## Description: Peripheral Analysis Order |
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| 4 | ## Date: Fri Nov 09 20:37:15 2012 (by Create and Import Peripheral Wizard) |
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| 5 | ############################################################################## |
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| 6 | |
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| 7 | lib proc_common_v3_00_a all |
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| 8 | lib axi_lite_ipif_v1_01_a all |
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| 9 | lib w3_userio_axi_v1_03_a user_logic verilog |
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| 10 | lib w3_userio_axi_v1_03_a w3_userio_axi vhdl |
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