source:
PlatformSupport/CustomPeripherals/pcores/w3_userio_v1_00_a/hdl/verilog
| Name | Size | Rev | Age | Author | Last Change |
|---|---|---|---|---|---|
| ../ | |||||
| user_logic.v | 24.0 KB | 1782 | 12 years | murphpo | adding ad_bridge g, with separate sys_samp_clk ports for Tx/Rx to … |
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