1 | /***************************************************************** |
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2 | * File: w3_userio.h |
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3 | * Copyright (c) 2012 Mango Communications, all rights reseved |
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4 | * Released under the WARP License |
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5 | * See http://warp.rice.edu/license for details |
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6 | *****************************************************************/ |
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7 | |
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8 | /*! \file w3_userio.h |
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9 | |
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10 | \mainpage |
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11 | This is the driver for the w3_userio core, which provides access to all the user IO resources on WARP v3 boards. These resources include |
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12 | user LEDs, RF LEDs, hex displays, push buttons and a DIP switch. |
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13 | |
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14 | This driver only implements macros for reading/writing registers in the w3_userio core hardware. Macros are also provided to read the Virtex-6 device DNA. |
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15 | |
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16 | @version 1.00.a |
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17 | @author Patrick Murphy |
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18 | @copyright (c) 2012 Mango Communications, Inc. All rights reserved.<br> |
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19 | Released under the WARP open source license (see http://warp.rice.edu/license) |
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20 | |
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21 | */ |
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22 | |
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23 | /* Address map (from user_logic.v) |
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24 | HDL is coded [MSB:LSB] = [0:31] |
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25 | regX[0] maps to 0x80000000 in C driver |
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26 | regX[31] maps to 0x00000001 in C driver |
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27 | |
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28 | 0: Control RW |
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29 | [ 0: 1] = Reserved |
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30 | [ 2] = Left hex data mode (0=user supplies bit-per-segment; 1=user supplies 4-bit hex) 0x20000000 |
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31 | [ 3] = Right hex data mode (0=user supplies bit-per-segment; 1=user supplies 4-bit hex) 0x10000000 |
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32 | Control source for LEDs: 0=software controlled, 1=usr_ port controlled |
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33 | [ 4: 7] = {rfb_red rfb_green rfa_red rfa_green} 0x0F000000 |
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34 | [ 8:15] = {leds_red leds_green} 0x00FF0000 |
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35 | [16:23] = {hexdisp_left{a b c d e f g dp}} 0x0000FF00 |
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36 | [24:31] = {hexdisp_right{a b c d e f g dp}} 0x000000FF |
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37 | 1: Left hex display RW |
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38 | [ 0:22] = reserved |
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39 | [ 23] = DP (controlled directly; doesn't depend on data mode) 0x100 |
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40 | [25:31] = Data value ([25:27] ignored when data mode = 1) 0x03F |
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41 | 2: Right hex display RW |
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42 | [ 0:22] = reserved |
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43 | [ 23] = DP (controlled directly; doesn't depend on data mode) 0x100 |
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44 | [25:31] = Data value ([25:27] ignored when data mode = 1) 0x03F |
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45 | 3: Red user LEDs RW |
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46 | [ 0:27] = reserved |
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47 | [28:31] = Data value (1=LED illuminated) 0xF, with 0x1 mapped to lowest LED |
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48 | 4: Green user LEDs RW |
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49 | [ 0:27] = reserved |
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50 | [28:31] = Data value (1=LED illuminated) 0xF, with 0x1 mapped to lowest LED |
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51 | 5: RF LEDs RW |
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52 | [ 0:27] = reserved |
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53 | [ 28] = rfb_red 0x8 |
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54 | [ 29] = rfb_green 0x4 |
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55 | [ 30] = rfa_red 0x2 |
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56 | [ 31] = rfa_green 0x1 |
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57 | 6: Switch/button inputs RO |
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58 | [ 0:24] = reserved |
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59 | [ 25] = pb_up 0x40 |
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60 | [ 26] = pb_mid 0x20 |
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61 | [ 27] = pb_down 0x10 |
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62 | [28:31] = DIP switch 0x0F (with 0x1 mapped to right-most switch) |
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63 | */ |
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64 | |
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65 | #ifndef W3_USERIO_H |
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66 | #define W3_USERIO_H |
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67 | |
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68 | #include "xil_io.h" |
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69 | |
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70 | /// @cond EXCLUDE_FROM_DOCS |
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71 | // Address offset for each slave register; exclude from docs, as users never use these directly |
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72 | #define W3_USERIO_USER_SLV_SPACE_OFFSET (0x00000000) |
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73 | #define W3_USERIO_SLV_REG0_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000000) |
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74 | #define W3_USERIO_SLV_REG1_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000004) |
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75 | #define W3_USERIO_SLV_REG2_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000008) |
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76 | #define W3_USERIO_SLV_REG3_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x0000000C) |
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77 | #define W3_USERIO_SLV_REG4_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000010) |
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78 | #define W3_USERIO_SLV_REG5_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000014) |
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79 | #define W3_USERIO_SLV_REG6_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000018) |
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80 | #define W3_USERIO_SLV_REG7_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x0000001C) |
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81 | #define W3_USERIO_SLV_REG8_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000020) |
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82 | #define W3_USERIO_SLV_REG9_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000024) |
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83 | #define W3_USERIO_SLV_REG10_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x00000028) |
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84 | #define W3_USERIO_SLV_REG11_OFFSET (W3_USERIO_USER_SLV_SPACE_OFFSET + 0x0000002C) |
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85 | /// @endcond |
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86 | |
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87 | /** \defgroup control_reg Control register |
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88 | * \addtogroup control_reg |
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89 | <b>Hardware vs. software control</b>: |
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90 | Every LED and hex display segment can be controlled either via software or hardware: |
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91 | <ul> |
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92 | <li>Software: user code sets LED state by writing a 1 to the corresponding register bit |
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93 | <li>Hardware: LED state is controlled by corresponding usr_* port |
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94 | </ul> |
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95 | |
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96 | The WARP reference designs use hardware control for the RF LEDs (to indicate real-time Tx/Rx state of each RF interface) and software control |
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97 | for all other LED/hex display outputs. |
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98 | |
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99 | The control source (hw or sw) for each output bit is set by the control register described below. |
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100 | |
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101 | Examples: |
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102 | \code{.c} |
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103 | //Assumes user code sets USERIO_BASEADDR to base address of w3_userio core, as set in xparameters.h |
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104 | |
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105 | //Set both hex dipslays to map 4-bit to 7-segment values automatically |
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106 | userio_write_control(USERIO_BASEADDR, (W3_USERIO_HEXDISP_L_MAPMODE | W3_USERIO_HEXDISP_R_MAPMODE)); |
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107 | |
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108 | //Select software control of all outputs |
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109 | userio_set_ctrlSrc_sw(USERIO_BASEADDR, (W3_USERIO_CTRLSRC_LEDS_RF | W3_USERIO_CTRLSRC_LEDS | W3_USERIO_CTRLSRC_HEXDISPS)); |
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110 | |
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111 | //Select hardware control of RF LEDs |
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112 | userio_set_ctrlSrc_hw(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_RF); |
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113 | |
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114 | //Enable hardware control of green user LEDs, software control of red user LEDs |
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115 | userio_set_ctrlSrc_hw(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_GREEN); |
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116 | userio_set_ctrlSrc_sw(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_RED); |
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117 | \endcode |
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118 | |
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119 | * @{ |
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120 | */ |
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121 | |
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122 | #define userio_read_control(baseaddr) Xil_In32(baseaddr+W3_USERIO_SLV_REG0_OFFSET) //!< Returns the value of the control register |
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123 | #define userio_write_control(baseaddr, x) Xil_Out32(baseaddr+W3_USERIO_SLV_REG0_OFFSET, x) //!< Sets the control register to x |
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124 | |
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125 | #define userio_set_ctrlSrc_hw(baseaddr, ioMask) Xil_Out32(baseaddr+W3_USERIO_SLV_REG0_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG0_OFFSET) | (ioMask))) //!< Sets selected outputs to hardware control (usr_ ports) |
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126 | #define userio_set_ctrlSrc_sw(baseaddr, ioMask) Xil_Out32(baseaddr+W3_USERIO_SLV_REG0_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG0_OFFSET) & ~(ioMask)))//!< Sets selected outputs to software control (register writes) |
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127 | |
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128 | //reg0 masks |
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129 | #define W3_USERIO_HEXDISP_L_MAPMODE 0x20000000 //!< Enables 4-bit to 7-segment mapping for left hex display |
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130 | #define W3_USERIO_HEXDISP_R_MAPMODE 0x10000000 //!< Enables 4-bit to 7-segment mapping for right hex display |
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131 | #define W3_USERIO_CTRLSRC_LED_RFB_RED 0x08000000 //!< Control source selection mask for red LED near RF B |
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132 | #define W3_USERIO_CTRLSRC_LED_RFB_GREEN 0x04000000 //!< Control source selection mask for green LED near RF B |
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133 | #define W3_USERIO_CTRLSRC_LED_RFA_RED 0x02000000 //!< Control source selection mask for red LED near RF A |
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134 | #define W3_USERIO_CTRLSRC_LED_RFA_GREEN 0x01000000 //!< Control source selection mask for green LED near RF A |
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135 | #define W3_USERIO_CTRLSRC_LEDS_RED 0x000F0000 //!< Control source selection mask for the red user LEDs |
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136 | #define W3_USERIO_CTRLSRC_LEDS_GREEN 0x00F00000 //!< Control source selection mask for the green user LEDs |
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137 | #define W3_USERIO_CTRLSRC_HEXDISP_L 0x0000FF00 //!< Control source selection mask for the left hex display |
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138 | #define W3_USERIO_CTRLSRC_HEXDISP_R 0x000000FF //!< Control source selection mask for the right hex display |
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139 | |
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140 | #define W3_USERIO_CTRLSRC_LEDS_RFA (W3_USERIO_CTRLSRC_LED_RFA_RED | W3_USERIO_CTRLSRC_LED_RFA_GREEN) //!< Control source selection masks for both LEDs near RF A |
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141 | #define W3_USERIO_CTRLSRC_LEDS_RFB (W3_USERIO_CTRLSRC_LED_RFB_RED | W3_USERIO_CTRLSRC_LED_RFB_GREEN) //!< Control source selection masks for both LEDs near RF B |
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142 | #define W3_USERIO_CTRLSRC_LEDS_RF (W3_USERIO_CTRLSRC_LEDS_RFA | W3_USERIO_CTRLSRC_LEDS_RFB) //!< Control source selection masks for all RF LEDs |
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143 | #define W3_USERIO_CTRLSRC_LEDS (W3_USERIO_CTRLSRC_LEDS_RED | W3_USERIO_CTRLSRC_LEDS_GREEN) //!< Control source selection masks for all user LEDs |
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144 | #define W3_USERIO_CTRLSRC_HEXDISPS (W3_USERIO_CTRLSRC_HEXDISP_L | W3_USERIO_CTRLSRC_HEXDISP_R) //!< Control source selection masks for both hex displays |
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145 | /** @}*/ |
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146 | |
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147 | |
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148 | /** \defgroup userio_read Reading user IO |
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149 | <b>Note on output state</b>: The macros for reading the current state of user outputs (LEDs, hex displays) can only access outputs configured for software control. Attempts to read the state |
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150 | of outputs configured for hardware control (i.e. outputs with corresponding CTRLSRC_* asserted in control reg) will not reflect actual output state. |
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151 | |
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152 | Examples: |
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153 | \code{.c} |
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154 | //Assumes user code sets USERIO_BASEADDR to base address of w3_userio core, as set in xparameters.h |
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155 | |
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156 | //Check if middle push button is being pressed |
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157 | if(userio_read_inputs(USERIO_BASEADDR) & W3_USERIO_PB_M) {...} |
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158 | |
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159 | //Read 4-bit DIP switch value |
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160 | u8 x = userio_read_inputs(USERIO_BASEADDR) & W3_USERIO_DIPSW; |
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161 | \endcode |
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162 | |
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163 | * \addtogroup userio_read |
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164 | * @{ |
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165 | */ |
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166 | #define userio_read_inputs(baseaddr) Xil_In32(baseaddr+W3_USERIO_SLV_REG6_OFFSET) //!< Returns the current state of the user inputs (buttons and DIP switch) |
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167 | #define userio_read_hexdisp_left(baseaddr) Xil_In32(baseaddr+W3_USERIO_SLV_REG1_OFFSET) //!< Returns the current state of the left hex display outputs |
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168 | #define userio_read_hexdisp_right(baseaddr) Xil_In32(baseaddr+W3_USERIO_SLV_REG2_OFFSET) //!< Returns the current state of the right hex display outputs |
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169 | #define userio_read_leds_red(baseaddr) Xil_In32(baseaddr+W3_USERIO_SLV_REG3_OFFSET) //!< Returns the current state of the red user LEDs |
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170 | #define userio_read_leds_green(baseaddr) Xil_In32(baseaddr+W3_USERIO_SLV_REG4_OFFSET) //!< Returns the current state of the green user LEDs |
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171 | #define userio_read_leds_rf(baseaddr) Xil_In32(baseaddr+W3_USERIO_SLV_REG5_OFFSET) //!< Returns the current state of the RF LEDs |
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172 | /** @}*/ |
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173 | |
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174 | /** \defgroup userio_write Setting user outputs |
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175 | |
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176 | <b>Hex display notes:</b> |
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177 | The w3_userio core implements logic to map 4-bit values to the 7-segment representation of the corresponding hex value. When this mode |
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178 | is enabled via the control register (W3_USERIO_HEXDISP_x_MAPMODE is asserte), user code should write 4-bit values via the hex display macros below. When map |
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179 | mode is disabled, the user value is driven directly to the 7-segments of the hex display. |
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180 | |
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181 | The decimal point on each hex dipslay is controlled by OR'ing 4 bit (in map mode) or 7 bit (in non-map mode) value with W3_USERIO_HEXDISP_DP. |
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182 | |
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183 | Examples: |
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184 | \code{.c} |
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185 | //Assumes user code sets USERIO_BASEADDR to base address of w3_userio core, as set in xparameters.h |
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186 | |
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187 | //Display "B" on the left hex dipslay (assumes map mode is enabled; see control register docs) |
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188 | userio_write_hexdisp_left(USERIO_ADDR, 0xB); |
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189 | |
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190 | //Display "4" on the right hex dipslay and light the decimal point (assumes map mode is enabled; see control register docs) |
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191 | userio_write_hexdisp_right(USERIO_ADDR, (0x4 | W3_USERIO_HEXDISP_DP) ); |
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192 | |
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193 | //Turn off all four green user LEDs |
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194 | userio_write_leds_green(USERIO_ADDR, 0); |
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195 | |
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196 | //Toggle the 2 LSB of the red user LEDs |
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197 | userio_toggle_leds_red(USERIO_ADDR, 0x3); |
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198 | |
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199 | \endcode |
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200 | * \addtogroup userio_write |
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201 | * @{ |
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202 | */ |
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203 | #define userio_write_hexdisp_left(baseaddr, x) Xil_Out32(baseaddr+W3_USERIO_SLV_REG1_OFFSET, x) //!< Sets the left hex dispaly |
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204 | #define userio_write_hexdisp_right(baseaddr, x) Xil_Out32(baseaddr+W3_USERIO_SLV_REG2_OFFSET, x) //!< Sets the right hex dispaly |
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205 | #define userio_write_leds_red(baseaddr, x) Xil_Out32(baseaddr+W3_USERIO_SLV_REG3_OFFSET, x) //!< Sets the 4 red LEDs when configured for software control (software control is default) |
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206 | #define userio_write_leds_green(baseaddr, x) Xil_Out32(baseaddr+W3_USERIO_SLV_REG4_OFFSET, x) //!< Sets the 4 green LEDs when configured for software control (software control is default) |
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207 | #define userio_write_leds_rf(baseaddr, x) Xil_Out32(baseaddr+W3_USERIO_SLV_REG5_OFFSET, x) //!< Sets the 4 RF LEDs when configured for software control (hardware control is default) |
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208 | #define userio_toggle_hexdisp_left(baseaddr, mask) Xil_Out32(baseaddr+W3_USERIO_SLV_REG1_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG1_OFFSET) ^ mask)) //!< Toggles the state of bits selected by mask on left hex display |
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209 | #define userio_toggle_hexdisp_right(baseaddr, mask) Xil_Out32(baseaddr+W3_USERIO_SLV_REG2_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG2_OFFSET) ^ mask)) //!< Toggles the state of bits selected by mask on right hex display |
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210 | #define userio_toggle_leds_red(baseaddr, mask) Xil_Out32(baseaddr+W3_USERIO_SLV_REG3_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG3_OFFSET) ^ mask)) //!< Toggles the state of bits selected by mask in red LEDs |
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211 | #define userio_toggle_leds_green(baseaddr, mask) Xil_Out32(baseaddr+W3_USERIO_SLV_REG4_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG4_OFFSET) ^ mask)) //!< Toggles the state of bits selected by mask in green LEDs |
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212 | #define userio_toggle_leds_rf(baseaddr, mask) Xil_Out32(baseaddr+W3_USERIO_SLV_REG5_OFFSET, (Xil_In32(baseaddr+W3_USERIO_SLV_REG5_OFFSET) ^ mask)) //!< Toggles the state of bits selected by mask in RF LEDs |
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213 | /** @}*/ |
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214 | |
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215 | /** \defgroup userio_masks Masks for user IO elements |
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216 | * \addtogroup userio_masks |
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217 | * @{ |
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218 | */ |
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219 | |
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220 | //reg1/reg2 masks |
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221 | #define W3_USERIO_HEXDISP_DP 0x100 //!< Mask for decimal point LEDs on hex displays |
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222 | |
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223 | //reg5 masks |
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224 | #define W3_USERIO_RFA_LED_GREEN 0x1 //!< Mask for green LED near RF A |
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225 | #define W3_USERIO_RFA_LED_RED 0x2 //!< Mask for red LED near RF A |
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226 | #define W3_USERIO_RFB_LED_GREEN 0x4 //!< Mask for green LED near RF B |
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227 | #define W3_USERIO_RFB_LED_RED 0x8 //!< Mask for red LED near RF B |
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228 | |
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229 | //reg6 masks |
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230 | #define W3_USERIO_PB_U 0x40 //!< Mask for up push button |
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231 | #define W3_USERIO_PB_M 0x20 //!< Mask for middle push button |
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232 | #define W3_USERIO_PB_D 0x10 //!< Mask for down push button |
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233 | #define W3_USERIO_DIPSW 0x0F //!< Mask for 4 positions of DIP switch |
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234 | /** @}*/ |
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235 | |
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236 | /** \defgroup dna_read Reading FPGA DNA |
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237 | Every Virtex-6 FPGA has a unique "DNA" value embedded in the device. The w3_userio core implements logic to read this value into software-accessible registers. The |
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238 | DNA value is 56 bits, so two 32-bit registers are used to store the full value. |
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239 | |
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240 | <b>Hardware requirements:</b> |
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241 | <ul> |
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242 | <li>A clock signal slower than 100MHz must be connected to the w3_userio core DNA_Port_Clk port |
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243 | <li>The w3_userio core parameter INCLUDE_DNA_READ_LOGIC must be enabled |
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244 | </ul> |
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245 | If both requirements aren't met the DNA register values are undefined. |
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246 | |
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247 | The FPGA DNA value is also stored in the WARP v3 board EEPROM. Refer to the user guide EEPROM page for details. |
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248 | * \addtogroup dna_read |
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249 | * @{ |
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250 | */ |
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251 | #define userio_read_fpga_dna_lsb(baseaddr) Xil_In32(baseaddr+W3_USERIO_SLV_REG10_OFFSET) //!< Returns the 32 LSB of the FPGA DNA |
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252 | #define userio_read_fpga_dna_msb(baseaddr) Xil_In32(baseaddr+W3_USERIO_SLV_REG11_OFFSET) //!< Returns the 24 MSB of the FPGA DNA |
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253 | /** @}*/ |
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254 | |
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255 | #endif /** W3_USERIO_H */ |
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256 | |
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