source: PlatformSupport/CustomPeripherals/pcores/w3_w2_radio_io_shim_v1_00_a/hdl/verilog/w3_w2_radio_io_shim.v

module w3_w2_radio_io_shim (
    input [11:0] RFA_RXD_I_12b_i,
    input [11:0] RFA_RXD_Q_12b_i,
    output [13:0] RFA_RXD_I_14b_o,
    output [13:0] RFA_RXD_Q_14b_o,

    output [11:0] RFA_TXD_I_12b_o,
    output [11:0] RFA_TXD_Q_12b_o,
    input  [15:0] RFA_TXD_I_16b_i,
    input  [15:0] RFA_TXD_Q_16b_i,

    input [11:0] RFB_RXD_I_12b_i,
    input [11:0] RFB_RXD_Q_12b_i,
    output [13:0] RFB_RXD_I_14b_o,
    output [13:0] RFB_RXD_Q_14b_o,

    output [11:0] RFB_TXD_I_12b_o,
    output [11:0] RFB_TXD_Q_12b_o,
    input  [15:0] RFB_TXD_I_16b_i,
    input  [15:0] RFB_TXD_Q_16b_i
);

parameter C_FAMILY = "virtex6";

//Fix12_11 ADC -> Fix14_13 user outputs
assign RFA_RXD_I_14b_o = {RFA_RXD_I_12b_i, 2'b0};
assign RFA_RXD_Q_14b_o = {RFA_RXD_Q_12b_i, 2'b0};

assign RFB_RXD_I_14b_o = {RFB_RXD_I_12b_i, 2'b0};
assign RFB_RXD_Q_14b_o = {RFB_RXD_Q_12b_i, 2'b0};

//Fix16_15 user inputs -> Fix12_11 DAC
assign RFA_TXD_I_12b_o = RFA_TXD_I_16b_i[15:4];
assign RFA_TXD_Q_12b_o = RFA_TXD_Q_16b_i[15:4];

assign RFB_TXD_I_12b_o = RFB_TXD_I_16b_i[15:4];
assign RFB_TXD_Q_12b_o = RFB_TXD_Q_16b_i[15:4];

endmodule