source: PlatformSupport/CustomPeripherals/pcores/warp_spi_io_v1_00_a/hdl/verilog/warp_spi_io.v

module warp_spi_io (
    input sys_clk,
    input reset,
    input go,
    input [0:2]  clkDiv,

    input [0:31] txData,

    output reg [0:31] rxData1,
    output reg [0:31] rxData2,
    output reg [0:31] rxData3,
    output reg [0:31] rxData4,

    output done,

    //Current bit index, in case user code needs to switch output enable mid-xfer
    output [0:4] currBitNum,
    
    //SPI signals
    output spi_mosi, //Master-out-slave-in serial data
    output spi_cs,   //Active-high chip select
    output spi_sclk, //Serial clock (masked by spi_cs)

    input spi_miso1, //Dev 1 master-in-slave-out
    input spi_miso2, //Dev 2 master-in-slave-out
    input spi_miso3, //Dev 3 master-in-slave-out
    input spi_miso4  //Dev 4 master-in-slave-out
);

parameter SPI_XFER_LEN = 5'd24;

//Counter to generate SPI clock
// Big enough that clkDiv can index any bit
reg [0:7] spi_clk_counter;

wire spi_clk;
reg spi_clk_d1;
wire spi_clk_pos, spi_clk_neg;

reg go_d1;
wire go_pos;

reg [0:4] spi_xfer_counter;
reg spi_xfer_running, spi_xfer_done;

assign go_pos = go & ~go_d1;

assign spi_cs = spi_xfer_running;
assign currBitNum = spi_xfer_counter;
assign done = spi_xfer_done;

always @(posedge sys_clk)
begin
    if(reset == 1)
        go_d1 <= 1'b0;
    else if(spi_clk_neg)
        go_d1 <= go;
end

//Free-running counter to generate SPI clock
// 1 bit of this counter will be selected as the clock source
always @(posedge sys_clk)
begin
    if(reset == 1)
    begin
        spi_clk_counter <= 6'b0;
        spi_clk_d1 <= 1'b0;
    end
    else
    begin
        spi_clk_counter <= spi_clk_counter + 6'b000001;
        spi_clk_d1 <= spi_clk;
    end
end

//Select a bit of the counter to create the free-running clock
// masked by an active SPI transfer
//User code will mask again by per-device CS
assign spi_clk = spi_clk_counter[clkDiv];
assign spi_sclk = spi_clk & spi_xfer_running;

//Rising/falling edges of spi clk for internal clk enables
assign spi_clk_pos = (spi_clk & ~spi_clk_d1);
assign spi_clk_neg = (~spi_clk & spi_clk_d1);


//SPI transfer status signals
// spi_xfer_running:
//  Asserts when the user signals go
//  De-asserts when the last SPI character bit is processed
// spi_xfer_done
//  Asserts after the last SPI character bit is processed
//  De-asserts when a new SPI transaction starts
always @(posedge sys_clk)
begin
    if(reset == 1)
    begin
        spi_xfer_running <= 1'b0;
        spi_xfer_done <= 1'b0;
    end
    else if( go & (spi_xfer_counter < SPI_XFER_LEN) & spi_clk_neg)
    begin       
        spi_xfer_running <= 1'b1;
        spi_xfer_done <= 1'b0;
    end
    else if(spi_xfer_counter >= SPI_XFER_LEN)
    begin
        spi_xfer_running <= 1'b0;
        spi_xfer_done <= 1'b1;
    end
    else
    begin
        spi_xfer_running <= spi_xfer_running;
        spi_xfer_done <= 1'b0;
    end
end

//Bit-counter for SPI transactions
// Counts from 0 to SPI_XFER_LEN, used to select the current Tx/Rx bit for serial I/O
// Increments on the neg edge of the output SPI clock, so that output data is valid
//  on the arriving rising edge of sclk at SPI slave devices
always @(posedge sys_clk)
begin
    if((reset == 1) || spi_xfer_done)
        spi_xfer_counter <= 5'b0;
    else if (spi_xfer_counter >= (SPI_XFER_LEN))
        spi_xfer_counter <= SPI_XFER_LEN;
    else if (spi_xfer_running & spi_clk_neg)
        spi_xfer_counter <= spi_xfer_counter + 1;
    else
        spi_xfer_counter <= spi_xfer_counter;
end

//Add 1 extra bit to txData, so the bit select below can safely select bit[32]
wire [0:32] txData_safe;
wire [4:0] data_bitSel;
assign data_bitSel = spi_xfer_counter + (32-SPI_XFER_LEN);
assign txData_safe = {txData, 1'b0};

//SPI data out is one bit from txData
// The least significant SPI_XFER_LEN bits of txData are used
// Data is transmitted MSB first
//Example: for SPI_XFER_LEN=24, txData[8:31] is used, with txData[8] sent first, txData[31] last
assign spi_mosi = spi_xfer_running ? txData_safe[data_bitSel] : 1'b0;

//Second condition used to be:
// else if(spi_xfer_running & spi_rnw & (spi_xfer_counter >= SPI_FIRST_RXBIT) & spi_clk_freerun_neg)
// Don't care about rnw at this level anymore (right?)
//data capture used to be:
//      if(~ad1_spi_cs_n)
//          rxByte1[spi_xfer_counter - SPI_FIRST_RXBIT] <= ad1_spi_miso;
            
always @(posedge sys_clk)
begin
    if(reset == 1)
    begin
        rxData1 <= 32'b0;
        rxData2 <= 32'b0;
        rxData3 <= 32'b0;
        rxData4 <= 32'b0;
    end
//  else if(spi_xfer_running & spi_clk_neg)
    else if(spi_xfer_running & spi_clk_pos)
    begin
        rxData1[data_bitSel] <= spi_miso1;
        rxData2[data_bitSel] <= spi_miso2;
        rxData3[data_bitSel] <= spi_miso3;
        rxData4[data_bitSel] <= spi_miso4;
    end
    else
    begin
        rxData1 <= rxData1;
        rxData2 <= rxData2;
        rxData3 <= rxData3;
        rxData4 <= rxData4;
    end
end

endmodule