source: PlatformSupport/CustomPeripherals/pcores/warp_timer_plbw_v1_00_a/data/warp_timer_plbw_v2_1_0.mpd

## Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

## You may copy and modify these files for your own internal use solely with
## Xilinx programmable logic devices and  Xilinx EDK system or create IP
## modules solely for Xilinx programmable logic devices and Xilinx EDK system.
## No rights are granted to distribute any files unless they are distributed in
## Xilinx programmable logic devices.

BEGIN warp_timer_plbw

## Peripheral Options
OPTION RUN_NGCBUILD = TRUE
OPTION IMP_NETLIST = TRUE
OPTION STYLE = MIX
OPTION HDL = MIXED
OPTION IPTYPE = PERIPHERAL
OPTION LAST_UPDATED = 10.1.2.1250
OPTION USAGE_LEVEL = BASE_USER


## Bus Interfaces
BUS_INTERFACE BUS = SPLB, BUS_STD = PLBV46, BUS_TYPE = SLAVE

## Generics for VHDL or Parameters for Verilog
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector(0 to 31), BUS = SPLB, ADDRESS = BASE, PAIR = C_HIGHADDR, MIN_SIZE = 0x1000, ASSIGNMENT = REQUIRE
PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector(0 to 31), BUS = SPLB, ADDRESS = HIGH, PAIR = C_BASEADDR, ASSIGNMENT = REQUIRE
PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_DWIDTH = 32, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_MID_WIDTH = 1, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_NUM_MASTERS = 1, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_SUPPORT_BURSTS = 0, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT

# Memory Map Information
# From Registers
PARAMETER C_MEMMAP_TIMER0_TIMELEFT = 0x814, DT = integer, ASSIGNMENT = CONSTANT 
PARAMETER C_MEMMAP_TIMER0_TIMELEFT_N_BITS = 32, DT = integer, ASSIGNMENT = CONSTANT 
PARAMETER C_MEMMAP_TIMER0_TIMELEFT_BIN_PT = 0, DT = integer, ASSIGNMENT = CONSTANT
PARAMETER C_MEMMAP_TIMER1_TIMELEFT = 0x818, DT = integer, ASSIGNMENT = CONSTANT 
PARAMETER C_MEMMAP_TIMER1_TIMELEFT_N_BITS = 32, DT = integer, ASSIGNMENT = CONSTANT 
PARAMETER C_MEMMAP_TIMER1_TIMELEFT_BIN_PT = 0, DT = integer, ASSIGNMENT = CONSTANT
PARAMETER C_MEMMAP_TIMER2_TIMELEFT = 0x81C, DT = integer, ASSIGNMENT = CONSTANT 
PARAMETER C_MEMMAP_TIMER2_TIMELEFT_N_BITS = 32, DT = integer, ASSIGNMENT = CONSTANT 
PARAMETER C_MEMMAP_TIMER2_TIMELEFT_BIN_PT = 0, DT = integer, ASSIGNMENT = CONSTANT
PARAMETER C_MEMMAP_TIMER3_TIMELEFT = 0x820, DT = integer, ASSIGNMENT = CONSTANT 
PARAMETER C_MEMMAP_TIMER3_TIMELEFT_N_BITS = 32, DT = integer, ASSIGNMENT = CONSTANT 
PARAMETER C_MEMMAP_TIMER3_TIMELEFT_BIN_PT = 0, DT = integer, ASSIGNMENT = CONSTANT
PARAMETER C_MEMMAP_TIMER_CONTROL_R = 0x824, DT = integer, ASSIGNMENT = CONSTANT 
PARAMETER C_MEMMAP_TIMER_CONTROL_R_N_BITS = 32, DT = integer, ASSIGNMENT = CONSTANT 
PARAMETER C_MEMMAP_TIMER_CONTROL_R_BIN_PT = 0, DT = integer, ASSIGNMENT = CONSTANT
PARAMETER C_MEMMAP_TIMER_STATUS = 0x828, DT = integer, ASSIGNMENT = CONSTANT 
PARAMETER C_MEMMAP_TIMER_STATUS_N_BITS = 32, DT = integer, ASSIGNMENT = CONSTANT 
PARAMETER C_MEMMAP_TIMER_STATUS_BIN_PT = 0, DT = integer, ASSIGNMENT = CONSTANT
# To Registers
PARAMETER C_MEMMAP_TIMER0_COUNTTO = 0x800, DT = integer, ASSIGNMENT = CONSTANT
PARAMETER C_MEMMAP_TIMER0_COUNTTO_N_BITS = 32, DT = integer, ASSIGNMENT = CONSTANT
PARAMETER C_MEMMAP_TIMER0_COUNTTO_BIN_PT = 0, DT = integer, ASSIGNMENT = CONSTANT 
PARAMETER C_MEMMAP_TIMER1_COUNTTO = 0x804, DT = integer, ASSIGNMENT = CONSTANT
PARAMETER C_MEMMAP_TIMER1_COUNTTO_N_BITS = 32, DT = integer, ASSIGNMENT = CONSTANT
PARAMETER C_MEMMAP_TIMER1_COUNTTO_BIN_PT = 0, DT = integer, ASSIGNMENT = CONSTANT 
PARAMETER C_MEMMAP_TIMER2_COUNTTO = 0x808, DT = integer, ASSIGNMENT = CONSTANT
PARAMETER C_MEMMAP_TIMER2_COUNTTO_N_BITS = 32, DT = integer, ASSIGNMENT = CONSTANT
PARAMETER C_MEMMAP_TIMER2_COUNTTO_BIN_PT = 0, DT = integer, ASSIGNMENT = CONSTANT 
PARAMETER C_MEMMAP_TIMER3_COUNTTO = 0x80C, DT = integer, ASSIGNMENT = CONSTANT
PARAMETER C_MEMMAP_TIMER3_COUNTTO_N_BITS = 32, DT = integer, ASSIGNMENT = CONSTANT
PARAMETER C_MEMMAP_TIMER3_COUNTTO_BIN_PT = 0, DT = integer, ASSIGNMENT = CONSTANT 
PARAMETER C_MEMMAP_TIMER_CONTROL_W = 0x810, DT = integer, ASSIGNMENT = CONSTANT
PARAMETER C_MEMMAP_TIMER_CONTROL_W_N_BITS = 32, DT = integer, ASSIGNMENT = CONSTANT
PARAMETER C_MEMMAP_TIMER_CONTROL_W_BIN_PT = 0, DT = integer, ASSIGNMENT = CONSTANT 
# From FIFOs
# To FIFOs
# Shared RAMs

# Ports (Export flow)
PORT splb_clk = "", DIR = I, SIGIS = clk, BUS = SPLB
PORT idlefordifs = "", DIR = I
PORT plb_abus = plb_abus, DIR = I, VEC = [0:(32-1)], BUS = SPLB
PORT plb_pavalid = plb_pavalid, DIR = I, BUS = SPLB
PORT plb_rnw = plb_rnw, DIR = I, BUS = SPLB
PORT plb_wrdbus = plb_wrdbus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
PORT splb_rst = splb_rst, DIR = I, SIGIS = rst, BUS = SPLB

PORT sl_addrack = sl_addrack, DIR = O, BUS = SPLB
PORT sl_rdcomp = sl_rdcomp, DIR = O, BUS = SPLB
PORT sl_rddack = sl_rddack, DIR = O, BUS = SPLB
PORT sl_rddbus = sl_rddbus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
PORT sl_wait = sl_wait, DIR = O, BUS = SPLB
PORT sl_wrcomp = sl_wrcomp, DIR = O, BUS = SPLB
PORT sl_wrdack = sl_wrdack, DIR = O, BUS = SPLB
PORT timer0_active = "", DIR = O
PORT timer1_active = "", DIR = O
PORT timer2_active = "", DIR = O
PORT timer3_active = "", DIR = O
PORT timerexpire = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH, INTERRUPT_PRIORITY = HIGH                  



END