source: PlatformSupport/CustomPeripherals/pcores/warp_v4_userio_v1_00_a/hdl/verilog/hex_out.v

Last change on this file was 1331, checked in by sgupta, 15 years ago

userio core for V4
  • Property svn:executable set to *
File size: 163.0 KB
Line 
1////////////////////////////////////////////////////////////////////////////////
2// Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
3////////////////////////////////////////////////////////////////////////////////
4//   ____  ____
5//  /   /\/   /
6// /___/  \  /    Vendor: Xilinx
7// \   \   \/     Version: K.39
8//  \   \         Application: netgen
9//  /   /         Filename: adder_subtracter_virtex4_10_0_80b315fd28a09ef0.v
10// /___/   /\     Timestamp: Thu Oct 01 13:34:30 2009
11// \   \  /  \
12//  \___\/\___\
13//             
14// Command  : -intstyle ise -w -sim -ofmt verilog .\tmp\_cg\adder_subtracter_virtex4_10_0_80b315fd28a09ef0.ngc .\tmp\_cg\adder_subtracter_virtex4_10_0_80b315fd28a09ef0.v
15// Device   : 4vfx12sf363-12
16// Input file   : ./tmp/_cg/adder_subtracter_virtex4_10_0_80b315fd28a09ef0.ngc
17// Output file  : ./tmp/_cg/adder_subtracter_virtex4_10_0_80b315fd28a09ef0.v
18// # of Modules : 1
19// Design Name  : adder_subtracter_virtex4_10_0_80b315fd28a09ef0
20// Xilinx        : c:\xilinx\10.1\ise
21//             
22// Purpose:   
23//     This verilog netlist is a verification model and uses simulation
24//     primitives which may not represent the true implementation of the
25//     device, however the netlist is functionally correct and should not
26//     be modified. This file cannot be synthesized and should only be used
27//     with supported simulation tools.
28//             
29// Reference: 
30//     Development System Reference Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
31//             
32////////////////////////////////////////////////////////////////////////////////
33
34`timescale 1 ns/1 ps
35
36module adder_subtracter_virtex4_10_0_80b315fd28a09ef0 (
37a, b, s
38);
39  input [10 : 0] a;
40  input [10 : 0] b;
41  output [10 : 0] s;
42 
43  // synthesis translate_off
44 
45  wire \BU2/N1 ;
46  wire \BU2/c_out ;
47  wire NLW_VCC_P_UNCONNECTED;
48  wire NLW_GND_G_UNCONNECTED;
49  wire [10 : 0] \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum ;
50  wire [9 : 0] \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple ;
51  VCC   VCC_0 (
52    .P(NLW_VCC_P_UNCONNECTED)
53  );
54  GND   GND_1 (
55    .G(NLW_GND_G_UNCONNECTED)
56  );
57  LUT2 #(
58    .INIT ( 4'h9 ))
59  \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mxor_halfsum_Result(0)1  (
60    .I0(b[0]),
61    .I1(a[0]),
62    .O(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [0])
63  );
64  LUT2 #(
65    .INIT ( 4'h9 ))
66  \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mxor_halfsum_Result(1)1  (
67    .I0(b[1]),
68    .I1(a[1]),
69    .O(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [1])
70  );
71  LUT2 #(
72    .INIT ( 4'h9 ))
73  \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mxor_halfsum_Result(2)1  (
74    .I0(b[2]),
75    .I1(a[2]),
76    .O(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [2])
77  );
78  LUT2 #(
79    .INIT ( 4'h9 ))
80  \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mxor_halfsum_Result(3)1  (
81    .I0(b[3]),
82    .I1(a[3]),
83    .O(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [3])
84  );
85  LUT2 #(
86    .INIT ( 4'h9 ))
87  \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mxor_halfsum_Result(4)1  (
88    .I0(b[4]),
89    .I1(a[4]),
90    .O(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [4])
91  );
92  LUT2 #(
93    .INIT ( 4'h9 ))
94  \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mxor_halfsum_Result(5)1  (
95    .I0(b[5]),
96    .I1(a[5]),
97    .O(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [5])
98  );
99  LUT2 #(
100    .INIT ( 4'h9 ))
101  \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mxor_halfsum_Result(6)1  (
102    .I0(b[6]),
103    .I1(a[6]),
104    .O(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [6])
105  );
106  LUT2 #(
107    .INIT ( 4'h9 ))
108  \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mxor_halfsum_Result(7)1  (
109    .I0(b[7]),
110    .I1(a[7]),
111    .O(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [7])
112  );
113  LUT2 #(
114    .INIT ( 4'h9 ))
115  \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mxor_halfsum_Result(8)1  (
116    .I0(b[8]),
117    .I1(a[8]),
118    .O(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [8])
119  );
120  LUT2 #(
121    .INIT ( 4'h9 ))
122  \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mxor_halfsum_Result(9)1  (
123    .I0(b[9]),
124    .I1(a[9]),
125    .O(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [9])
126  );
127  LUT2 #(
128    .INIT ( 4'h9 ))
129  \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/Mxor_halfsum_Result(10)1  (
130    .I0(b[10]),
131    .I1(a[10]),
132    .O(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [10])
133  );
134  MUXCY   \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0  (
135    .CI(\BU2/N1 ),
136    .DI(a[0]),
137    .S(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [0]),
138    .O(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [0])
139  );
140  XORCY   \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0  (
141    .CI(\BU2/N1 ),
142    .LI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [0]),
143    .O(s[0])
144  );
145  XORCY   \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop  (
146    .CI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [9]),
147    .LI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [10]),
148    .O(s[10])
149  );
150  MUXCY   \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux  (
151    .CI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [0]),
152    .DI(a[1]),
153    .S(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [1]),
154    .O(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [1])
155  );
156  XORCY   \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor  (
157    .CI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [0]),
158    .LI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [1]),
159    .O(s[1])
160  );
161  MUXCY   \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux  (
162    .CI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [1]),
163    .DI(a[2]),
164    .S(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [2]),
165    .O(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [2])
166  );
167  XORCY   \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor  (
168    .CI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [1]),
169    .LI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [2]),
170    .O(s[2])
171  );
172  MUXCY   \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux  (
173    .CI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [2]),
174    .DI(a[3]),
175    .S(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [3]),
176    .O(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [3])
177  );
178  XORCY   \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor  (
179    .CI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [2]),
180    .LI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [3]),
181    .O(s[3])
182  );
183  MUXCY   \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux  (
184    .CI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [3]),
185    .DI(a[4]),
186    .S(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [4]),
187    .O(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [4])
188  );
189  XORCY   \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor  (
190    .CI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [3]),
191    .LI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [4]),
192    .O(s[4])
193  );
194  MUXCY   \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux  (
195    .CI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [4]),
196    .DI(a[5]),
197    .S(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [5]),
198    .O(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [5])
199  );
200  XORCY   \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor  (
201    .CI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [4]),
202    .LI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [5]),
203    .O(s[5])
204  );
205  MUXCY   \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux  (
206    .CI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [5]),
207    .DI(a[6]),
208    .S(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [6]),
209    .O(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [6])
210  );
211  XORCY   \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor  (
212    .CI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [5]),
213    .LI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [6]),
214    .O(s[6])
215  );
216  MUXCY   \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux  (
217    .CI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [6]),
218    .DI(a[7]),
219    .S(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [7]),
220    .O(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [7])
221  );
222  XORCY   \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor  (
223    .CI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [6]),
224    .LI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [7]),
225    .O(s[7])
226  );
227  MUXCY   \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux  (
228    .CI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [7]),
229    .DI(a[8]),
230    .S(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [8]),
231    .O(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [8])
232  );
233  XORCY   \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor  (
234    .CI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [7]),
235    .LI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [8]),
236    .O(s[8])
237  );
238  MUXCY   \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carrymux  (
239    .CI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [8]),
240    .DI(a[9]),
241    .S(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [9]),
242    .O(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [9])
243  );
244  XORCY   \BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[9].carryxor  (
245    .CI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [8]),
246    .LI(\BU2/U0/addsub_v9_1.i_addsub_v9_1/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [9]),
247    .O(s[9])
248  );
249  VCC   \BU2/XST_VCC  (
250    .P(\BU2/N1 )
251  );
252  GND   \BU2/XST_GND  (
253    .G(\BU2/c_out )
254  );
255
256// synthesis translate_on
257
258endmodule
259
260// synthesis translate_off
261
262`timescale  1 ps / 1 ps
263
264module glbl ();
265
266    parameter ROC_WIDTH = 100000;
267    parameter TOC_WIDTH = 0;
268
269    wire GSR;
270    wire GTS;
271    wire PRLD;
272
273    reg GSR_int;
274    reg GTS_int;
275    reg PRLD_int;
276
277//--------   JTAG Globals --------------
278    wire JTAG_TDO_GLBL;
279    wire JTAG_TCK_GLBL;
280    wire JTAG_TDI_GLBL;
281    wire JTAG_TMS_GLBL;
282    wire JTAG_TRST_GLBL;
283
284    reg JTAG_CAPTURE_GLBL;
285    reg JTAG_RESET_GLBL;
286    reg JTAG_SHIFT_GLBL;
287    reg JTAG_UPDATE_GLBL;
288
289    reg JTAG_SEL1_GLBL = 0;
290    reg JTAG_SEL2_GLBL = 0 ;
291    reg JTAG_SEL3_GLBL = 0;
292    reg JTAG_SEL4_GLBL = 0;
293
294    reg JTAG_USER_TDO1_GLBL = 1'bz;
295    reg JTAG_USER_TDO2_GLBL = 1'bz;
296    reg JTAG_USER_TDO3_GLBL = 1'bz;
297    reg JTAG_USER_TDO4_GLBL = 1'bz;
298
299    assign (weak1, weak0) GSR = GSR_int;
300    assign (weak1, weak0) GTS = GTS_int;
301    assign (weak1, weak0) PRLD = PRLD_int;
302
303    initial begin
304    GSR_int = 1'b1;
305    PRLD_int = 1'b1;
306    #(ROC_WIDTH)
307    GSR_int = 1'b0;
308    PRLD_int = 1'b0;
309    end
310
311    initial begin
312    GTS_int = 1'b1;
313    #(TOC_WIDTH)
314    GTS_int = 1'b0;
315    end
316
317endmodule
318
319// synthesis translate_on
320////////////////////////////////////////////////////////////////////////////////
321// Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
322////////////////////////////////////////////////////////////////////////////////
323//   ____  ____
324//  /   /\/   /
325// /___/  \  /    Vendor: Xilinx
326// \   \   \/     Version: K.39
327//  \   \         Application: netgen
328//  /   /         Filename: binary_counter_virtex4_10_0_0e77c8b832175d2c.v
329// /___/   /\     Timestamp: Thu Oct 01 13:34:45 2009
330// \   \  /  \
331//  \___\/\___\
332//             
333// Command  : -intstyle ise -w -sim -ofmt verilog .\tmp\_cg\binary_counter_virtex4_10_0_0e77c8b832175d2c.ngc .\tmp\_cg\binary_counter_virtex4_10_0_0e77c8b832175d2c.v
334// Device   : 4vfx12sf363-12
335// Input file   : ./tmp/_cg/binary_counter_virtex4_10_0_0e77c8b832175d2c.ngc
336// Output file  : ./tmp/_cg/binary_counter_virtex4_10_0_0e77c8b832175d2c.v
337// # of Modules : 1
338// Design Name  : binary_counter_virtex4_10_0_0e77c8b832175d2c
339// Xilinx        : c:\xilinx\10.1\ise
340//             
341// Purpose:   
342//     This verilog netlist is a verification model and uses simulation
343//     primitives which may not represent the true implementation of the
344//     device, however the netlist is functionally correct and should not
345//     be modified. This file cannot be synthesized and should only be used
346//     with supported simulation tools.
347//             
348// Reference: 
349//     Development System Reference Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
350//             
351////////////////////////////////////////////////////////////////////////////////
352
353`timescale 1 ns/1 ps
354
355module binary_counter_virtex4_10_0_0e77c8b832175d2c (
356  ce, sinit, clk, q
357);
358  input ce;
359  input sinit;
360  input clk;
361  output [9 : 0] q;
362 
363  // synthesis translate_off
364 
365  wire \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop_rt_40 ;
366  wire \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux_rt_38 ;
367  wire \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux_rt_35 ;
368  wire \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux_rt_32 ;
369  wire \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux_rt_29 ;
370  wire \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux_rt_26 ;
371  wire \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux_rt_23 ;
372  wire \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux_rt_20 ;
373  wire \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux_rt_16 ;
374  wire \BU2/N0 ;
375  wire \BU2/thresh0 ;
376  wire NLW_VCC_P_UNCONNECTED;
377  wire NLW_GND_G_UNCONNECTED;
378  wire [9 : 0] NlwRenamedSig_OI_q;
379  wire [9 : 0] \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/s ;
380  wire [0 : 0] \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum ;
381  wire [8 : 0] \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple ;
382  assign
383    q[9] = NlwRenamedSig_OI_q[9],
384    q[8] = NlwRenamedSig_OI_q[8],
385    q[7] = NlwRenamedSig_OI_q[7],
386    q[6] = NlwRenamedSig_OI_q[6],
387    q[5] = NlwRenamedSig_OI_q[5],
388    q[4] = NlwRenamedSig_OI_q[4],
389    q[3] = NlwRenamedSig_OI_q[3],
390    q[2] = NlwRenamedSig_OI_q[2],
391    q[1] = NlwRenamedSig_OI_q[1],
392    q[0] = NlwRenamedSig_OI_q[0];
393  VCC   VCC_0 (
394    .P(NLW_VCC_P_UNCONNECTED)
395  );
396  GND   GND_1 (
397    .G(NLW_GND_G_UNCONNECTED)
398  );
399  INV   \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum_not00001_INV_0  (
400    .I(NlwRenamedSig_OI_q[0]),
401    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [0])
402  );
403  LUT1 #(
404    .INIT ( 2'h2 ))
405  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop_rt  (
406    .I0(NlwRenamedSig_OI_q[9]),
407    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop_rt_40 )
408  );
409  LUT1 #(
410    .INIT ( 2'h2 ))
411  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux_rt  (
412    .I0(NlwRenamedSig_OI_q[1]),
413    .O
414(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux_rt_38 )
415
416  );
417  LUT1 #(
418    .INIT ( 2'h2 ))
419  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux_rt  (
420    .I0(NlwRenamedSig_OI_q[2]),
421    .O
422(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux_rt_35 )
423
424  );
425  LUT1 #(
426    .INIT ( 2'h2 ))
427  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux_rt  (
428    .I0(NlwRenamedSig_OI_q[3]),
429    .O
430(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux_rt_32 )
431
432  );
433  LUT1 #(
434    .INIT ( 2'h2 ))
435  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux_rt  (
436    .I0(NlwRenamedSig_OI_q[4]),
437    .O
438(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux_rt_29 )
439
440  );
441  LUT1 #(
442    .INIT ( 2'h2 ))
443  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux_rt  (
444    .I0(NlwRenamedSig_OI_q[5]),
445    .O
446(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux_rt_26 )
447
448  );
449  LUT1 #(
450    .INIT ( 2'h2 ))
451  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux_rt  (
452    .I0(NlwRenamedSig_OI_q[6]),
453    .O
454(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux_rt_23 )
455
456  );
457  LUT1 #(
458    .INIT ( 2'h2 ))
459  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux_rt  (
460    .I0(NlwRenamedSig_OI_q[7]),
461    .O
462(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux_rt_20 )
463
464  );
465  LUT1 #(
466    .INIT ( 2'h2 ))
467  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux_rt  (
468    .I0(NlwRenamedSig_OI_q[8]),
469    .O
470(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux_rt_16 )
471
472  );
473  FDRE #(
474    .INIT ( 1'b0 ))
475  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/fd/output_1  (
476    .C(clk),
477    .CE(ce),
478    .D(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/s [0]),
479    .R(sinit),
480    .Q(NlwRenamedSig_OI_q[0])
481  );
482  FDRE #(
483    .INIT ( 1'b0 ))
484  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/fd/output_2  (
485    .C(clk),
486    .CE(ce),
487    .D(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/s [1]),
488    .R(sinit),
489    .Q(NlwRenamedSig_OI_q[1])
490  );
491  FDRE #(
492    .INIT ( 1'b0 ))
493  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/fd/output_3  (
494    .C(clk),
495    .CE(ce),
496    .D(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/s [2]),
497    .R(sinit),
498    .Q(NlwRenamedSig_OI_q[2])
499  );
500  FDRE #(
501    .INIT ( 1'b0 ))
502  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/fd/output_4  (
503    .C(clk),
504    .CE(ce),
505    .D(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/s [3]),
506    .R(sinit),
507    .Q(NlwRenamedSig_OI_q[3])
508  );
509  FDRE #(
510    .INIT ( 1'b0 ))
511  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/fd/output_5  (
512    .C(clk),
513    .CE(ce),
514    .D(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/s [4]),
515    .R(sinit),
516    .Q(NlwRenamedSig_OI_q[4])
517  );
518  FDRE #(
519    .INIT ( 1'b0 ))
520  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/fd/output_6  (
521    .C(clk),
522    .CE(ce),
523    .D(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/s [5]),
524    .R(sinit),
525    .Q(NlwRenamedSig_OI_q[5])
526  );
527  FDRE #(
528    .INIT ( 1'b0 ))
529  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/fd/output_7  (
530    .C(clk),
531    .CE(ce),
532    .D(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/s [6]),
533    .R(sinit),
534    .Q(NlwRenamedSig_OI_q[6])
535  );
536  FDRE #(
537    .INIT ( 1'b0 ))
538  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/fd/output_8  (
539    .C(clk),
540    .CE(ce),
541    .D(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/s [7]),
542    .R(sinit),
543    .Q(NlwRenamedSig_OI_q[7])
544  );
545  FDRE #(
546    .INIT ( 1'b0 ))
547  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/fd/output_9  (
548    .C(clk),
549    .CE(ce),
550    .D(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/s [8]),
551    .R(sinit),
552    .Q(NlwRenamedSig_OI_q[8])
553  );
554  FDRE #(
555    .INIT ( 1'b0 ))
556  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/fd/output_10  (
557    .C(clk),
558    .CE(ce),
559    .D(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/s [9]),
560    .R(sinit),
561    .Q(NlwRenamedSig_OI_q[9])
562  );
563  MUXCY   \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0  (
564    .CI(\BU2/N0 ),
565    .DI(\BU2/thresh0 ),
566    .S(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [0]),
567    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [0])
568  );
569  XORCY   \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0  (
570    .CI(\BU2/N0 ),
571    .LI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [0]),
572    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/s [0])
573  );
574  XORCY   \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop  (
575    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [8]),
576    .LI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop_rt_40 ),
577    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/s [9])
578  );
579  MUXCY 
580  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux  (
581    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [0]),
582    .DI(\BU2/N0 ),
583    .S
584(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux_rt_38 )
585,
586    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [1])
587  );
588  XORCY 
589  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor  (
590    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [0]),
591    .LI
592(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux_rt_38 )
593,
594    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/s [1])
595  );
596  MUXCY 
597  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux  (
598    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [1]),
599    .DI(\BU2/N0 ),
600    .S
601(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux_rt_35 )
602,
603    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [2])
604  );
605  XORCY 
606  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor  (
607    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [1]),
608    .LI
609(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux_rt_35 )
610,
611    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/s [2])
612  );
613  MUXCY 
614  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux  (
615    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [2]),
616    .DI(\BU2/N0 ),
617    .S
618(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux_rt_32 )
619,
620    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [3])
621  );
622  XORCY 
623  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor  (
624    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [2]),
625    .LI
626(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux_rt_32 )
627,
628    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/s [3])
629  );
630  MUXCY 
631  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux  (
632    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [3]),
633    .DI(\BU2/N0 ),
634    .S
635(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux_rt_29 )
636,
637    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [4])
638  );
639  XORCY 
640  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor  (
641    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [3]),
642    .LI
643(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux_rt_29 )
644,
645    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/s [4])
646  );
647  MUXCY 
648  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux  (
649    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [4]),
650    .DI(\BU2/N0 ),
651    .S
652(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux_rt_26 )
653,
654    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [5])
655  );
656  XORCY 
657  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carryxor  (
658    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [4]),
659    .LI
660(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[5].carrymux_rt_26 )
661,
662    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/s [5])
663  );
664  MUXCY 
665  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux  (
666    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [5]),
667    .DI(\BU2/N0 ),
668    .S
669(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux_rt_23 )
670,
671    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [6])
672  );
673  XORCY 
674  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carryxor  (
675    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [5]),
676    .LI
677(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[6].carrymux_rt_23 )
678,
679    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/s [6])
680  );
681  MUXCY 
682  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux  (
683    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [6]),
684    .DI(\BU2/N0 ),
685    .S
686(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux_rt_20 )
687,
688    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [7])
689  );
690  XORCY 
691  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carryxor  (
692    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [6]),
693    .LI
694(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[7].carrymux_rt_20 )
695,
696    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/s [7])
697  );
698  MUXCY 
699  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux  (
700    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [7]),
701    .DI(\BU2/N0 ),
702    .S
703(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux_rt_16 )
704,
705    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [8])
706  );
707  XORCY 
708  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carryxor  (
709    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [7]),
710    .LI
711(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[8].carrymux_rt_16 )
712,
713    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/s [8])
714  );
715  VCC   \BU2/XST_VCC  (
716    .P(\BU2/thresh0 )
717  );
718  GND   \BU2/XST_GND  (
719    .G(\BU2/N0 )
720  );
721
722// synthesis translate_on
723
724endmodule
725
726// synthesis translate_off
727
728`timescale  1 ps / 1 ps
729
730module glbl ();
731
732    parameter ROC_WIDTH = 100000;
733    parameter TOC_WIDTH = 0;
734
735    wire GSR;
736    wire GTS;
737    wire PRLD;
738
739    reg GSR_int;
740    reg GTS_int;
741    reg PRLD_int;
742
743//--------   JTAG Globals --------------
744    wire JTAG_TDO_GLBL;
745    wire JTAG_TCK_GLBL;
746    wire JTAG_TDI_GLBL;
747    wire JTAG_TMS_GLBL;
748    wire JTAG_TRST_GLBL;
749
750    reg JTAG_CAPTURE_GLBL;
751    reg JTAG_RESET_GLBL;
752    reg JTAG_SHIFT_GLBL;
753    reg JTAG_UPDATE_GLBL;
754
755    reg JTAG_SEL1_GLBL = 0;
756    reg JTAG_SEL2_GLBL = 0 ;
757    reg JTAG_SEL3_GLBL = 0;
758    reg JTAG_SEL4_GLBL = 0;
759
760    reg JTAG_USER_TDO1_GLBL = 1'bz;
761    reg JTAG_USER_TDO2_GLBL = 1'bz;
762    reg JTAG_USER_TDO3_GLBL = 1'bz;
763    reg JTAG_USER_TDO4_GLBL = 1'bz;
764
765    assign (weak1, weak0) GSR = GSR_int;
766    assign (weak1, weak0) GTS = GTS_int;
767    assign (weak1, weak0) PRLD = PRLD_int;
768
769    initial begin
770    GSR_int = 1'b1;
771    PRLD_int = 1'b1;
772    #(ROC_WIDTH)
773    GSR_int = 1'b0;
774    PRLD_int = 1'b0;
775    end
776
777    initial begin
778    GTS_int = 1'b1;
779    #(TOC_WIDTH)
780    GTS_int = 1'b0;
781    end
782
783endmodule
784
785// synthesis translate_on
786////////////////////////////////////////////////////////////////////////////////
787// Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
788////////////////////////////////////////////////////////////////////////////////
789//   ____  ____
790//  /   /\/   /
791// /___/  \  /    Vendor: Xilinx
792// \   \   \/     Version: K.39
793//  \   \         Application: netgen
794//  /   /         Filename: binary_counter_virtex4_10_0_407917162894eacc.v
795// /___/   /\     Timestamp: Thu Oct 01 13:35:00 2009
796// \   \  /  \
797//  \___\/\___\
798//             
799// Command  : -intstyle ise -w -sim -ofmt verilog .\tmp\_cg\binary_counter_virtex4_10_0_407917162894eacc.ngc .\tmp\_cg\binary_counter_virtex4_10_0_407917162894eacc.v
800// Device   : 4vfx12sf363-12
801// Input file   : ./tmp/_cg/binary_counter_virtex4_10_0_407917162894eacc.ngc
802// Output file  : ./tmp/_cg/binary_counter_virtex4_10_0_407917162894eacc.v
803// # of Modules : 1
804// Design Name  : binary_counter_virtex4_10_0_407917162894eacc
805// Xilinx        : c:\xilinx\10.1\ise
806//             
807// Purpose:   
808//     This verilog netlist is a verification model and uses simulation
809//     primitives which may not represent the true implementation of the
810//     device, however the netlist is functionally correct and should not
811//     be modified. This file cannot be synthesized and should only be used
812//     with supported simulation tools.
813//             
814// Reference: 
815//     Development System Reference Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
816//             
817////////////////////////////////////////////////////////////////////////////////
818
819`timescale 1 ns/1 ps
820
821module binary_counter_virtex4_10_0_407917162894eacc (
822  ce, sinit, clk, q
823);
824  input ce;
825  input sinit;
826  input clk;
827  output [1 : 0] q;
828 
829  // synthesis translate_off
830 
831  wire \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop_rt_10 ;
832  wire \BU2/N0 ;
833  wire \BU2/thresh0 ;
834  wire NLW_VCC_P_UNCONNECTED;
835  wire NLW_GND_G_UNCONNECTED;
836  wire [1 : 0] NlwRenamedSig_OI_q;
837  wire [0 : 0] \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum ;
838  wire [0 : 0] \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple ;
839  wire [1 : 0] \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/s ;
840  assign
841    q[1] = NlwRenamedSig_OI_q[1],
842    q[0] = NlwRenamedSig_OI_q[0];
843  VCC   VCC_0 (
844    .P(NLW_VCC_P_UNCONNECTED)
845  );
846  GND   GND_1 (
847    .G(NLW_GND_G_UNCONNECTED)
848  );
849  INV   \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum_not00001_INV_0  (
850    .I(NlwRenamedSig_OI_q[0]),
851    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [0])
852  );
853  LUT1 #(
854    .INIT ( 2'h2 ))
855  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop_rt  (
856    .I0(NlwRenamedSig_OI_q[1]),
857    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop_rt_10 )
858  );
859  MUXCY   \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0  (
860    .CI(\BU2/N0 ),
861    .DI(\BU2/thresh0 ),
862    .S(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [0]),
863    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [0])
864  );
865  XORCY   \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0  (
866    .CI(\BU2/N0 ),
867    .LI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [0]),
868    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/s [0])
869  );
870  XORCY   \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop  (
871    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [0]),
872    .LI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop_rt_10 ),
873    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/s [1])
874  );
875  FDRE #(
876    .INIT ( 1'b0 ))
877  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/fd/output_1  (
878    .C(clk),
879    .CE(ce),
880    .D(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/s [0]),
881    .R(sinit),
882    .Q(NlwRenamedSig_OI_q[0])
883  );
884  FDRE #(
885    .INIT ( 1'b0 ))
886  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/fd/output_2  (
887    .C(clk),
888    .CE(ce),
889    .D(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/s [1]),
890    .R(sinit),
891    .Q(NlwRenamedSig_OI_q[1])
892  );
893  VCC   \BU2/XST_VCC  (
894    .P(\BU2/thresh0 )
895  );
896  GND   \BU2/XST_GND  (
897    .G(\BU2/N0 )
898  );
899
900// synthesis translate_on
901
902endmodule
903
904// synthesis translate_off
905
906`timescale  1 ps / 1 ps
907
908module glbl ();
909
910    parameter ROC_WIDTH = 100000;
911    parameter TOC_WIDTH = 0;
912
913    wire GSR;
914    wire GTS;
915    wire PRLD;
916
917    reg GSR_int;
918    reg GTS_int;
919    reg PRLD_int;
920
921//--------   JTAG Globals --------------
922    wire JTAG_TDO_GLBL;
923    wire JTAG_TCK_GLBL;
924    wire JTAG_TDI_GLBL;
925    wire JTAG_TMS_GLBL;
926    wire JTAG_TRST_GLBL;
927
928    reg JTAG_CAPTURE_GLBL;
929    reg JTAG_RESET_GLBL;
930    reg JTAG_SHIFT_GLBL;
931    reg JTAG_UPDATE_GLBL;
932
933    reg JTAG_SEL1_GLBL = 0;
934    reg JTAG_SEL2_GLBL = 0 ;
935    reg JTAG_SEL3_GLBL = 0;
936    reg JTAG_SEL4_GLBL = 0;
937
938    reg JTAG_USER_TDO1_GLBL = 1'bz;
939    reg JTAG_USER_TDO2_GLBL = 1'bz;
940    reg JTAG_USER_TDO3_GLBL = 1'bz;
941    reg JTAG_USER_TDO4_GLBL = 1'bz;
942
943    assign (weak1, weak0) GSR = GSR_int;
944    assign (weak1, weak0) GTS = GTS_int;
945    assign (weak1, weak0) PRLD = PRLD_int;
946
947    initial begin
948    GSR_int = 1'b1;
949    PRLD_int = 1'b1;
950    #(ROC_WIDTH)
951    GSR_int = 1'b0;
952    PRLD_int = 1'b0;
953    end
954
955    initial begin
956    GTS_int = 1'b1;
957    #(TOC_WIDTH)
958    GTS_int = 1'b0;
959    end
960
961endmodule
962
963// synthesis translate_on
964////////////////////////////////////////////////////////////////////////////////
965// Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
966////////////////////////////////////////////////////////////////////////////////
967//   ____  ____
968//  /   /\/   /
969// /___/  \  /    Vendor: Xilinx
970// \   \   \/     Version: K.39
971//  \   \         Application: netgen
972//  /   /         Filename: binary_counter_virtex4_10_0_7f29bec8df1c7606.v
973// /___/   /\     Timestamp: Thu Oct 01 13:35:16 2009
974// \   \  /  \
975//  \___\/\___\
976//             
977// Command  : -intstyle ise -w -sim -ofmt verilog .\tmp\_cg\binary_counter_virtex4_10_0_7f29bec8df1c7606.ngc .\tmp\_cg\binary_counter_virtex4_10_0_7f29bec8df1c7606.v
978// Device   : 4vfx12sf363-12
979// Input file   : ./tmp/_cg/binary_counter_virtex4_10_0_7f29bec8df1c7606.ngc
980// Output file  : ./tmp/_cg/binary_counter_virtex4_10_0_7f29bec8df1c7606.v
981// # of Modules : 1
982// Design Name  : binary_counter_virtex4_10_0_7f29bec8df1c7606
983// Xilinx        : c:\xilinx\10.1\ise
984//             
985// Purpose:   
986//     This verilog netlist is a verification model and uses simulation
987//     primitives which may not represent the true implementation of the
988//     device, however the netlist is functionally correct and should not
989//     be modified. This file cannot be synthesized and should only be used
990//     with supported simulation tools.
991//             
992// Reference: 
993//     Development System Reference Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
994//             
995////////////////////////////////////////////////////////////////////////////////
996
997`timescale 1 ns/1 ps
998
999module binary_counter_virtex4_10_0_7f29bec8df1c7606 (
1000  ce, sinit, clk, q
1001);
1002  input ce;
1003  input sinit;
1004  input clk;
1005  output [5 : 0] q;
1006 
1007  // synthesis translate_off
1008 
1009  wire \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop_rt_26 ;
1010  wire \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux_rt_25 ;
1011  wire \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux_rt_23 ;
1012  wire \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux_rt_21 ;
1013  wire \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux_rt_18 ;
1014  wire \BU2/N0 ;
1015  wire \BU2/thresh0 ;
1016  wire NLW_VCC_P_UNCONNECTED;
1017  wire NLW_GND_G_UNCONNECTED;
1018  wire [5 : 0] NlwRenamedSig_OI_q;
1019  wire [0 : 0] \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum ;
1020  wire [4 : 0] \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple ;
1021  wire [5 : 0] \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/s ;
1022  assign
1023    q[5] = NlwRenamedSig_OI_q[5],
1024    q[4] = NlwRenamedSig_OI_q[4],
1025    q[3] = NlwRenamedSig_OI_q[3],
1026    q[2] = NlwRenamedSig_OI_q[2],
1027    q[1] = NlwRenamedSig_OI_q[1],
1028    q[0] = NlwRenamedSig_OI_q[0];
1029  VCC   VCC_0 (
1030    .P(NLW_VCC_P_UNCONNECTED)
1031  );
1032  GND   GND_1 (
1033    .G(NLW_GND_G_UNCONNECTED)
1034  );
1035  INV   \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum_not00001_INV_0  (
1036    .I(NlwRenamedSig_OI_q[0]),
1037    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [0])
1038  );
1039  LUT1 #(
1040    .INIT ( 2'h2 ))
1041  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop_rt  (
1042    .I0(NlwRenamedSig_OI_q[5]),
1043    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop_rt_26 )
1044  );
1045  LUT1 #(
1046    .INIT ( 2'h2 ))
1047  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux_rt  (
1048    .I0(NlwRenamedSig_OI_q[1]),
1049    .O
1050(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux_rt_25 )
1051
1052  );
1053  LUT1 #(
1054    .INIT ( 2'h2 ))
1055  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux_rt  (
1056    .I0(NlwRenamedSig_OI_q[2]),
1057    .O
1058(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux_rt_23 )
1059
1060  );
1061  LUT1 #(
1062    .INIT ( 2'h2 ))
1063  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux_rt  (
1064    .I0(NlwRenamedSig_OI_q[3]),
1065    .O
1066(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux_rt_21 )
1067
1068  );
1069  LUT1 #(
1070    .INIT ( 2'h2 ))
1071  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux_rt  (
1072    .I0(NlwRenamedSig_OI_q[4]),
1073    .O
1074(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux_rt_18 )
1075
1076  );
1077  MUXCY   \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_need_mux.carrymux0  (
1078    .CI(\BU2/N0 ),
1079    .DI(\BU2/thresh0 ),
1080    .S(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [0]),
1081    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [0])
1082  );
1083  XORCY   \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.carryxor0  (
1084    .CI(\BU2/N0 ),
1085    .LI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/halfsum [0]),
1086    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/s [0])
1087  );
1088  XORCY   \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop  (
1089    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [4]),
1090    .LI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carryxortop_rt_26 ),
1091    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/s [5])
1092  );
1093  MUXCY 
1094  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux  (
1095    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [0]),
1096    .DI(\BU2/N0 ),
1097    .S
1098(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux_rt_25 )
1099,
1100    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [1])
1101  );
1102  XORCY 
1103  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carryxor  (
1104    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [0]),
1105    .LI
1106(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[1].carrymux_rt_25 )
1107,
1108    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/s [1])
1109  );
1110  MUXCY 
1111  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux  (
1112    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [1]),
1113    .DI(\BU2/N0 ),
1114    .S
1115(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux_rt_23 )
1116,
1117    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [2])
1118  );
1119  XORCY 
1120  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carryxor  (
1121    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [1]),
1122    .LI
1123(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[2].carrymux_rt_23 )
1124,
1125    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/s [2])
1126  );
1127  MUXCY 
1128  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux  (
1129    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [2]),
1130    .DI(\BU2/N0 ),
1131    .S
1132(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux_rt_21 )
1133,
1134    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [3])
1135  );
1136  XORCY 
1137  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carryxor  (
1138    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [2]),
1139    .LI
1140(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[3].carrymux_rt_21 )
1141,
1142    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/s [3])
1143  );
1144  MUXCY 
1145  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux  (
1146    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [3]),
1147    .DI(\BU2/N0 ),
1148    .S
1149(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux_rt_18 )
1150,
1151    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [4])
1152  );
1153  XORCY 
1154  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carryxor  (
1155    .CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/carry_simple [3]),
1156    .LI
1157(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_simple_model.i_gt_1.carrychaingen[4].carrymux_rt_18 )
1158,
1159    .O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/s [4])
1160  );
1161  FDRE #(
1162    .INIT ( 1'b0 ))
1163  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/fd/output_1  (
1164    .C(clk),
1165    .CE(ce),
1166    .D(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/s [0]),
1167    .R(sinit),
1168    .Q(NlwRenamedSig_OI_q[0])
1169  );
1170  FDRE #(
1171    .INIT ( 1'b0 ))
1172  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/fd/output_2  (
1173    .C(clk),
1174    .CE(ce),
1175    .D(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/s [1]),
1176    .R(sinit),
1177    .Q(NlwRenamedSig_OI_q[1])
1178  );
1179  FDRE #(
1180    .INIT ( 1'b0 ))
1181  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/fd/output_3  (
1182    .C(clk),
1183    .CE(ce),
1184    .D(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/s [2]),
1185    .R(sinit),
1186    .Q(NlwRenamedSig_OI_q[2])
1187  );
1188  FDRE #(
1189    .INIT ( 1'b0 ))
1190  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/fd/output_4  (
1191    .C(clk),
1192    .CE(ce),
1193    .D(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/s [3]),
1194    .R(sinit),
1195    .Q(NlwRenamedSig_OI_q[3])
1196  );
1197  FDRE #(
1198    .INIT ( 1'b0 ))
1199  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/fd/output_5  (
1200    .C(clk),
1201    .CE(ce),
1202    .D(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/s [4]),
1203    .R(sinit),
1204    .Q(NlwRenamedSig_OI_q[4])
1205  );
1206  FDRE #(
1207    .INIT ( 1'b0 ))
1208  \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut4.i_lut4_addsub/i_q.i_simple.qreg/fd/output_6  (
1209    .C(clk),
1210    .CE(ce),
1211    .D(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/s [5]),
1212    .R(sinit),
1213    .Q(NlwRenamedSig_OI_q[5])
1214  );
1215  VCC   \BU2/XST_VCC  (
1216    .P(\BU2/thresh0 )
1217  );
1218  GND   \BU2/XST_GND  (
1219    .G(\BU2/N0 )
1220  );
1221
1222// synthesis translate_on
1223
1224endmodule
1225
1226// synthesis translate_off
1227
1228`timescale  1 ps / 1 ps
1229
1230module glbl ();
1231
1232    parameter ROC_WIDTH = 100000;
1233    parameter TOC_WIDTH = 0;
1234
1235    wire GSR;
1236    wire GTS;
1237    wire PRLD;
1238
1239    reg GSR_int;
1240    reg GTS_int;
1241    reg PRLD_int;
1242
1243//--------   JTAG Globals --------------
1244    wire JTAG_TDO_GLBL;
1245    wire JTAG_TCK_GLBL;
1246    wire JTAG_TDI_GLBL;
1247    wire JTAG_TMS_GLBL;
1248    wire JTAG_TRST_GLBL;
1249
1250    reg JTAG_CAPTURE_GLBL;
1251    reg JTAG_RESET_GLBL;
1252    reg JTAG_SHIFT_GLBL;
1253    reg JTAG_UPDATE_GLBL;
1254
1255    reg JTAG_SEL1_GLBL = 0;
1256    reg JTAG_SEL2_GLBL = 0 ;
1257    reg JTAG_SEL3_GLBL = 0;
1258    reg JTAG_SEL4_GLBL = 0;
1259
1260    reg JTAG_USER_TDO1_GLBL = 1'bz;
1261    reg JTAG_USER_TDO2_GLBL = 1'bz;
1262    reg JTAG_USER_TDO3_GLBL = 1'bz;
1263    reg JTAG_USER_TDO4_GLBL = 1'bz;
1264
1265    assign (weak1, weak0) GSR = GSR_int;
1266    assign (weak1, weak0) GTS = GTS_int;
1267    assign (weak1, weak0) PRLD = PRLD_int;
1268
1269    initial begin
1270    GSR_int = 1'b1;
1271    PRLD_int = 1'b1;
1272    #(ROC_WIDTH)
1273    GSR_int = 1'b0;
1274    PRLD_int = 1'b0;
1275    end
1276
1277    initial begin
1278    GTS_int = 1'b1;
1279    #(TOC_WIDTH)
1280    GTS_int = 1'b0;
1281    end
1282
1283endmodule
1284
1285// synthesis translate_on
1286/*******************************************************************************
1287*     This file is owned and controlled by Xilinx and must be used             *
1288*     solely for design, simulation, implementation and creation of            *
1289*     design files limited to Xilinx devices or technologies. Use              *
1290*     with non-Xilinx devices or technologies is expressly prohibited          *
1291*     and immediately terminates your license.                                 *
1292*                                                                              *
1293*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
1294*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
1295*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
1296*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
1297*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
1298*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
1299*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
1300*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
1301*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
1302*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
1303*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
1304*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
1305*     FOR A PARTICULAR PURPOSE.                                                *
1306*                                                                              *
1307*     Xilinx products are not intended for use in life support                 *
1308*     appliances, devices, or systems. Use in such applications are            *
1309*     expressly prohibited.                                                    *
1310*                                                                              *
1311*     (c) Copyright 1995-2007 Xilinx, Inc.                                     *
1312*     All rights reserved.                                                     *
1313*******************************************************************************/
1314// The synthesis directives "translate_off/translate_on" specified below are
1315// supported by Xilinx, Mentor Graphics and Synplicity synthesis
1316// tools. Ensure they are correct for your synthesis tool(s).
1317
1318// You must compile the wrapper file dmg_33_vx4_dcb0c4b6adf24a19.v when simulating
1319// the core, dmg_33_vx4_dcb0c4b6adf24a19. When compiling the wrapper file, be sure to
1320// reference the XilinxCoreLib Verilog simulation library. For detailed
1321// instructions, please refer to the "CORE Generator Help".
1322
1323`timescale 1ns/1ps
1324
1325module dmg_33_vx4_dcb0c4b6adf24a19(
1326    a,
1327    d,
1328    dpra,
1329    clk,
1330    we,
1331    spo,
1332    dpo);
1333
1334
1335input [5 : 0] a;
1336input [0 : 0] d;
1337input [5 : 0] dpra;
1338input clk;
1339input we;
1340output [0 : 0] spo;
1341output [0 : 0] dpo;
1342
1343// synthesis translate_off
1344
1345      DIST_MEM_GEN_V3_3 #(
1346        .C_ADDR_WIDTH(6),
1347        .C_DEFAULT_DATA("0"),
1348        .C_DEPTH(64),
1349        .C_HAS_CLK(1),
1350        .C_HAS_D(1),
1351        .C_HAS_DPO(1),
1352        .C_HAS_DPRA(1),
1353        .C_HAS_I_CE(0),
1354        .C_HAS_QDPO(0),
1355        .C_HAS_QDPO_CE(0),
1356        .C_HAS_QDPO_CLK(0),
1357        .C_HAS_QDPO_RST(0),
1358        .C_HAS_QDPO_SRST(0),
1359        .C_HAS_QSPO(0),
1360        .C_HAS_QSPO_CE(0),
1361        .C_HAS_QSPO_RST(0),
1362        .C_HAS_QSPO_SRST(0),
1363        .C_HAS_SPO(1),
1364        .C_HAS_SPRA(0),
1365        .C_HAS_WE(1),
1366        .C_MEM_INIT_FILE("dmg_33_vx4_dcb0c4b6adf24a19.mif"),
1367        .C_MEM_TYPE(2),
1368        .C_PIPELINE_STAGES(0),
1369        .C_QCE_JOINED(0),
1370        .C_QUALIFY_WE(0),
1371        .C_READ_MIF(1),
1372        .C_REG_A_D_INPUTS(0),
1373        .C_REG_DPRA_INPUT(0),
1374        .C_SYNC_ENABLE(1),
1375        .C_WIDTH(1))
1376    inst (
1377        .A(a),
1378        .D(d),
1379        .DPRA(dpra),
1380        .CLK(clk),
1381        .WE(we),
1382        .SPO(spo),
1383        .DPO(dpo),
1384        .SPRA(),
1385        .I_CE(),
1386        .QSPO_CE(),
1387        .QDPO_CE(),
1388        .QDPO_CLK(),
1389        .QSPO_RST(),
1390        .QDPO_RST(),
1391        .QSPO_SRST(),
1392        .QDPO_SRST(),
1393        .QSPO(),
1394        .QDPO());
1395
1396
1397// synthesis translate_on
1398
1399endmodule
1400
1401
1402//-----------------------------------------------------------------
1403// System Generator version 10.1.3 VERILOG source file.
1404//
1405// Copyright(C) 2008 by Xilinx, Inc.  All rights reserved.  This
1406// text/file contains proprietary, confidential information of Xilinx,
1407// Inc., is distributed under license from Xilinx, Inc., and may be used,
1408// copied and/or disclosed only pursuant to the terms of a valid license
1409// agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
1410// this text/file solely for design, simulation, implementation and
1411// creation of design files limited to Xilinx devices or technologies.
1412// Use with non-Xilinx devices or technologies is expressly prohibited
1413// and immediately terminates your license unless covered by a separate
1414// agreement.
1415//
1416// Xilinx is providing this design, code, or information "as is" solely
1417// for use in developing programs and solutions for Xilinx devices.  By
1418// providing this design, code, or information as one possible
1419// implementation of this feature, application or standard, Xilinx is
1420// making no representation that this implementation is free from any
1421// claims of infringement.  You are responsible for obtaining any rights
1422// you may require for your implementation.  Xilinx expressly disclaims
1423// any warranty whatsoever with respect to the adequacy of the
1424// implementation, including but not limited to warranties of
1425// merchantability or fitness for a particular purpose.
1426//
1427// Xilinx products are not intended for use in life support appliances,
1428// devices, or systems.  Use in such applications is expressly prohibited.
1429//
1430// Any modifications that are made to the source code are done at the user's
1431// sole risk and will be unsupported.
1432//
1433// This copyright and support notice must be retained as part of this
1434// text at all times.  (c) Copyright 1995-2008 Xilinx, Inc.  All rights
1435// reserved.
1436//-----------------------------------------------------------------
1437// synopsys translate_off
1438`ifndef simulating
1439  `define simulating 1
1440`endif
1441// synopsys translate_on
1442`ifndef simulating
1443  `define simulating 0
1444`endif
1445`ifndef xlUnsigned
1446 `define xlUnsigned 1
1447`endif
1448`ifndef xlSigned
1449 `define xlSigned 2
1450`endif
1451`ifndef xlWrap
1452 `define xlWrap 1
1453`endif
1454`ifndef xlSaturate
1455 `define xlSaturate 2
1456`endif
1457`ifndef xlTruncate
1458 `define xlTruncate 1
1459`endif
1460`ifndef xlRound
1461 `define xlRound 2
1462`endif
1463`ifndef xlRoundBanker
1464 `define xlRoundBanker 3
1465`endif
1466`ifndef xlAddMode
1467 `define xlAddMode 1
1468`endif
1469`ifndef xlSubMode
1470 `define xlSubMode 2
1471`endif
1472
1473//-----------------------------------------------------------------
1474// System Generator version 10.1.3 VERILOG source file.
1475//
1476// Copyright(C) 2008 by Xilinx, Inc.  All rights reserved.  This
1477// text/file contains proprietary, confidential information of Xilinx,
1478// Inc., is distributed under license from Xilinx, Inc., and may be used,
1479// copied and/or disclosed only pursuant to the terms of a valid license
1480// agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
1481// this text/file solely for design, simulation, implementation and
1482// creation of design files limited to Xilinx devices or technologies.
1483// Use with non-Xilinx devices or technologies is expressly prohibited
1484// and immediately terminates your license unless covered by a separate
1485// agreement.
1486//
1487// Xilinx is providing this design, code, or information "as is" solely
1488// for use in developing programs and solutions for Xilinx devices.  By
1489// providing this design, code, or information as one possible
1490// implementation of this feature, application or standard, Xilinx is
1491// making no representation that this implementation is free from any
1492// claims of infringement.  You are responsible for obtaining any rights
1493// you may require for your implementation.  Xilinx expressly disclaims
1494// any warranty whatsoever with respect to the adequacy of the
1495// implementation, including but not limited to warranties of
1496// merchantability or fitness for a particular purpose.
1497//
1498// Xilinx products are not intended for use in life support appliances,
1499// devices, or systems.  Use in such applications is expressly prohibited.
1500//
1501// Any modifications that are made to the source code are done at the user's
1502// sole risk and will be unsupported.
1503//
1504// This copyright and support notice must be retained as part of this
1505// text at all times.  (c) Copyright 1995-2008 Xilinx, Inc.  All rights
1506// reserved.
1507//-----------------------------------------------------------------
1508`timescale 1 ns / 10 ps
1509module srl17e (clk, ce, d, q);
1510    parameter width = 16;
1511    parameter latency = 8;
1512    input clk, ce;
1513    input [width-1:0] d;
1514    output [width-1:0] q;
1515    parameter signed [5:0] a = latency - 2;
1516    wire[width - 1:0] #0.2 d_delayed;
1517    wire[width - 1:0] srl16_out;
1518    genvar i;
1519    assign d_delayed = d ;
1520    generate
1521      for(i=0; i<width; i=i+1)
1522      begin:reg_array
1523            if (latency > 1)
1524                begin: has_2_latency
1525                 SRL16E u1 (.CLK(clk), .D(d_delayed[i]), .Q(srl16_out[i]), .CE(ce), .A0(a[0]), .A1(a[1]), .A2(a[2]), .A3(a[3]));
1526                end
1527            if (latency <= 1)
1528                begin: has_1_latency
1529                 assign srl16_out[i] = d_delayed[i];
1530                end
1531            if (latency != 0)
1532                begin: has_latency
1533                 FDE u2 (.C(clk), .D(srl16_out[i]), .Q(q[i]), .CE(ce));
1534                end
1535            if (latency == 0)
1536                begin:has_0_latency
1537                 assign q[i] = srl16_out[i];
1538                end
1539        end
1540    endgenerate
1541endmodule
1542module synth_reg (i, ce, clr, clk, o);
1543   parameter width  = 8;
1544   parameter latency  = 1;
1545   input[width - 1:0] i;
1546   input ce,clr,clk;
1547   output[width - 1:0] o;
1548   parameter complete_num_srl17es = latency/17;
1549   parameter remaining_latency = latency%17;
1550   parameter temp_num_srl17es = (latency/17) + ((latency%17)?1:0);
1551   parameter num_srl17es = temp_num_srl17es ? temp_num_srl17es : 1;
1552   wire [width - 1:0] z [0:num_srl17es-1];
1553   genvar t;
1554    generate
1555      if (latency <= 17)
1556          begin:has_only_1
1557              srl17e #(width, latency) srl17e_array0(.clk(clk), .ce(ce), .d(i), .q(o));
1558          end
1559     endgenerate
1560    generate
1561     if (latency > 17)
1562        begin:has_1
1563             assign o = z[num_srl17es-1];
1564             srl17e #(width, 17) srl17e_array0(.clk(clk), .ce(ce), .d(i), .q(z[0]));
1565        end
1566   endgenerate
1567   generate
1568      if (latency > 17)
1569          begin:more_than_1
1570              for (t=1; t < complete_num_srl17es; t=t+1)
1571                begin:left_complete_ones
1572                   srl17e #(width, 17) srl17e_array(.clk(clk), .ce(ce), .d(z[t-1]), .q(z[t]));
1573                end
1574          end
1575   endgenerate
1576   generate
1577     if ((remaining_latency > 0) && (latency>17))
1578          begin:remaining_ones
1579             srl17e #(width, (latency%17)) last_srl17e (.clk(clk), .ce(ce), .d(z[num_srl17es-2]), .q(z[num_srl17es-1]));
1580          end
1581   endgenerate
1582endmodule
1583module synth_reg_reg (i, ce, clr, clk, o);
1584   parameter width  = 8;
1585   parameter latency  = 1;
1586   input[width - 1:0] i;
1587   input ce, clr, clk;
1588   output[width - 1:0] o;
1589   wire[width - 1:0] o;
1590   genvar idx;
1591   reg[width - 1:0] reg_bank [latency:0];
1592   integer j;
1593   initial
1594     begin
1595        for (j=0; j < latency+1; j=j+1)
1596          begin
1597             reg_bank[j] = {width{1'b0}};
1598          end
1599     end
1600
1601   generate
1602     if (latency == 0)
1603        begin:has_0_latency
1604         assign o = i;
1605       end
1606   endgenerate
1607
1608   always @(i)
1609        begin
1610             reg_bank[0] = i;
1611         end
1612   generate
1613     if (latency > 0)
1614        begin:more_than_1
1615            assign o = reg_bank[latency];
1616         for (idx=0; idx < latency; idx=idx+1) begin:sync_loop
1617            always @(posedge clk)
1618                  begin
1619                  if (ce)
1620                    begin
1621                        reg_bank[idx+1] <= reg_bank[idx] ;
1622                    end
1623               end
1624        end
1625      end
1626   endgenerate
1627endmodule
1628
1629//-----------------------------------------------------------------
1630// System Generator version 10.1.3 VERILOG source file.
1631//
1632// Copyright(C) 2008 by Xilinx, Inc.  All rights reserved.  This
1633// text/file contains proprietary, confidential information of Xilinx,
1634// Inc., is distributed under license from Xilinx, Inc., and may be used,
1635// copied and/or disclosed only pursuant to the terms of a valid license
1636// agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
1637// this text/file solely for design, simulation, implementation and
1638// creation of design files limited to Xilinx devices or technologies.
1639// Use with non-Xilinx devices or technologies is expressly prohibited
1640// and immediately terminates your license unless covered by a separate
1641// agreement.
1642//
1643// Xilinx is providing this design, code, or information "as is" solely
1644// for use in developing programs and solutions for Xilinx devices.  By
1645// providing this design, code, or information as one possible
1646// implementation of this feature, application or standard, Xilinx is
1647// making no representation that this implementation is free from any
1648// claims of infringement.  You are responsible for obtaining any rights
1649// you may require for your implementation.  Xilinx expressly disclaims
1650// any warranty whatsoever with respect to the adequacy of the
1651// implementation, including but not limited to warranties of
1652// merchantability or fitness for a particular purpose.
1653//
1654// Xilinx products are not intended for use in life support appliances,
1655// devices, or systems.  Use in such applications is expressly prohibited.
1656//
1657// Any modifications that are made to the source code are done at the user's
1658// sole risk and will be unsupported.
1659//
1660// This copyright and support notice must be retained as part of this
1661// text at all times.  (c) Copyright 1995-2008 Xilinx, Inc.  All rights
1662// reserved.
1663//-----------------------------------------------------------------
1664`timescale 1 ns / 10 ps
1665module synth_reg_w_init (i, ce, clr, clk, o);
1666   parameter width  = 8;
1667   parameter init_index  = 0;
1668   parameter [width-1 : 0] init_value  = 'b0000;
1669   parameter latency  = 1;
1670
1671   input[width - 1:0] i;
1672   input ce, clr, clk;
1673   output[width - 1:0] o;
1674   wire[(latency + 1) * width - 1:0] dly_i;
1675   wire #0.2 dly_clr;
1676   genvar index;
1677
1678   generate
1679     if (latency == 0)
1680        begin:has_0_latency
1681         assign o = i;
1682        end
1683     else
1684        begin:has_latency
1685         assign dly_i[(latency + 1) * width - 1:latency * width] = i ;
1686         assign dly_clr = clr ;
1687         for (index=1; index<=latency; index=index+1)
1688           begin:fd_array
1689// synopsys translate_off
1690             defparam reg_comp_1.width = width;
1691             defparam reg_comp_1.init_index = init_index;
1692             defparam reg_comp_1.init_value = init_value;
1693// synopsys translate_on
1694             single_reg_w_init #(width, init_index, init_value)
1695               reg_comp_1(.clk(clk),
1696                          .i(dly_i[(index + 1)*width-1:index*width]),
1697                          .o(dly_i[index * width - 1:(index - 1) * width]),
1698                          .ce(ce),
1699                          .clr(dly_clr));
1700             end
1701        assign o = dly_i[width-1:0];
1702       end
1703   endgenerate
1704endmodule
1705module single_reg_w_init (i, ce, clr, clk, o);
1706   parameter width  = 8;
1707   parameter init_index  = 0;
1708   parameter [width-1 : 0] init_value  = 8'b00000000;
1709   input[width - 1:0] i;
1710   input ce;
1711   input clr;
1712   input clk;
1713   output[width - 1:0] o;
1714   parameter [0:0] init_index_val = (init_index ==  1) ? 1'b1 : 1'b0;
1715   parameter [width-1:0] result = (width > 1) ? { {(width-1){1'b0}}, init_index_val } : init_index_val;
1716   parameter [width-1:0] init_const = (init_index > 1) ? init_value : result;
1717   wire[width - 1:0] o;
1718   genvar index;
1719
1720   generate
1721     for (index=0;index < width; index=index+1) begin:fd_prim_array
1722          if (init_const[index] == 0)
1723            begin:rst_comp
1724              FDRE fdre_comp(.C(clk),
1725                             .D(i[index]),
1726                             .Q(o[index]),
1727                             .CE(ce),
1728                             .R(clr));
1729            end
1730          else
1731            begin:set_comp
1732             FDSE fdse_comp(.C(clk),
1733                            .D(i[index]),
1734                            .Q(o[index]),
1735                            .CE(ce),
1736                            .S(clr));
1737            end
1738    end
1739   endgenerate
1740endmodule
1741
1742//-----------------------------------------------------------------
1743// System Generator version 10.1.3 VERILOG source file.
1744//
1745// Copyright(C) 2008 by Xilinx, Inc.  All rights reserved.  This
1746// text/file contains proprietary, confidential information of Xilinx,
1747// Inc., is distributed under license from Xilinx, Inc., and may be used,
1748// copied and/or disclosed only pursuant to the terms of a valid license
1749// agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
1750// this text/file solely for design, simulation, implementation and
1751// creation of design files limited to Xilinx devices or technologies.
1752// Use with non-Xilinx devices or technologies is expressly prohibited
1753// and immediately terminates your license unless covered by a separate
1754// agreement.
1755//
1756// Xilinx is providing this design, code, or information "as is" solely
1757// for use in developing programs and solutions for Xilinx devices.  By
1758// providing this design, code, or information as one possible
1759// implementation of this feature, application or standard, Xilinx is
1760// making no representation that this implementation is free from any
1761// claims of infringement.  You are responsible for obtaining any rights
1762// you may require for your implementation.  Xilinx expressly disclaims
1763// any warranty whatsoever with respect to the adequacy of the
1764// implementation, including but not limited to warranties of
1765// merchantability or fitness for a particular purpose.
1766//
1767// Xilinx products are not intended for use in life support appliances,
1768// devices, or systems.  Use in such applications is expressly prohibited.
1769//
1770// Any modifications that are made to the source code are done at the user's
1771// sole risk and will be unsupported.
1772//
1773// This copyright and support notice must be retained as part of this
1774// text at all times.  (c) Copyright 1995-2008 Xilinx, Inc.  All rights
1775// reserved.
1776//-----------------------------------------------------------------
1777`ifndef xlConvertType
1778 `define xlConvertType
1779 `timescale 1 ns / 10 ps
1780module cast (inp, res);
1781    parameter signed [31:0] old_width = 4;
1782    parameter signed [31:0] old_bin_pt = 1;
1783    parameter signed [31:0] new_width = 4;
1784    parameter signed [31:0] new_bin_pt = 1;
1785    parameter signed [31:0] new_arith = `xlSigned;
1786    input [old_width - 1 : 0] inp;
1787    output [new_width - 1 : 0] res;
1788
1789   parameter signed [31:0] right_of_dp = new_bin_pt - old_bin_pt;
1790    wire [new_width-1:0] result;
1791   genvar i;
1792   assign res = result;
1793   generate
1794      for (i = 0; i<new_width;  i = i+1)
1795        begin:cast_loop
1796           if ((i-right_of_dp) > old_width - 1)
1797             begin:u0
1798                if (new_arith == `xlUnsigned)
1799                  begin:u1
1800                     assign result[i] = 1'b0;
1801                  end
1802                if (new_arith == `xlSigned)
1803                  begin:u2
1804                     assign result[i] = inp[old_width-1];
1805                  end
1806             end
1807           else if ((i-right_of_dp) >= 0)
1808             begin:u3
1809                assign result[i] = inp[i-right_of_dp];
1810             end
1811           else
1812             begin:u4
1813                assign result[i] = 1'b0;
1814             end
1815        end
1816      endgenerate
1817
1818endmodule
1819module pad_lsb (inp, res);
1820   parameter signed [31:0] orig_width = 4;
1821   parameter signed [31:0] new_width = 2;
1822   input [orig_width - 1 : 0] inp;
1823   output [new_width - 1 : 0] res;
1824   parameter signed [31:0] pad_pos = new_width - orig_width -1;
1825   wire [new_width-1:0] result;
1826   genvar i;
1827   assign  res = result;
1828   generate
1829      if (new_width >= orig_width)
1830        begin:u0
1831           assign result[new_width-1:new_width-orig_width] = inp[orig_width-1:0];
1832        end
1833   endgenerate
1834
1835   generate
1836      if (pad_pos >= 0)
1837        begin:u1
1838           assign result[pad_pos:0] = {pad_pos{1'b0}};
1839        end
1840   endgenerate
1841endmodule
1842module zero_ext (inp, res);
1843   parameter signed [31:0]  old_width = 4;
1844   parameter signed [31:0]  new_width = 2;
1845   input [old_width - 1 : 0] inp;
1846   output [new_width - 1 : 0] res;
1847   wire [new_width-1:0] result;
1848   genvar i;
1849   assign res = result;
1850   generate
1851     if (new_width >= old_width)
1852       begin:u0
1853          assign result = { {(new_width-old_width){1'b0}}, inp};
1854       end
1855     else
1856       begin:u1
1857          assign result[new_width-1:0] = inp[new_width-1:0];
1858       end
1859    endgenerate
1860endmodule
1861module sign_ext (inp, res);
1862   parameter signed [31:0]  old_width = 4;
1863   parameter signed [31:0]  new_width = 2;
1864   input [old_width - 1 : 0] inp;
1865   output [new_width - 1 : 0] res;
1866   wire [new_width-1:0] result;
1867   assign res = result;
1868   generate
1869     if (new_width >= old_width)
1870       begin:u0
1871          assign result = { {(new_width-old_width){inp[old_width-1]}}, inp};
1872       end
1873     else
1874       begin:u1
1875          assign result[new_width-1:0] = inp[new_width-1:0];
1876       end
1877   endgenerate
1878
1879endmodule
1880module extend_msb (inp, res);
1881    parameter signed [31:0]  old_width = 4;
1882    parameter signed [31:0]  new_width = 4;
1883    parameter signed [31:0]  new_arith = `xlSigned;
1884    input [old_width - 1 : 0] inp;
1885    output [new_width - 1 : 0] res;
1886    wire [new_width-1:0] result;
1887   assign res = result;
1888   generate
1889      if (new_arith ==`xlUnsigned)
1890        begin:u0
1891           zero_ext # (old_width, new_width)
1892             em_zero_ext (.inp(inp), .res(result));
1893        end
1894      else
1895        begin:u1
1896           sign_ext # (old_width, new_width)
1897             em_sign_ext (.inp(inp), .res(result));
1898        end
1899    endgenerate
1900endmodule
1901module align_input (inp, res);
1902    parameter signed [31:0]  old_width = 4;
1903    parameter signed [31:0]  delta = 1;
1904    parameter signed [31:0]  new_arith = `xlSigned;
1905    parameter signed [31:0]  new_width = 4;
1906    input [old_width - 1 : 0] inp;
1907    output [new_width - 1 : 0] res;
1908    parameter signed [31:0]  abs_delta = (delta >= 0) ? (delta) : (-delta);
1909    wire [new_width-1:0] result;
1910    wire [(old_width+abs_delta)-1:0] padded_inp;
1911   assign res = result;
1912   generate
1913      if (delta > 0)
1914        begin:u0
1915           pad_lsb # (old_width, old_width+delta)
1916             ai_pad_lsb (.inp(inp), .res(padded_inp));
1917           extend_msb # (old_width+delta, new_width, new_arith)
1918             ai_extend_msb (.inp(padded_inp), .res(result));
1919        end
1920      else
1921        begin:u1
1922           extend_msb # (old_width, new_width, new_arith)
1923             ai_extend_msb (.inp(inp), .res(result));
1924        end
1925   endgenerate
1926endmodule
1927module round_towards_inf (inp, res);
1928    parameter signed [31:0]  old_width = 4;
1929    parameter signed [31:0]  old_bin_pt = 2;
1930    parameter signed [31:0]  old_arith = `xlSigned;
1931    parameter signed [31:0]  new_width = 4;
1932    parameter signed [31:0]  new_bin_pt = 1;
1933    parameter signed [31:0]  new_arith = `xlSigned;
1934    input [old_width - 1 : 0] inp;
1935    output [new_width - 1 : 0] res;
1936
1937   parameter signed [31:0]  right_of_dp = old_bin_pt - new_bin_pt;
1938   parameter signed [31:0]  abs_right_of_dp = (new_bin_pt > old_bin_pt) ? (new_bin_pt-old_bin_pt) : (old_bin_pt - new_bin_pt);
1939   parameter signed [31:0]  right_of_dp_2 = (right_of_dp >=2) ? right_of_dp-2 : 0;
1940   parameter signed [31:0]  right_of_dp_1 = (right_of_dp >=1) ? right_of_dp-1 : 0;
1941   reg [new_width-1:0] one_or_zero;
1942   wire [new_width-1:0] truncated_val;
1943   wire signed [new_width-1:0] result_signed;
1944   wire [abs_right_of_dp+old_width-1 : 0] padded_val;
1945   initial
1946     begin
1947        one_or_zero = {new_width{1'b0}};
1948     end
1949   generate
1950      if (right_of_dp >= 0)
1951        begin:u0
1952           if (new_arith ==`xlUnsigned)
1953             begin:u1
1954                zero_ext # (old_width-right_of_dp, new_width)
1955                  rti_zero_ext (.inp(inp[old_width-1:right_of_dp]), .res(truncated_val));
1956             end
1957           else
1958             begin:u2
1959                sign_ext # (old_width-right_of_dp, new_width)
1960                  rti_sign_ext (.inp(inp[old_width-1:right_of_dp]), .res(truncated_val));
1961             end
1962        end
1963      else
1964        begin:u3
1965           pad_lsb # (old_width, abs_right_of_dp+old_width)
1966             rti_pad_lsb (.inp(inp), .res(padded_val));
1967           if (new_arith ==`xlUnsigned)
1968             begin:u4
1969                zero_ext # (abs_right_of_dp+old_width, new_width)
1970                  rti_zero_ext1 (.inp(padded_val), .res(truncated_val));
1971             end
1972           else
1973             begin:u5
1974                sign_ext # (abs_right_of_dp+old_width, new_width)
1975                  rti_sign_ext1 (.inp(padded_val), .res(truncated_val));
1976             end
1977        end
1978   endgenerate
1979   generate
1980      if (new_arith == `xlSigned)
1981        begin:u6
1982           always @(inp)
1983             begin
1984                one_or_zero = {new_width{1'b0}};
1985               if (inp[old_width-1] == 1'b0)
1986                 begin
1987                    one_or_zero[0] = 1'b1;
1988                 end
1989               if ((right_of_dp >=2) && (right_of_dp <= old_width))
1990                 begin
1991                    if(|inp[right_of_dp_2:0] == 1'b1)
1992                       begin
1993                          one_or_zero[0] = 1'b1;
1994                       end
1995                 end
1996               if ((right_of_dp >=1) && (right_of_dp <= old_width))
1997                 begin
1998                    if(inp[right_of_dp_1] == 1'b0)
1999                      begin
2000                         one_or_zero[0] = 1'b0;
2001                      end
2002                 end
2003               else
2004                 begin
2005                    one_or_zero[0] = 1'b0;
2006                 end
2007             end
2008             assign result_signed = truncated_val + one_or_zero;
2009             assign res = result_signed;
2010        end
2011
2012      else
2013        begin:u7
2014           always @(inp)
2015             begin
2016                one_or_zero = {new_width{1'b0}};
2017               if ((right_of_dp >=1) && (right_of_dp <= old_width))
2018                 begin
2019                    one_or_zero[0] = inp[right_of_dp_1];
2020                 end
2021             end
2022             assign res = truncated_val + one_or_zero;
2023        end
2024   endgenerate
2025
2026endmodule
2027module round_towards_even (inp, res);
2028    parameter signed [31:0]  old_width = 4;
2029    parameter signed [31:0]  old_bin_pt = 2;
2030    parameter signed [31:0]  old_arith = `xlSigned;
2031    parameter signed [31:0]  new_width = 4;
2032    parameter signed [31:0]  new_bin_pt = 1;
2033    parameter signed [31:0]  new_arith = `xlSigned;
2034    input [old_width - 1 : 0] inp;
2035    output [new_width - 1 : 0] res;
2036   parameter signed [31:0]  right_of_dp = old_bin_pt - new_bin_pt;
2037   parameter signed [31:0]  abs_right_of_dp = (new_bin_pt > old_bin_pt) ? (new_bin_pt-old_bin_pt) : (old_bin_pt - new_bin_pt);
2038   parameter signed [31:0]  expected_new_width = old_width - right_of_dp + 1;
2039   reg [new_width-1:0] one_or_zero;
2040   wire signed [new_width-1:0] result_signed;
2041   wire [new_width-1:0] truncated_val;
2042   wire [abs_right_of_dp+old_width-1 : 0] padded_val;
2043   initial
2044     begin
2045      one_or_zero = { new_width{1'b0}};
2046     end
2047
2048   generate
2049      if (right_of_dp >= 0)
2050        begin:u0
2051           if (new_arith == `xlUnsigned)
2052             begin:u1
2053                zero_ext # (old_width-right_of_dp, new_width)
2054                            rte_zero_ext (.inp(inp[old_width-1:right_of_dp]), .res(truncated_val));
2055             end
2056           else
2057             begin:u2
2058                sign_ext # (old_width-right_of_dp, new_width)
2059                            rte_sign_ext (.inp(inp[old_width-1:right_of_dp]), .res(truncated_val));
2060             end
2061        end
2062
2063      else
2064        begin:u3
2065           pad_lsb # (old_width, abs_right_of_dp+old_width)
2066                            rte_pad_lsb (.inp(inp), .res(padded_val));
2067           if (new_arith == `xlUnsigned)
2068             begin:u4
2069                zero_ext # (abs_right_of_dp+old_width, new_width)
2070                            rte_zero_ext1 (.inp(padded_val), .res(truncated_val));
2071             end
2072           else
2073             begin:u5
2074                sign_ext # (abs_right_of_dp+old_width, new_width)
2075                            rte_sign_ext1 (.inp(padded_val), .res(truncated_val));
2076             end
2077        end
2078   endgenerate
2079
2080   generate
2081      if ((right_of_dp ==1) && (right_of_dp <= old_width))
2082        begin:u6a
2083           always @(inp)
2084             begin
2085                one_or_zero = { new_width{1'b0}};
2086                if(inp[right_of_dp-1] == 1'b1)
2087                  begin
2088                     one_or_zero[0] = inp[right_of_dp];
2089                  end
2090                else
2091                  begin
2092                     one_or_zero[0] = inp[right_of_dp-1];
2093                  end
2094             end
2095       end
2096      else if ((right_of_dp >=2) && (right_of_dp <= old_width))
2097        begin:u6b
2098           always @(inp)
2099             begin
2100                one_or_zero = { new_width{1'b0}};
2101                if( (inp[right_of_dp-1] == 'b1) && !(|inp[right_of_dp-2:0]) )
2102                  begin
2103                     one_or_zero[0] = inp[right_of_dp];
2104                  end
2105                else
2106                  begin
2107                     one_or_zero[0] = inp[right_of_dp-1];
2108                  end
2109             end
2110       end
2111      else
2112        begin:u7
2113            always @(inp)
2114             begin
2115                one_or_zero = { new_width{1'b0}};
2116             end
2117        end
2118   endgenerate
2119
2120   generate
2121      if (new_arith == `xlSigned)
2122        begin:u8
2123           assign result_signed = truncated_val + one_or_zero;
2124           assign res = result_signed;
2125        end
2126      else
2127        begin:u9
2128           assign res = truncated_val + one_or_zero;
2129        end
2130   endgenerate
2131
2132endmodule
2133module trunc (inp, res);
2134    parameter signed [31:0]  old_width = 4;
2135    parameter signed [31:0]  old_bin_pt = 2;
2136    parameter signed [31:0]  old_arith = `xlSigned;
2137    parameter signed [31:0]  new_width = 4;
2138    parameter signed [31:0]  new_bin_pt = 1;
2139    parameter signed [31:0]  new_arith = `xlSigned;
2140    input [old_width - 1 : 0] inp;
2141    output [new_width - 1 : 0] res;
2142
2143   parameter signed [31:0]  right_of_dp = old_bin_pt - new_bin_pt;
2144   parameter signed [31:0]  abs_right_of_dp = (new_bin_pt > old_bin_pt) ? (new_bin_pt-old_bin_pt) : (old_bin_pt - new_bin_pt);
2145   wire [new_width-1:0] result;
2146   wire [abs_right_of_dp+old_width-1 : 0] padded_val;
2147   assign res = result;
2148   generate
2149      if (new_bin_pt > old_bin_pt)
2150        begin:tr_u2
2151           pad_lsb # (old_width, abs_right_of_dp+old_width)
2152             tr_pad_lsb (.inp(inp), .res(padded_val));
2153           extend_msb # (old_width+abs_right_of_dp, new_width, new_arith)
2154             tr_extend_msb (.inp(padded_val), .res(result));
2155        end
2156      else
2157        begin:tr_u1
2158           extend_msb # (old_width-right_of_dp, new_width, new_arith)
2159             tr_extend_msb (.inp(inp[old_width-1:right_of_dp]), .res(result));
2160        end
2161   endgenerate
2162
2163endmodule
2164module saturation_arith (inp, res);
2165    parameter signed [31:0]  old_width = 4;
2166    parameter signed [31:0]  old_bin_pt = 2;
2167    parameter signed [31:0]  old_arith = `xlSigned;
2168    parameter signed [31:0]  new_width = 4;
2169    parameter signed [31:0]  new_bin_pt = 1;
2170    parameter signed [31:0]  new_arith = `xlSigned;
2171    input [old_width - 1 : 0] inp;
2172    output [new_width - 1 : 0] res;
2173   parameter signed [31:0]  abs_right_of_dp = (new_bin_pt > old_bin_pt) ? (new_bin_pt-old_bin_pt) : (old_bin_pt - new_bin_pt);
2174   parameter signed [31:0]  abs_width = (new_width > old_width) ? (new_width-old_width) : 1;
2175   parameter signed [31:0]  abs_new_width = (old_width > new_width) ? new_width : 1;
2176   reg overflow;
2177   reg [old_width-1:0] vec;
2178   reg [new_width-1:0] result;
2179   assign res = result;
2180   generate
2181      if (old_width > new_width)
2182        begin:sa_u0
2183           always @ (inp)
2184             begin
2185                vec = inp;
2186                overflow = 1;
2187                if ( (old_arith == `xlSigned) && (new_arith == `xlSigned) )
2188                  begin
2189                    if (~|inp[old_width-1:abs_new_width-1] || &inp[old_width-1:abs_new_width-1])
2190                     begin
2191                       overflow = 0;
2192                     end
2193                 end
2194
2195                if ( (old_arith == `xlSigned) && (new_arith == `xlUnsigned))
2196                   begin
2197                    if (~|inp[old_width-1 : abs_new_width])
2198                    begin
2199                       overflow = 0;
2200                    end
2201                end
2202
2203                if ((old_arith == `xlUnsigned) &&  (new_arith == `xlUnsigned))
2204                  begin
2205                    if (~|inp[old_width-1 : abs_new_width])
2206                     begin
2207                       overflow = 0;
2208                     end
2209                  end
2210
2211               if ( (old_arith == `xlUnsigned) && (new_arith == `xlSigned))
2212                 begin
2213                  if (~|inp[old_width-1:abs_new_width-1] || &inp[old_width-1:abs_new_width-1])
2214                    begin
2215                      overflow = 0;
2216                    end
2217                 end
2218               if (overflow == 1)
2219                 begin
2220                   if (new_arith == `xlSigned)
2221                     begin
2222                       if (inp[old_width-1] == 'b0)
2223                         begin
2224                           result = (new_width ==1) ? 1'b0 : {1'b0, {(new_width-1){1'b1}} };
2225                         end
2226                      else
2227                        begin
2228                          result = (new_width ==1) ? 1'b1 : {1'b1, {(new_width-1){1'b0}} };
2229                       end
2230                     end
2231                   else
2232                     begin
2233                       if ((old_arith == `xlSigned) && (inp[old_width-1] == 'b1))
2234                         begin
2235                           result = {new_width{1'b0}};
2236                         end
2237                       else
2238                         begin
2239                           result = {new_width{1'b1}};
2240                         end
2241                     end
2242                 end
2243               else
2244                 begin
2245                    if ( (old_arith == `xlSigned) && (new_arith == `xlUnsigned) && (inp[old_width-1] == 'b1) )
2246                    begin
2247                      vec = {old_width{1'b0}};
2248                    end
2249                    result = vec[new_width-1:0];
2250                 end
2251             end
2252        end
2253   endgenerate
2254   generate
2255      if (new_width > old_width)
2256        begin:sa_u1
2257         always @ (inp)
2258           begin
2259            vec = inp;
2260            if ( (old_arith == `xlSigned) && (new_arith == `xlUnsigned) && (inp[old_width-1] == 1'b1) )
2261              begin
2262                vec = {old_width{1'b0}};
2263              end
2264              if (new_arith == `xlUnsigned)
2265                begin
2266                  result = { {abs_width{1'b0}}, vec};
2267                end
2268              else
2269                begin
2270                  result = { {abs_width{inp[old_width-1]}}, vec};
2271                end
2272           end
2273       end
2274   endgenerate
2275
2276   generate
2277      if (new_width == old_width)
2278        begin:sa_u2
2279         always @ (inp)
2280           begin
2281             if ( (old_arith == `xlSigned) && (new_arith == `xlUnsigned) && (inp[old_width-1] == 'b1) )
2282               begin
2283                 result = {old_width{1'b0}};
2284               end
2285             else
2286               begin
2287                 result = inp;
2288               end
2289           end
2290        end
2291   endgenerate
2292
2293endmodule
2294module wrap_arith (inp, res);
2295    parameter signed [31:0]  old_width = 4;
2296    parameter signed [31:0]  old_bin_pt = 2;
2297    parameter signed [31:0]  old_arith = `xlSigned;
2298    parameter signed [31:0]  new_width = 4;
2299    parameter signed [31:0]  new_bin_pt = 1;
2300    parameter signed [31:0]  new_arith = `xlSigned;
2301    parameter signed [31:0]  result_arith = ((old_arith==`xlSigned)&&(new_arith==`xlUnsigned))? `xlSigned : new_arith;
2302    input [old_width - 1 : 0] inp;
2303    output [new_width - 1 : 0] res;
2304   wire [new_width-1:0] result;
2305   cast # (old_width, old_bin_pt, new_width, new_bin_pt, result_arith)
2306     wrap_cast (.inp(inp), .res(result));
2307   assign res = result;
2308
2309endmodule
2310module convert_type (inp, res);
2311    parameter signed [31:0]  old_width = 4;
2312    parameter signed [31:0]  old_bin_pt = 2;
2313    parameter signed [31:0]  old_arith = `xlSigned;
2314    parameter signed [31:0]  new_width = 4;
2315    parameter signed [31:0]  new_bin_pt = 1;
2316    parameter signed [31:0]  new_arith = `xlSigned;
2317    parameter signed [31:0]  quantization = `xlTruncate;
2318    parameter signed [31:0]  overflow = `xlWrap;
2319    input [old_width - 1 : 0] inp;
2320    output [new_width - 1 : 0] res;
2321
2322   parameter signed [31:0]  fp_width = old_width + 2;
2323   parameter signed [31:0]  fp_bin_pt = old_bin_pt;
2324   parameter signed [31:0]  fp_arith = old_arith;
2325   parameter signed [31:0]  q_width = fp_width + new_bin_pt - old_bin_pt;
2326   parameter signed [31:0]  q_bin_pt = new_bin_pt;
2327   parameter signed [31:0]  q_arith = old_arith;
2328   wire [fp_width-1:0] full_precision_result;
2329   wire [new_width-1:0] result;
2330   wire [q_width-1:0] quantized_result;
2331   assign res = result;
2332   cast # (old_width, old_bin_pt, fp_width, fp_bin_pt, fp_arith)
2333     fp_cast (.inp(inp), .res(full_precision_result));
2334   generate
2335      if (quantization == `xlRound)
2336        begin:ct_u0
2337           round_towards_inf # (fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith)
2338             quant_rtf (.inp(full_precision_result), .res(quantized_result));
2339        end
2340   endgenerate
2341
2342   generate
2343      if (quantization == `xlRoundBanker)
2344        begin:ct_u1
2345           round_towards_even # (fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith)
2346             quant_rte (.inp(full_precision_result), .res(quantized_result));
2347        end
2348   endgenerate
2349
2350   generate
2351      if (quantization == `xlTruncate)
2352        begin:ct_u2
2353           trunc # (fp_width, fp_bin_pt, fp_arith, q_width, q_bin_pt, q_arith)
2354             quant_tr (.inp(full_precision_result), .res(quantized_result));
2355        end
2356   endgenerate
2357
2358   generate
2359      if (overflow == `xlSaturate)
2360        begin:ct_u3
2361           saturation_arith # (q_width, q_bin_pt, q_arith, new_width, new_bin_pt, new_arith)
2362            ovflo_sat (.inp(quantized_result), .res(result));
2363        end
2364   endgenerate
2365
2366   generate
2367      if ((overflow == `xlWrap) || (overflow == 3))
2368        begin:ct_u4
2369           wrap_arith # (q_width, q_bin_pt, q_arith, new_width, new_bin_pt, new_arith)
2370             ovflo_wrap (.inp(quantized_result), .res(result));
2371        end
2372   endgenerate
2373
2374endmodule
2375//synopsys translate_off
2376`timescale 1 ns / 10 ps
2377module clock_pkg();
2378   wire int_clk;
2379endmodule
2380//synopsys translate_on
2381`endif
2382
2383
2384module constant_204e9a8bfd (
2385  output [(6 - 1):0] op,
2386  input clk,
2387  input ce,
2388  input clr);
2389  localparam [(6 - 1):0] const_value = 6'b000111;
2390  assign op = 6'b000111;
2391endmodule
2392 
2393
2394
2395
2396module constant_752327bec1 (
2397  output [(6 - 1):0] op,
2398  input clk,
2399  input ce,
2400  input clr);
2401  localparam [(6 - 1):0] const_value = 6'b011111;
2402  assign op = 6'b011111;
2403endmodule
2404 
2405
2406
2407//-----------------------------------------------------------------
2408// System Generator version 10.1.3 VERILOG source file.
2409//
2410// Copyright(C) 2008 by Xilinx, Inc.  All rights reserved.  This
2411// text/file contains proprietary, confidential information of Xilinx,
2412// Inc., is distributed under license from Xilinx, Inc., and may be used,
2413// copied and/or disclosed only pursuant to the terms of a valid license
2414// agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
2415// this text/file solely for design, simulation, implementation and
2416// creation of design files limited to Xilinx devices or technologies.
2417// Use with non-Xilinx devices or technologies is expressly prohibited
2418// and immediately terminates your license unless covered by a separate
2419// agreement.
2420//
2421// Xilinx is providing this design, code, or information "as is" solely
2422// for use in developing programs and solutions for Xilinx devices.  By
2423// providing this design, code, or information as one possible
2424// implementation of this feature, application or standard, Xilinx is
2425// making no representation that this implementation is free from any
2426// claims of infringement.  You are responsible for obtaining any rights
2427// you may require for your implementation.  Xilinx expressly disclaims
2428// any warranty whatsoever with respect to the adequacy of the
2429// implementation, including but not limited to warranties of
2430// merchantability or fitness for a particular purpose.
2431//
2432// Xilinx products are not intended for use in life support appliances,
2433// devices, or systems.  Use in such applications is expressly prohibited.
2434//
2435// Any modifications that are made to the source code are done at the user's
2436// sole risk and will be unsupported.
2437//
2438// This copyright and support notice must be retained as part of this
2439// text at all times.  (c) Copyright 1995-2008 Xilinx, Inc.  All rights
2440// reserved.
2441//-----------------------------------------------------------------
2442module xlcounter_free (ce, clr, clk, op, up, load, din, en, rst);
2443parameter core_name0= "";
2444parameter op_width= 5;
2445parameter op_arith= `xlSigned;
2446input ce, clr, clk;
2447input up, load;
2448input [op_width-1:0] din;
2449input en, rst;
2450output [op_width-1:0] op;
2451parameter [(8*op_width)-1:0] oneStr = { op_width{"1"}};
2452wire  core_sinit;
2453wire  core_ce;
2454wire [op_width-1:0] op_net;
2455   assign core_ce = ce & en;
2456   assign core_sinit = (clr | rst) & ce;
2457   assign op = op_net;
2458
2459
2460generate
2461  if (core_name0 == "binary_counter_virtex4_10_0_7f29bec8df1c7606")
2462    begin:comp0
2463    binary_counter_virtex4_10_0_7f29bec8df1c7606 core_instance0 (
2464        .clk(clk),
2465        .ce(core_ce),
2466        .sinit(core_sinit),
2467        .q(op_net)
2468      );
2469  end
2470  if (core_name0 == "binary_counter_virtex4_10_0_0e77c8b832175d2c")
2471    begin:comp1
2472    binary_counter_virtex4_10_0_0e77c8b832175d2c core_instance1 (
2473        .clk(clk),
2474        .ce(core_ce),
2475        .sinit(core_sinit),
2476        .q(op_net)
2477      );
2478  end
2479  if (core_name0 == "binary_counter_virtex4_10_0_407917162894eacc")
2480    begin:comp2
2481    binary_counter_virtex4_10_0_407917162894eacc core_instance2 (
2482        .clk(clk),
2483        .ce(core_ce),
2484        .sinit(core_sinit),
2485        .q(op_net)
2486      );
2487  end
2488endgenerate
2489endmodule
2490
2491//-----------------------------------------------------------------
2492// System Generator version 10.1.3 VERILOG source file.
2493//
2494// Copyright(C) 2008 by Xilinx, Inc.  All rights reserved.  This
2495// text/file contains proprietary, confidential information of Xilinx,
2496// Inc., is distributed under license from Xilinx, Inc., and may be used,
2497// copied and/or disclosed only pursuant to the terms of a valid license
2498// agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
2499// this text/file solely for design, simulation, implementation and
2500// creation of design files limited to Xilinx devices or technologies.
2501// Use with non-Xilinx devices or technologies is expressly prohibited
2502// and immediately terminates your license unless covered by a separate
2503// agreement.
2504//
2505// Xilinx is providing this design, code, or information "as is" solely
2506// for use in developing programs and solutions for Xilinx devices.  By
2507// providing this design, code, or information as one possible
2508// implementation of this feature, application or standard, Xilinx is
2509// making no representation that this implementation is free from any
2510// claims of infringement.  You are responsible for obtaining any rights
2511// you may require for your implementation.  Xilinx expressly disclaims
2512// any warranty whatsoever with respect to the adequacy of the
2513// implementation, including but not limited to warranties of
2514// merchantability or fitness for a particular purpose.
2515//
2516// Xilinx products are not intended for use in life support appliances,
2517// devices, or systems.  Use in such applications is expressly prohibited.
2518//
2519// Any modifications that are made to the source code are done at the user's
2520// sole risk and will be unsupported.
2521//
2522// This copyright and support notice must be retained as part of this
2523// text at all times.  (c) Copyright 1995-2008 Xilinx, Inc.  All rights
2524// reserved.
2525//-----------------------------------------------------------------
2526module xldelay #(parameter width = -1, latency = -1, reg_retiming = 0)
2527  (input [width-1:0] d,
2528   input ce, clk, en,
2529   output [width-1:0] q);
2530generate
2531  if ((latency == 0) || (reg_retiming == 0))
2532  begin:srl_delay
2533    synth_reg # (width, latency)
2534      reg1 (
2535        .i(d),
2536        .ce(ce & en),
2537        .clr(1'b0),
2538        .clk(clk),
2539        .o(q));
2540  end
2541
2542  if ((latency>=1) && (reg_retiming))
2543  begin:reg_delay
2544    synth_reg_reg # (width, latency)
2545      reg2 (
2546        .i(d),
2547        .ce(ce & en),
2548        .clr(1'b0),
2549        .clk(clk),
2550        .o(q));
2551  end
2552endgenerate
2553endmodule
2554
2555
2556module logical_28d385d867 (
2557  input [(1 - 1):0] d0,
2558  input [(1 - 1):0] d1,
2559  output [(1 - 1):0] y,
2560  input clk,
2561  input ce,
2562  input clr);
2563  wire d0_1_24;
2564  wire d1_1_27;
2565  wire fully_2_1_bit;
2566  assign d0_1_24 = d0;
2567  assign d1_1_27 = d1;
2568  assign fully_2_1_bit = d0_1_24 & d1_1_27;
2569  assign y = fully_2_1_bit;
2570endmodule
2571 
2572
2573
2574
2575module relational_440eb07a2f (
2576  input [(3 - 1):0] a,
2577  input [(6 - 1):0] b,
2578  input [(1 - 1):0] en,
2579  output [(1 - 1):0] op,
2580  input clk,
2581  input ce,
2582  input clr);
2583  wire [(3 - 1):0] a_1_31;
2584  wire [(6 - 1):0] b_1_34;
2585  wire en_1_37;
2586  reg op_mem_32_22[0:(1 - 1)];
2587  initial
2588    begin
2589      op_mem_32_22[0] = 1'b0;
2590    end
2591  wire op_mem_32_22_front_din;
2592  wire op_mem_32_22_back;
2593  wire op_mem_32_22_push_front_pop_back_en;
2594  localparam [(1 - 1):0] const_value = 1'b1;
2595  wire [(6 - 1):0] cast_14_12;
2596  wire result_14_3_rel;
2597  reg op_mem_shift_join_34_3;
2598  reg op_mem_shift_join_34_3_en;
2599  assign a_1_31 = a;
2600  assign b_1_34 = b;
2601  assign en_1_37 = en;
2602  assign op_mem_32_22_back = op_mem_32_22[0];
2603  always @(posedge clk)
2604    begin:proc_op_mem_32_22
2605      integer i;
2606      if (((ce == 1'b1) && (op_mem_32_22_push_front_pop_back_en == 1'b1)))
2607        begin
2608          op_mem_32_22[0] <= op_mem_32_22_front_din;
2609        end
2610    end
2611  assign cast_14_12 = {3'b000, a_1_31[2:0]};
2612  assign result_14_3_rel = cast_14_12 != b_1_34;
2613  always @(en_1_37 or result_14_3_rel)
2614    begin:proc_if_34_3
2615      if (en_1_37)
2616        begin
2617          op_mem_shift_join_34_3_en = 1'b1;
2618        end
2619      else 
2620        begin
2621          op_mem_shift_join_34_3_en = 1'b0;
2622        end
2623      op_mem_shift_join_34_3 = result_14_3_rel;
2624    end
2625  assign op_mem_32_22_front_din = op_mem_shift_join_34_3;
2626  assign op_mem_32_22_push_front_pop_back_en = op_mem_shift_join_34_3_en;
2627  assign op = op_mem_32_22_back;
2628endmodule
2629 
2630
2631
2632
2633module relational_7e0e56c195 (
2634  input [(5 - 1):0] a,
2635  input [(6 - 1):0] b,
2636  input [(1 - 1):0] en,
2637  output [(1 - 1):0] op,
2638  input clk,
2639  input ce,
2640  input clr);
2641  wire [(5 - 1):0] a_1_31;
2642  wire [(6 - 1):0] b_1_34;
2643  wire en_1_37;
2644  reg op_mem_32_22[0:(1 - 1)];
2645  initial
2646    begin
2647      op_mem_32_22[0] = 1'b0;
2648    end
2649  wire op_mem_32_22_front_din;
2650  wire op_mem_32_22_back;
2651  wire op_mem_32_22_push_front_pop_back_en;
2652  localparam [(1 - 1):0] const_value = 1'b1;
2653  wire [(6 - 1):0] cast_14_12;
2654  wire result_14_3_rel;
2655  reg op_mem_shift_join_34_3;
2656  reg op_mem_shift_join_34_3_en;
2657  assign a_1_31 = a;
2658  assign b_1_34 = b;
2659  assign en_1_37 = en;
2660  assign op_mem_32_22_back = op_mem_32_22[0];
2661  always @(posedge clk)
2662    begin:proc_op_mem_32_22
2663      integer i;
2664      if (((ce == 1'b1) && (op_mem_32_22_push_front_pop_back_en == 1'b1)))
2665        begin
2666          op_mem_32_22[0] <= op_mem_32_22_front_din;
2667        end
2668    end
2669  assign cast_14_12 = {1'b0, a_1_31[4:0]};
2670  assign result_14_3_rel = cast_14_12 != b_1_34;
2671  always @(en_1_37 or result_14_3_rel)
2672    begin:proc_if_34_3
2673      if (en_1_37)
2674        begin
2675          op_mem_shift_join_34_3_en = 1'b1;
2676        end
2677      else 
2678        begin
2679          op_mem_shift_join_34_3_en = 1'b0;
2680        end
2681      op_mem_shift_join_34_3 = result_14_3_rel;
2682    end
2683  assign op_mem_32_22_front_din = op_mem_shift_join_34_3;
2684  assign op_mem_32_22_push_front_pop_back_en = op_mem_shift_join_34_3_en;
2685  assign op = op_mem_32_22_back;
2686endmodule
2687 
2688
2689
2690//-----------------------------------------------------------------
2691// System Generator version 10.1.3 VERILOG source file.
2692//
2693// Copyright(C) 2008 by Xilinx, Inc.  All rights reserved.  This
2694// text/file contains proprietary, confidential information of Xilinx,
2695// Inc., is distributed under license from Xilinx, Inc., and may be used,
2696// copied and/or disclosed only pursuant to the terms of a valid license
2697// agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
2698// this text/file solely for design, simulation, implementation and
2699// creation of design files limited to Xilinx devices or technologies.
2700// Use with non-Xilinx devices or technologies is expressly prohibited
2701// and immediately terminates your license unless covered by a separate
2702// agreement.
2703//
2704// Xilinx is providing this design, code, or information "as is" solely
2705// for use in developing programs and solutions for Xilinx devices.  By
2706// providing this design, code, or information as one possible
2707// implementation of this feature, application or standard, Xilinx is
2708// making no representation that this implementation is free from any
2709// claims of infringement.  You are responsible for obtaining any rights
2710// you may require for your implementation.  Xilinx expressly disclaims
2711// any warranty whatsoever with respect to the adequacy of the
2712// implementation, including but not limited to warranties of
2713// merchantability or fitness for a particular purpose.
2714//
2715// Xilinx products are not intended for use in life support appliances,
2716// devices, or systems.  Use in such applications is expressly prohibited.
2717//
2718// Any modifications that are made to the source code are done at the user's
2719// sole risk and will be unsupported.
2720//
2721// This copyright and support notice must be retained as part of this
2722// text at all times.  (c) Copyright 1995-2008 Xilinx, Inc.  All rights
2723// reserved.
2724//-----------------------------------------------------------------
2725module  xlslice  (x, y);
2726parameter new_msb= 9;
2727parameter new_lsb= 1;
2728parameter x_width= 16;
2729parameter y_width= 8;
2730input [x_width-1:0] x;
2731output [y_width-1:0] y;
2732assign y = x[new_msb:new_lsb];
2733endmodule
2734
2735
2736module concat_fb3e05a33e (
2737  input [(8 - 1):0] in0,
2738  input [(2 - 1):0] in1,
2739  output [(10 - 1):0] y,
2740  input clk,
2741  input ce,
2742  input clr);
2743  wire [(8 - 1):0] in0_1_23;
2744  wire [(2 - 1):0] in1_1_27;
2745  wire [(10 - 1):0] y_2_1_concat;
2746  assign in0_1_23 = in0;
2747  assign in1_1_27 = in1;
2748  assign y_2_1_concat = {in0_1_23, in1_1_27};
2749  assign y = y_2_1_concat;
2750endmodule
2751 
2752
2753
2754
2755module constant_9e0724a33a (
2756  output [(2 - 1):0] op,
2757  input clk,
2758  input ce,
2759  input clr);
2760  localparam [(2 - 1):0] const_value = 2'b00;
2761  assign op = 2'b00;
2762endmodule
2763 
2764
2765
2766
2767module relational_d74f8dcf86 (
2768  input [(10 - 1):0] a,
2769  input [(10 - 1):0] b,
2770  output [(1 - 1):0] op,
2771  input clk,
2772  input ce,
2773  input clr);
2774  wire [(10 - 1):0] a_1_31;
2775  wire [(10 - 1):0] b_1_34;
2776  reg op_mem_32_22[0:(1 - 1)];
2777  initial
2778    begin
2779      op_mem_32_22[0] = 1'b0;
2780    end
2781  wire op_mem_32_22_front_din;
2782  wire op_mem_32_22_back;
2783  wire op_mem_32_22_push_front_pop_back_en;
2784  localparam [(1 - 1):0] const_value = 1'b1;
2785  wire result_12_3_rel;
2786  assign a_1_31 = a;
2787  assign b_1_34 = b;
2788  assign op_mem_32_22_back = op_mem_32_22[0];
2789  always @(posedge clk)
2790    begin:proc_op_mem_32_22
2791      integer i;
2792      if (((ce == 1'b1) && (op_mem_32_22_push_front_pop_back_en == 1'b1)))
2793        begin
2794          op_mem_32_22[0] <= op_mem_32_22_front_din;
2795        end
2796    end
2797  assign result_12_3_rel = a_1_31 == b_1_34;
2798  assign op_mem_32_22_front_din = result_12_3_rel;
2799  assign op_mem_32_22_push_front_pop_back_en = 1'b1;
2800  assign op = op_mem_32_22_back;
2801endmodule
2802 
2803
2804
2805
2806module logical_7970a672aa (
2807  input [(1 - 1):0] d0,
2808  input [(1 - 1):0] d1,
2809  output [(1 - 1):0] y,
2810  input clk,
2811  input ce,
2812  input clr);
2813  wire d0_1_24;
2814  wire d1_1_27;
2815  wire fully_2_1_bit;
2816  assign d0_1_24 = d0;
2817  assign d1_1_27 = d1;
2818  assign fully_2_1_bit = d0_1_24 | d1_1_27;
2819  assign y = fully_2_1_bit;
2820endmodule
2821 
2822
2823
2824
2825module constant_787b59efba (
2826  output [(10 - 1):0] op,
2827  input clk,
2828  input ce,
2829  input clr);
2830  localparam [(10 - 1):0] const_value = 10'b0000000010;
2831  assign op = 10'b0000000010;
2832endmodule
2833 
2834
2835
2836//-----------------------------------------------------------------
2837// System Generator version 10.1.3 VERILOG source file.
2838//
2839// Copyright(C) 2008 by Xilinx, Inc.  All rights reserved.  This
2840// text/file contains proprietary, confidential information of Xilinx,
2841// Inc., is distributed under license from Xilinx, Inc., and may be used,
2842// copied and/or disclosed only pursuant to the terms of a valid license
2843// agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
2844// this text/file solely for design, simulation, implementation and
2845// creation of design files limited to Xilinx devices or technologies.
2846// Use with non-Xilinx devices or technologies is expressly prohibited
2847// and immediately terminates your license unless covered by a separate
2848// agreement.
2849//
2850// Xilinx is providing this design, code, or information "as is" solely
2851// for use in developing programs and solutions for Xilinx devices.  By
2852// providing this design, code, or information as one possible
2853// implementation of this feature, application or standard, Xilinx is
2854// making no representation that this implementation is free from any
2855// claims of infringement.  You are responsible for obtaining any rights
2856// you may require for your implementation.  Xilinx expressly disclaims
2857// any warranty whatsoever with respect to the adequacy of the
2858// implementation, including but not limited to warranties of
2859// merchantability or fitness for a particular purpose.
2860//
2861// Xilinx products are not intended for use in life support appliances,
2862// devices, or systems.  Use in such applications is expressly prohibited.
2863//
2864// Any modifications that are made to the source code are done at the user's
2865// sole risk and will be unsupported.
2866//
2867// This copyright and support notice must be retained as part of this
2868// text at all times.  (c) Copyright 1995-2008 Xilinx, Inc.  All rights
2869// reserved.
2870//-----------------------------------------------------------------
2871module xladdsubv10_0 (a, b, c_in, ce, clr, clk, rst, en, c_out, s);
2872parameter core_name0= "";
2873parameter a_width= 16;
2874parameter signed a_bin_pt= 4;
2875parameter a_arith= `xlUnsigned;
2876parameter c_in_width= 16;
2877parameter c_in_bin_pt= 4;
2878parameter c_in_arith= `xlUnsigned;
2879parameter c_out_width= 16;
2880parameter c_out_bin_pt= 4;
2881parameter c_out_arith= `xlUnsigned;
2882parameter b_width= 8;
2883parameter signed b_bin_pt= 2;
2884parameter b_arith= `xlUnsigned;
2885parameter s_width= 17;
2886parameter s_bin_pt= 4;
2887parameter s_arith= `xlUnsigned;
2888parameter rst_width= 1;
2889parameter rst_bin_pt= 0;
2890parameter rst_arith= `xlUnsigned;
2891parameter en_width= 1;
2892parameter en_bin_pt= 0;
2893parameter en_arith= `xlUnsigned;
2894parameter full_s_width= 17;
2895parameter full_s_arith= `xlUnsigned;
2896parameter mode= `xlAddMode;
2897parameter extra_registers= 0;
2898parameter latency= 0;
2899parameter quantization= `xlTruncate;
2900parameter overflow= `xlWrap;
2901parameter c_a_width= 16;
2902parameter c_b_width= 8;
2903parameter c_a_type= 1;
2904parameter c_b_type= 1;
2905parameter c_has_sclr= 0;
2906parameter c_has_ce= 0;
2907parameter c_latency= 0;
2908parameter c_output_width= 17;
2909parameter c_enable_rlocs= 1;
2910parameter c_has_c_in= 0;
2911parameter c_has_c_out= 0;
2912input [a_width-1:0] a;
2913input [b_width-1:0] b;
2914input c_in, ce, clr, clk, rst, en;
2915output c_out;
2916output [s_width-1:0] s;
2917parameter full_a_width = full_s_width;
2918parameter full_b_width = full_s_width;
2919parameter full_s_bin_pt = (a_bin_pt > b_bin_pt) ? a_bin_pt : b_bin_pt;
2920wire [full_a_width-1:0] full_a;
2921wire [full_b_width-1:0] full_b;
2922wire [full_s_width-1:0] full_s;
2923wire [full_s_width-1:0] core_s;
2924wire [s_width-1:0] conv_s;
2925wire  temp_cout;
2926wire  real_a,real_b,real_s;
2927wire  internal_clr;
2928wire  internal_ce;
2929wire  extra_reg_ce;
2930wire  override;
2931wire  logic1;
2932wire  temp_cin;
2933assign internal_clr = (clr | rst) & ce;
2934assign internal_ce = ce & en;
2935assign logic1 = 1'b1;
2936assign temp_cin = (c_has_c_in) ? c_in : 1'b0;
2937align_input # (a_width, b_bin_pt - a_bin_pt, a_arith, full_a_width)
2938align_inp_a(.inp(a),.res(full_a));
2939align_input # (b_width, a_bin_pt - b_bin_pt, b_arith, full_b_width)
2940align_inp_b(.inp(b),.res(full_b));
2941convert_type # (full_s_width, full_s_bin_pt, full_s_arith, s_width,
2942                s_bin_pt, s_arith, quantization, overflow)
2943conv_typ_s(.inp(core_s),.res(conv_s));
2944generate
2945  if (core_name0 == "adder_subtracter_virtex4_10_0_80b315fd28a09ef0")
2946    begin:comp0
2947    adder_subtracter_virtex4_10_0_80b315fd28a09ef0 core_instance0 (
2948         .a(full_a),
2949         .s(core_s),
2950         .b(full_b)
2951      );
2952  end
2953
2954endgenerate
2955generate
2956  if (extra_registers > 0)
2957  begin:latency_test
2958
2959    if (c_latency > 1)
2960    begin:override_test
2961      synth_reg # (1, c_latency)
2962        override_pipe (
2963          .i(logic1),
2964          .ce(internal_ce),
2965          .clr(internal_clr),
2966          .clk(clk),
2967          .o(override));
2968      assign extra_reg_ce = ce & en & override;
2969    end
2970    if ((c_latency == 0) || (c_latency == 1))
2971    begin:no_override
2972      assign extra_reg_ce = ce & en;
2973    end
2974    synth_reg # (s_width, extra_registers)
2975      extra_reg (
2976        .i(conv_s),
2977        .ce(extra_reg_ce),
2978        .clr(internal_clr),
2979        .clk(clk),
2980        .o(s));
2981    if (c_has_c_out == 1)
2982    begin:cout_test
2983      synth_reg # (1, extra_registers)
2984        c_out_extra_reg (
2985          .i(temp_cout),
2986          .ce(extra_reg_ce),
2987          .clr(internal_clr),
2988          .clk(clk),
2989          .o(c_out));
2990    end
2991
2992  end
2993endgenerate
2994generate
2995  if ((latency == 0) || (extra_registers == 0))
2996  begin:latency_s
2997    assign s = conv_s;
2998  end
2999endgenerate
3000generate
3001  if (((latency == 0) || (extra_registers == 0)) &&
3002      (c_has_c_out == 1))
3003  begin:latency0
3004    assign c_out = temp_cout;
3005  end
3006endgenerate
3007generate
3008  if (c_has_c_out == 0)
3009  begin:tie_dangling_cout
3010    assign c_out = 0;
3011  end
3012endgenerate
3013endmodule
3014
3015
3016module concat_ba8a620a74 (
3017  input [(2 - 1):0] in0,
3018  input [(8 - 1):0] in1,
3019  output [(10 - 1):0] y,
3020  input clk,
3021  input ce,
3022  input clr);
3023  wire [(2 - 1):0] in0_1_23;
3024  wire [(8 - 1):0] in1_1_27;
3025  wire [(10 - 1):0] y_2_1_concat;
3026  assign in0_1_23 = in0;
3027  assign in1_1_27 = in1;
3028  assign y_2_1_concat = {in0_1_23, in1_1_27};
3029  assign y = y_2_1_concat;
3030endmodule
3031 
3032
3033
3034
3035module inverter_33a63b558a (
3036  input [(1 - 1):0] ip,
3037  output [(1 - 1):0] op,
3038  input clk,
3039  input ce,
3040  input clr);
3041  wire ip_1_26;
3042  reg op_mem_22_20[0:(1 - 1)];
3043  initial
3044    begin
3045      op_mem_22_20[0] = 1'b0;
3046    end
3047  wire op_mem_22_20_front_din;
3048  wire op_mem_22_20_back;
3049  wire op_mem_22_20_push_front_pop_back_en;
3050  localparam [(1 - 1):0] const_value = 1'b1;
3051  wire internal_ip_12_1_bitnot;
3052  assign ip_1_26 = ip;
3053  assign op_mem_22_20_back = op_mem_22_20[0];
3054  always @(posedge clk)
3055    begin:proc_op_mem_22_20
3056      integer i;
3057      if (((ce == 1'b1) && (op_mem_22_20_push_front_pop_back_en == 1'b1)))
3058        begin
3059          op_mem_22_20[0] <= op_mem_22_20_front_din;
3060        end
3061    end
3062  assign internal_ip_12_1_bitnot = ~ip_1_26;
3063  assign op_mem_22_20_push_front_pop_back_en = 1'b0;
3064  assign op = internal_ip_12_1_bitnot;
3065endmodule
3066 
3067
3068
3069
3070module logical_818bd6d54b (
3071  input [(1 - 1):0] d0,
3072  input [(1 - 1):0] d1,
3073  input [(1 - 1):0] d2,
3074  input [(1 - 1):0] d3,
3075  output [(1 - 1):0] y,
3076  input clk,
3077  input ce,
3078  input clr);
3079  wire d0_1_24;
3080  wire d1_1_27;
3081  wire d2_1_30;
3082  wire d3_1_33;
3083  wire fully_2_1_bit;
3084  assign d0_1_24 = d0;
3085  assign d1_1_27 = d1;
3086  assign d2_1_30 = d2;
3087  assign d3_1_33 = d3;
3088  assign fully_2_1_bit = d0_1_24 & d1_1_27 & d2_1_30 & d3_1_33;
3089  assign y = fully_2_1_bit;
3090endmodule
3091 
3092
3093
3094//-----------------------------------------------------------------
3095// System Generator version 10.1.3 VERILOG source file.
3096//
3097// Copyright(C) 2008 by Xilinx, Inc.  All rights reserved.  This
3098// text/file contains proprietary, confidential information of Xilinx,
3099// Inc., is distributed under license from Xilinx, Inc., and may be used,
3100// copied and/or disclosed only pursuant to the terms of a valid license
3101// agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
3102// this text/file solely for design, simulation, implementation and
3103// creation of design files limited to Xilinx devices or technologies.
3104// Use with non-Xilinx devices or technologies is expressly prohibited
3105// and immediately terminates your license unless covered by a separate
3106// agreement.
3107//
3108// Xilinx is providing this design, code, or information "as is" solely
3109// for use in developing programs and solutions for Xilinx devices.  By
3110// providing this design, code, or information as one possible
3111// implementation of this feature, application or standard, Xilinx is
3112// making no representation that this implementation is free from any
3113// claims of infringement.  You are responsible for obtaining any rights
3114// you may require for your implementation.  Xilinx expressly disclaims
3115// any warranty whatsoever with respect to the adequacy of the
3116// implementation, including but not limited to warranties of
3117// merchantability or fitness for a particular purpose.
3118//
3119// Xilinx products are not intended for use in life support appliances,
3120// devices, or systems.  Use in such applications is expressly prohibited.
3121//
3122// Any modifications that are made to the source code are done at the user's
3123// sole risk and will be unsupported.
3124//
3125// This copyright and support notice must be retained as part of this
3126// text at all times.  (c) Copyright 1995-2008 Xilinx, Inc.  All rights
3127// reserved.
3128//-----------------------------------------------------------------
3129`timescale 1 ns / 10 ps
3130module xlregister (d, rst, en, ce, clk, q);
3131   parameter d_width = 5;
3132   parameter init_value = 'b0;
3133
3134   input [d_width-1:0] d;
3135   input rst, en, ce, clk;
3136   output [d_width-1:0] q;
3137   wire internal_clr, internal_ce;
3138   assign internal_clr = rst & ce;
3139   assign internal_ce  = ce & en;
3140
3141   synth_reg_w_init #(.width(d_width),
3142                      .init_index(2),
3143                      .init_value(init_value),
3144                      .latency(1))
3145   synth_reg_inst(.i(d),
3146                  .ce(internal_ce),
3147                  .clr(internal_clr),
3148                  .clk(clk),
3149                  .o(q));
3150endmodule
3151
3152
3153module mux_485ea02169 (
3154  input [(1 - 1):0] sel,
3155  input [(1 - 1):0] d0,
3156  input [(1 - 1):0] d1,
3157  output [(1 - 1):0] y,
3158  input clk,
3159  input ce,
3160  input clr);
3161  wire sel_1_20;
3162  wire [(1 - 1):0] d0_1_24;
3163  wire [(1 - 1):0] d1_1_27;
3164  wire [(1 - 1):0] sel_internal_2_1_convert;
3165  reg [(1 - 1):0] unregy_join_6_1;
3166  assign sel_1_20 = sel;
3167  assign d0_1_24 = d0;
3168  assign d1_1_27 = d1;
3169  assign sel_internal_2_1_convert = {sel_1_20};
3170  always @(d0_1_24 or d1_1_27 or sel_internal_2_1_convert)
3171    begin:proc_switch_6_1
3172      case (sel_internal_2_1_convert)
3173        1'b0 :
3174          begin
3175            unregy_join_6_1 = d0_1_24;
3176          end
3177        default:
3178          begin
3179            unregy_join_6_1 = d1_1_27;
3180          end
3181      endcase
3182    end
3183  assign y = unregy_join_6_1;
3184endmodule
3185 
3186
3187
3188
3189module constant_9cf45430cd (
3190  output [(1 - 1):0] op,
3191  input clk,
3192  input ce,
3193  input clr);
3194  localparam [(1 - 1):0] const_value = 1'b1;
3195  assign op = 1'b1;
3196endmodule
3197 
3198
3199
3200
3201module constant_67d0b5242e (
3202  output [(8 - 1):0] op,
3203  input clk,
3204  input ce,
3205  input clr);
3206  localparam [(8 - 1):0] const_value = 8'b00000010;
3207  assign op = 8'b00000010;
3208endmodule
3209 
3210
3211
3212
3213module mux_f80a0abc7d (
3214  input [(3 - 1):0] sel,
3215  input [(8 - 1):0] d0,
3216  input [(8 - 1):0] d1,
3217  input [(8 - 1):0] d2,
3218  input [(8 - 1):0] d3,
3219  input [(8 - 1):0] d4,
3220  input [(8 - 1):0] d5,
3221  input [(8 - 1):0] d6,
3222  input [(8 - 1):0] d7,
3223  output [(8 - 1):0] y,
3224  input clk,
3225  input ce,
3226  input clr);
3227  wire [(3 - 1):0] sel_1_20;
3228  wire [(8 - 1):0] d0_1_24;
3229  wire [(8 - 1):0] d1_1_27;
3230  wire [(8 - 1):0] d2_1_30;
3231  wire [(8 - 1):0] d3_1_33;
3232  wire [(8 - 1):0] d4_1_36;
3233  wire [(8 - 1):0] d5_1_39;
3234  wire [(8 - 1):0] d6_1_42;
3235  wire [(8 - 1):0] d7_1_45;
3236  reg [(8 - 1):0] unregy_join_6_1;
3237  assign sel_1_20 = sel;
3238  assign d0_1_24 = d0;
3239  assign d1_1_27 = d1;
3240  assign d2_1_30 = d2;
3241  assign d3_1_33 = d3;
3242  assign d4_1_36 = d4;
3243  assign d5_1_39 = d5;
3244  assign d6_1_42 = d6;
3245  assign d7_1_45 = d7;
3246  always @(d0_1_24 or d1_1_27 or d2_1_30 or d3_1_33 or d4_1_36 or d5_1_39 or d6_1_42 or d7_1_45 or sel_1_20)
3247    begin:proc_switch_6_1
3248      case (sel_1_20)
3249        3'b000 :
3250          begin
3251            unregy_join_6_1 = d0_1_24;
3252          end
3253        3'b001 :
3254          begin
3255            unregy_join_6_1 = d1_1_27;
3256          end
3257        3'b010 :
3258          begin
3259            unregy_join_6_1 = d2_1_30;
3260          end
3261        3'b011 :
3262          begin
3263            unregy_join_6_1 = d3_1_33;
3264          end
3265        3'b100 :
3266          begin
3267            unregy_join_6_1 = d4_1_36;
3268          end
3269        3'b101 :
3270          begin
3271            unregy_join_6_1 = d5_1_39;
3272          end
3273        3'b110 :
3274          begin
3275            unregy_join_6_1 = d6_1_42;
3276          end
3277        default:
3278          begin
3279            unregy_join_6_1 = d7_1_45;
3280          end
3281      endcase
3282    end
3283  assign y = unregy_join_6_1;
3284endmodule
3285 
3286
3287
3288//-----------------------------------------------------------------
3289// System Generator version 10.1.3 VERILOG source file.
3290//
3291// Copyright(C) 2008 by Xilinx, Inc.  All rights reserved.  This
3292// text/file contains proprietary, confidential information of Xilinx,
3293// Inc., is distributed under license from Xilinx, Inc., and may be used,
3294// copied and/or disclosed only pursuant to the terms of a valid license
3295// agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
3296// this text/file solely for design, simulation, implementation and
3297// creation of design files limited to Xilinx devices or technologies.
3298// Use with non-Xilinx devices or technologies is expressly prohibited
3299// and immediately terminates your license unless covered by a separate
3300// agreement.
3301//
3302// Xilinx is providing this design, code, or information "as is" solely
3303// for use in developing programs and solutions for Xilinx devices.  By
3304// providing this design, code, or information as one possible
3305// implementation of this feature, application or standard, Xilinx is
3306// making no representation that this implementation is free from any
3307// claims of infringement.  You are responsible for obtaining any rights
3308// you may require for your implementation.  Xilinx expressly disclaims
3309// any warranty whatsoever with respect to the adequacy of the
3310// implementation, including but not limited to warranties of
3311// merchantability or fitness for a particular purpose.
3312//
3313// Xilinx products are not intended for use in life support appliances,
3314// devices, or systems.  Use in such applications is expressly prohibited.
3315//
3316// Any modifications that are made to the source code are done at the user's
3317// sole risk and will be unsupported.
3318//
3319// This copyright and support notice must be retained as part of this
3320// text at all times.  (c) Copyright 1995-2008 Xilinx, Inc.  All rights
3321// reserved.
3322//-----------------------------------------------------------------
3323module  xlp2s  (din, src_ce, src_clr, src_clk, dest_ce, dest_clr, dest_clk, rst, en, dout);
3324parameter dout_width= 8;
3325parameter dout_arith= `xlSigned;
3326parameter dout_bin_pt= 0;
3327parameter din_width= 1;
3328parameter din_arith= `xlUnsigned;
3329parameter din_bin_pt= 0;
3330parameter rst_width= 1;
3331parameter rst_bin_pt= 0;
3332parameter rst_arith= `xlUnsigned;
3333parameter en_width= 1;
3334parameter en_bin_pt= 0;
3335parameter en_arith= `xlUnsigned;
3336parameter lsb_first= 0;
3337parameter latency= 0;
3338parameter num_outputs= 0;
3339input [din_width-1:0] din;
3340input src_ce, src_clr, src_clk;
3341input dest_ce, dest_clr, dest_clk;
3342input rst;
3343input en;
3344output [dout_width-1:0] dout;
3345   wire [dout_width-1:0] i [0:num_outputs-1];
3346   wire [din_width-1:0] din_temp;
3347   wire [dout_width-1:0] o [0:num_outputs-1];
3348   wire [dout_width-1:0] dout_temp;
3349   wire src_ce_hold;
3350   wire internal_src_ce;
3351   wire internal_dest_ce;
3352   wire internal_clr;
3353   genvar index, idx, idx1;
3354
3355   assign internal_src_ce = src_ce_hold & en;
3356   assign internal_dest_ce = dest_ce & en;
3357   assign internal_clr = (dest_clr | src_clr | rst) & dest_ce;
3358   assign dout_temp = internal_src_ce ? din_temp[dout_width-1:0]: o[1];
3359   FDSE src_ce_reg(.Q(src_ce_hold),
3360                   .D(src_ce),
3361                   .C(src_clk),
3362                   .CE(dest_ce),
3363                   .S(src_clr));
3364   generate
3365      if (lsb_first==1)
3366        begin:lsb_is_first
3367           assign din_temp = din;
3368        end
3369      else
3370        begin:msb_is_first
3371           p2s_bit_reverse # (din_width, dout_width, num_outputs) reverse_input(.din(din), .dout(din_temp));
3372        end
3373   endgenerate
3374
3375   generate
3376      for(index=0; index<num_outputs; index=index+1)
3377        begin:fd_array
3378           synth_reg_w_init # (dout_width, 0, 1'b0, 1)
3379             capture ( .i(i[index]),
3380                       .ce(internal_dest_ce),
3381                       .clr(internal_clr),
3382                       .clk(dest_clk),
3383                       .o(o[index]));
3384        end
3385   endgenerate
3386   generate
3387      for (idx=0; idx<num_outputs; idx=idx+1)
3388        begin:signal_select
3389           if (idx < num_outputs-1)
3390             begin:signal_0
3391                assign i[idx] = internal_src_ce ? din_temp[idx*dout_width+dout_width-1:idx*dout_width] : o[idx+1];
3392             end
3393           if (idx == num_outputs-1)
3394             begin:signal_1
3395                assign i[idx] = internal_src_ce ? din_temp[idx*dout_width+dout_width-1:idx*dout_width] : o[idx];
3396             end
3397        end
3398   endgenerate
3399   generate
3400      if (latency > 0)
3401        begin:latency_gt_0
3402           synth_reg # (dout_width, latency)
3403             data_reg (.i(dout_temp),
3404                       .ce(internal_dest_ce),
3405                       .clr(internal_clr),
3406                       .clk(dest_clk),
3407                       .o(dout));
3408        end
3409      if (latency == 0)
3410        begin:latency0
3411           assign dout = dout_temp;
3412        end
3413   endgenerate
3414endmodule
3415module p2s_bit_reverse (din, dout);
3416   parameter din_width = 8;
3417   parameter dout_width = 2;
3418   parameter num_outputs = 4;
3419   input [din_width-1:0] din;
3420   output [din_width-1:0] dout;
3421   genvar index;
3422   generate
3423      for (index=0; index<num_outputs; index=index+1)
3424        begin:u0
3425          assign dout[(num_outputs-index)*dout_width-1:(num_outputs-index-1)*dout_width] = din[index*dout_width+dout_width-1:index*dout_width];
3426       end
3427 endgenerate
3428endmodule
3429
3430
3431module constant_11c05a5fb4 (
3432  output [(8 - 1):0] op,
3433  input clk,
3434  input ce,
3435  input clr);
3436  localparam [(8 - 1):0] const_value = 8'b00000000;
3437  assign op = 8'b00000000;
3438endmodule
3439 
3440
3441
3442
3443module constant_4ffad13294 (
3444  output [(8 - 1):0] op,
3445  input clk,
3446  input ce,
3447  input clr);
3448  localparam [(8 - 1):0] const_value = 8'b00000110;
3449  assign op = 8'b00000110;
3450endmodule
3451 
3452
3453
3454
3455module constant_5e90e4a8ec (
3456  output [(1 - 1):0] op,
3457  input clk,
3458  input ce,
3459  input clr);
3460  assign op = 1'b1;
3461endmodule
3462 
3463
3464
3465//-----------------------------------------------------------------
3466// System Generator version 10.1.3 VERILOG source file.
3467//
3468// Copyright(C) 2008 by Xilinx, Inc.  All rights reserved.  This
3469// text/file contains proprietary, confidential information of Xilinx,
3470// Inc., is distributed under license from Xilinx, Inc., and may be used,
3471// copied and/or disclosed only pursuant to the terms of a valid license
3472// agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
3473// this text/file solely for design, simulation, implementation and
3474// creation of design files limited to Xilinx devices or technologies.
3475// Use with non-Xilinx devices or technologies is expressly prohibited
3476// and immediately terminates your license unless covered by a separate
3477// agreement.
3478//
3479// Xilinx is providing this design, code, or information "as is" solely
3480// for use in developing programs and solutions for Xilinx devices.  By
3481// providing this design, code, or information as one possible
3482// implementation of this feature, application or standard, Xilinx is
3483// making no representation that this implementation is free from any
3484// claims of infringement.  You are responsible for obtaining any rights
3485// you may require for your implementation.  Xilinx expressly disclaims
3486// any warranty whatsoever with respect to the adequacy of the
3487// implementation, including but not limited to warranties of
3488// merchantability or fitness for a particular purpose.
3489//
3490// Xilinx products are not intended for use in life support appliances,
3491// devices, or systems.  Use in such applications is expressly prohibited.
3492//
3493// Any modifications that are made to the source code are done at the user's
3494// sole risk and will be unsupported.
3495//
3496// This copyright and support notice must be retained as part of this
3497// text at all times.  (c) Copyright 1995-2008 Xilinx, Inc.  All rights
3498// reserved.
3499//-----------------------------------------------------------------
3500module  xldsamp  (d, src_clk, src_ce, src_clr, dest_clk, dest_ce, dest_clr, en, q);
3501parameter d_width= 12;
3502parameter d_bin_pt= 0;
3503parameter d_arith= `xlUnsigned;
3504parameter q_width= 12;
3505parameter q_bin_pt= 0;
3506parameter q_arith= `xlUnsigned;
3507parameter en_width= 1;
3508parameter en_bin_pt= 0;
3509parameter en_arith= `xlUnsigned;
3510parameter ds_ratio= 2;
3511parameter phase= 0;
3512parameter latency= 1;
3513input [d_width-1:0] d;
3514input  src_clk;
3515input  src_ce;
3516input  src_clr;
3517input  dest_clk;
3518input  dest_ce;
3519input  dest_clr;
3520input [en_width-1:0] en;
3521output [q_width-1:0] q;
3522wire  adjusted_dest_ce;
3523wire  adjusted_dest_ce_w_en;
3524wire  dest_ce_w_en;
3525wire [d_width-1:0] smpld_d;
3526reg [q_width-1:0] q_reg;
3527assign dest_ce_w_en = dest_ce & en[0];
3528assign adjusted_dest_ce_w_en = adjusted_dest_ce & en[0];
3529generate
3530if((latency==0) | (phase!= (ds_ratio-1)))
3531   begin:adjusted_ce_needed
3532   FDSE dest_ce_reg(.Q(adjusted_dest_ce),
3533                    .D(dest_ce),
3534                    .C(src_clk),
3535                    .S(src_clr),
3536                    .CE(src_ce)
3537                   );
3538   end
3539if(latency==0)
3540  begin:shutter_d_reg
3541  synth_reg # (d_width,1)
3542  reg1(.i(d),
3543       .ce(adjusted_dest_ce),
3544       .clr(src_clr),
3545       .clk(src_clk),
3546       .o(smpld_d)
3547      );
3548
3549   assign q = q_reg;
3550   always@(adjusted_dest_ce,d,smpld_d)
3551      begin
3552        if(adjusted_dest_ce == 'b0) begin
3553           q_reg = smpld_d;
3554        end
3555        else begin
3556           q_reg = d;
3557        end
3558      end
3559  end
3560 if(latency > 0)
3561 begin:double_reg_test
3562   if( phase!= (ds_ratio-1))
3563   begin:smpl_d_reg
3564   synth_reg # (d_width, 1)
3565          reg2 (
3566               .i(d),
3567               .ce(adjusted_dest_ce_w_en),
3568               .clr(src_clr),
3569               .clk(src_clk),
3570               .o(smpld_d));
3571   end
3572  if( phase == (ds_ratio-1))
3573  begin:sngl_reg_test
3574        assign smpld_d = d;
3575  end
3576  synth_reg # (d_width, latency)
3577          reg2 (
3578               .i(smpld_d),
3579               .ce(dest_ce_w_en),
3580               .clr(src_clr),
3581               .clk(src_clk),
3582               .o(q));
3583end
3584
3585endgenerate
3586endmodule
3587
3588//-----------------------------------------------------------------
3589// System Generator version 10.1.3 VERILOG source file.
3590//
3591// Copyright(C) 2008 by Xilinx, Inc.  All rights reserved.  This
3592// text/file contains proprietary, confidential information of Xilinx,
3593// Inc., is distributed under license from Xilinx, Inc., and may be used,
3594// copied and/or disclosed only pursuant to the terms of a valid license
3595// agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
3596// this text/file solely for design, simulation, implementation and
3597// creation of design files limited to Xilinx devices or technologies.
3598// Use with non-Xilinx devices or technologies is expressly prohibited
3599// and immediately terminates your license unless covered by a separate
3600// agreement.
3601//
3602// Xilinx is providing this design, code, or information "as is" solely
3603// for use in developing programs and solutions for Xilinx devices.  By
3604// providing this design, code, or information as one possible
3605// implementation of this feature, application or standard, Xilinx is
3606// making no representation that this implementation is free from any
3607// claims of infringement.  You are responsible for obtaining any rights
3608// you may require for your implementation.  Xilinx expressly disclaims
3609// any warranty whatsoever with respect to the adequacy of the
3610// implementation, including but not limited to warranties of
3611// merchantability or fitness for a particular purpose.
3612//
3613// Xilinx products are not intended for use in life support appliances,
3614// devices, or systems.  Use in such applications is expressly prohibited.
3615//
3616// Any modifications that are made to the source code are done at the user's
3617// sole risk and will be unsupported.
3618//
3619// This copyright and support notice must be retained as part of this
3620// text at all times.  (c) Copyright 1995-2008 Xilinx, Inc.  All rights
3621// reserved.
3622//-----------------------------------------------------------------
3623module xldpram_dist (dina, addra, wea, ena, a_ce, a_clk, douta, addrb, enb, b_ce, b_clk, doutb);
3624parameter core_name0= "";
3625parameter addr_width = 12;
3626parameter c_width= 12;
3627parameter c_address_width= 4;
3628parameter latency= 1;
3629input [c_width-1:0] dina;
3630input [addr_width-1:0] addra;
3631input wea, ena, a_ce, a_clk;
3632output [c_width-1:0] douta;
3633input [addr_width-1:0] addrb;
3634input enb, b_ce, b_clk;
3635output [c_width-1:0] doutb;
3636wire [c_address_width-1:0] core_addra,core_addrb;
3637wire [c_width-1:0] core_douta,core_doutb;
3638wire [c_width-1:0] reg_douta,reg_doutb;
3639wire core_we, core_cea, core_ceb;
3640
3641   assign core_addra = addra;
3642   assign core_addrb = addrb;
3643   assign douta = reg_douta;
3644   assign doutb = reg_doutb;
3645   assign core_cea = a_ce & ena;
3646   assign core_ceb = b_ce & enb;
3647   assign core_we = wea & core_cea;
3648
3649generate
3650  if (core_name0 == "dmg_33_vx4_dcb0c4b6adf24a19")
3651    begin:comp0
3652    dmg_33_vx4_dcb0c4b6adf24a19 core_instance0 (
3653      .a(core_addra),
3654      .clk(a_clk),
3655      .d(dina),
3656      .we(core_we),
3657      .dpra(core_addrb),
3658      .spo(core_douta),
3659      .dpo(core_doutb)
3660
3661    );
3662  end
3663 if (latency > 0)
3664   begin:registered_dpram_instA
3665      synth_reg # (c_width, latency)
3666        output_regA (.i(core_douta),
3667                     .ce(core_cea),
3668                     .clr(1'b0),
3669                     .clk(a_clk),
3670                     .o(reg_douta));
3671   end
3672 if (latency > 0)
3673   begin:registered_dpram_instB
3674      synth_reg # (c_width, latency)
3675        output_regB (.i(core_doutb),
3676                     .ce(core_ceb),
3677                     .clr(1'b0),
3678                     .clk(b_clk),
3679                     .o(reg_doutb));
3680   end
3681
3682   if (latency == 0)
3683     begin:nonregistered_ram
3684        assign reg_douta = core_douta;
3685        assign reg_doutb = core_doutb;
3686     end
3687endgenerate
3688endmodule
3689// Generated from Simulink block "hex_out/2wire Count Gen"
3690
3691module x2wire_count_gen_module_02dae4398f (
3692  addr,
3693  ce,
3694  ce_1,
3695  clk_1,
3696  enable31,
3697  enable7,
3698  reset
3699);
3700
3701  input [0:0] ce;
3702  input [0:0] ce_1;
3703  input [0:0] clk_1;
3704  input [0:0] reset;
3705  output [5:0] addr;
3706  output [0:0] enable31;
3707  output [0:0] enable7;
3708
3709  wire [0:0] ce_1_sg_x0;
3710  wire [0:0] clk_1_sg_x0;
3711  wire [5:0] constant1_op_net;
3712  wire [5:0] constant_op_net;
3713  wire [5:0] counter4_op_net_x0;
3714  wire [5:0] delay_q_net;
3715  wire [0:0] logical1_y_net;
3716  wire [0:0] logical_y_net;
3717  wire [0:0] logical_y_net_x1;
3718  wire [0:0] relational1_op_net_x0;
3719  wire [0:0] relational_op_net_x1;
3720  wire [0:0] relational_op_net_x2;
3721  wire [2:0] slice1_y_net;
3722  wire [4:0] slice2_y_net;
3723
3724  assign addr = counter4_op_net_x0;
3725  assign relational_op_net_x1 = ce;
3726  assign ce_1_sg_x0 = ce_1;
3727  assign clk_1_sg_x0 = clk_1;
3728  assign enable31 = relational1_op_net_x0;
3729  assign enable7 = relational_op_net_x2;
3730  assign logical_y_net_x1 = reset;
3731
3732
3733  constant_752327bec1  constant1 (
3734    .ce(1'b0),
3735    .clk(1'b0),
3736    .clr(1'b0),
3737    .op(constant1_op_net)
3738  );
3739
3740  constant_204e9a8bfd  constant_x0 (
3741    .ce(1'b0),
3742    .clk(1'b0),
3743    .clr(1'b0),
3744    .op(constant_op_net)
3745  );
3746
3747  xlcounter_free #(
3748
3749    .core_name0("binary_counter_virtex4_10_0_7f29bec8df1c7606"),
3750    .op_arith(`xlUnsigned),
3751    .op_width(6))
3752  counter4 (
3753    .ce(ce_1_sg_x0),
3754    .clk(clk_1_sg_x0),
3755    .clr(1'b0),
3756    .en(logical1_y_net),
3757    .rst(logical_y_net_x1),
3758    .op(counter4_op_net_x0)
3759  );
3760
3761  xldelay #(
3762
3763    .latency(1),
3764    .reg_retiming(0),
3765    .width(6))
3766  delay (
3767    .ce(ce_1_sg_x0),
3768    .clk(clk_1_sg_x0),
3769    .d(counter4_op_net_x0),
3770    .en(relational_op_net_x1),
3771    .q(delay_q_net)
3772  );
3773
3774  logical_28d385d867  logical (
3775    .ce(1'b0),
3776    .clk(1'b0),
3777    .clr(1'b0),
3778    .d0(relational_op_net_x2),
3779    .d1(relational1_op_net_x0),
3780    .y(logical_y_net)
3781  );
3782
3783  logical_28d385d867  logical1 (
3784    .ce(1'b0),
3785    .clk(1'b0),
3786    .clr(1'b0),
3787    .d0(relational_op_net_x1),
3788    .d1(logical_y_net),
3789    .y(logical1_y_net)
3790  );
3791
3792  relational_440eb07a2f  relational (
3793    .a(slice1_y_net),
3794    .b(constant_op_net),
3795    .ce(ce_1_sg_x0),
3796    .clk(clk_1_sg_x0),
3797    .clr(1'b0),
3798    .en(relational_op_net_x1),
3799    .op(relational_op_net_x2)
3800  );
3801
3802  relational_7e0e56c195  relational1 (
3803    .a(slice2_y_net),
3804    .b(constant1_op_net),
3805    .ce(ce_1_sg_x0),
3806    .clk(clk_1_sg_x0),
3807    .clr(1'b0),
3808    .en(relational_op_net_x1),
3809    .op(relational1_op_net_x0)
3810  );
3811
3812  xlslice #(
3813
3814    .new_lsb(0),
3815    .new_msb(2),
3816    .x_width(6),
3817    .y_width(3))
3818  slice1 (
3819    .x(counter4_op_net_x0),
3820    .y(slice1_y_net)
3821  );
3822
3823  xlslice #(
3824
3825    .new_lsb(0),
3826    .new_msb(4),
3827    .x_width(6),
3828    .y_width(5))
3829  slice2 (
3830    .x(delay_q_net),
3831    .y(slice2_y_net)
3832  );
3833endmodule
3834// Generated from Simulink block "hex_out/ClockEnableGen"
3835
3836module clockenablegen_module_78134ac374 (
3837  ce,
3838  ce_1,
3839  clk_1,
3840  divider,
3841  reset
3842);
3843
3844  input [0:0] ce_1;
3845  input [0:0] clk_1;
3846  input [7:0] divider;
3847  input [0:0] reset;
3848  output [0:0] ce;
3849
3850  wire [9:0] addsub_s_net;
3851  wire [0:0] ce_1_sg_x1;
3852  wire [0:0] clk_1_sg_x1;
3853  wire [9:0] concat_y_net;
3854  wire [1:0] constant15_op_net;
3855  wire [9:0] constant17_op_net;
3856  wire [9:0] counter2_op_net;
3857  wire [7:0] divider_net_x0;
3858  wire [0:0] logical_y_net;
3859  wire [0:0] logical_y_net_x2;
3860  wire [0:0] relational_op_net_x2;
3861
3862  assign ce = relational_op_net_x2;
3863  assign ce_1_sg_x1 = ce_1;
3864  assign clk_1_sg_x1 = clk_1;
3865  assign divider_net_x0 = divider;
3866  assign logical_y_net_x2 = reset;
3867
3868
3869  xladdsubv10_0 #(
3870
3871    .a_arith(`xlUnsigned),
3872    .a_bin_pt(0),
3873    .a_width(10),
3874    .b_arith(`xlUnsigned),
3875    .b_bin_pt(0),
3876    .b_width(10),
3877    .c_has_c_out(0),
3878    .c_latency(0),
3879    .c_output_width(11),
3880    .core_name0("adder_subtracter_virtex4_10_0_80b315fd28a09ef0"),
3881    .extra_registers(0),
3882    .full_s_arith(2),
3883    .full_s_width(11),
3884    .latency(0),
3885    .overflow(1),
3886    .quantization(1),
3887    .s_arith(`xlUnsigned),
3888    .s_bin_pt(0),
3889    .s_width(10))
3890  addsub (
3891    .a(concat_y_net),
3892    .b(constant17_op_net),
3893    .ce(ce_1_sg_x1),
3894    .clk(clk_1_sg_x1),
3895    .clr(1'b0),
3896    .en(1'b1),
3897    .s(addsub_s_net)
3898  );
3899
3900  concat_fb3e05a33e  concat (
3901    .ce(1'b0),
3902    .clk(1'b0),
3903    .clr(1'b0),
3904    .in0(divider_net_x0),
3905    .in1(constant15_op_net),
3906    .y(concat_y_net)
3907  );
3908
3909  constant_9e0724a33a  constant15 (
3910    .ce(1'b0),
3911    .clk(1'b0),
3912    .clr(1'b0),
3913    .op(constant15_op_net)
3914  );
3915
3916  constant_787b59efba  constant17 (
3917    .ce(1'b0),
3918    .clk(1'b0),
3919    .clr(1'b0),
3920    .op(constant17_op_net)
3921  );
3922
3923  xlcounter_free #(
3924
3925    .core_name0("binary_counter_virtex4_10_0_0e77c8b832175d2c"),
3926    .op_arith(`xlUnsigned),
3927    .op_width(10))
3928  counter2 (
3929    .ce(ce_1_sg_x1),
3930    .clk(clk_1_sg_x1),
3931    .clr(1'b0),
3932    .en(1'b1),
3933    .rst(logical_y_net),
3934    .op(counter2_op_net)
3935  );
3936
3937  logical_7970a672aa  logical (
3938    .ce(1'b0),
3939    .clk(1'b0),
3940    .clr(1'b0),
3941    .d0(logical_y_net_x2),
3942    .d1(relational_op_net_x2),
3943    .y(logical_y_net)
3944  );
3945
3946  relational_d74f8dcf86  relational (
3947    .a(addsub_s_net),
3948    .b(counter2_op_net),
3949    .ce(ce_1_sg_x1),
3950    .clk(clk_1_sg_x1),
3951    .clr(1'b0),
3952    .op(relational_op_net_x2)
3953  );
3954endmodule
3955// Generated from Simulink block "hex_out/ClockEnableGen_div4"
3956
3957module clockenablegen_div4_module_fa193c9017 (
3958  ce4,
3959  ce_1,
3960  clk_1,
3961  divider,
3962  reset
3963);
3964
3965  input [0:0] ce_1;
3966  input [0:0] clk_1;
3967  input [7:0] divider;
3968  input [0:0] reset;
3969  output [0:0] ce4;
3970
3971  wire [9:0] addsub_s_net;
3972  wire [0:0] ce_1_sg_x2;
3973  wire [0:0] clk_1_sg_x2;
3974  wire [9:0] concat_y_net;
3975  wire [1:0] constant15_op_net;
3976  wire [9:0] constant17_op_net;
3977  wire [9:0] counter2_op_net;
3978  wire [7:0] divider_net_x1;
3979  wire [0:0] logical_y_net;
3980  wire [0:0] logical_y_net_x3;
3981  wire [0:0] relational_op_net_x0;
3982
3983  assign ce4 = relational_op_net_x0;
3984  assign ce_1_sg_x2 = ce_1;
3985  assign clk_1_sg_x2 = clk_1;
3986  assign divider_net_x1 = divider;
3987  assign logical_y_net_x3 = reset;
3988
3989
3990  xladdsubv10_0 #(
3991
3992    .a_arith(`xlUnsigned),
3993    .a_bin_pt(0),
3994    .a_width(10),
3995    .b_arith(`xlUnsigned),
3996    .b_bin_pt(0),
3997    .b_width(10),
3998    .c_has_c_out(0),
3999    .c_latency(0),
4000    .c_output_width(11),
4001    .core_name0("adder_subtracter_virtex4_10_0_80b315fd28a09ef0"),
4002    .extra_registers(0),
4003    .full_s_arith(2),
4004    .full_s_width(11),
4005    .latency(0),
4006    .overflow(1),
4007    .quantization(1),
4008    .s_arith(`xlUnsigned),
4009    .s_bin_pt(0),
4010    .s_width(10))
4011  addsub (
4012    .a(concat_y_net),
4013    .b(constant17_op_net),
4014    .ce(ce_1_sg_x2),
4015    .clk(clk_1_sg_x2),
4016    .clr(1'b0),
4017    .en(1'b1),
4018    .s(addsub_s_net)
4019  );
4020
4021  concat_ba8a620a74  concat (
4022    .ce(1'b0),
4023    .clk(1'b0),
4024    .clr(1'b0),
4025    .in0(constant15_op_net),
4026    .in1(divider_net_x1),
4027    .y(concat_y_net)
4028  );
4029
4030  constant_9e0724a33a  constant15 (
4031    .ce(1'b0),
4032    .clk(1'b0),
4033    .clr(1'b0),
4034    .op(constant15_op_net)
4035  );
4036
4037  constant_787b59efba  constant17 (
4038    .ce(1'b0),
4039    .clk(1'b0),
4040    .clr(1'b0),
4041    .op(constant17_op_net)
4042  );
4043
4044  xlcounter_free #(
4045
4046    .core_name0("binary_counter_virtex4_10_0_0e77c8b832175d2c"),
4047    .op_arith(`xlUnsigned),
4048    .op_width(10))
4049  counter2 (
4050    .ce(ce_1_sg_x2),
4051    .clk(clk_1_sg_x2),
4052    .clr(1'b0),
4053    .en(1'b1),
4054    .rst(logical_y_net),
4055    .op(counter2_op_net)
4056  );
4057
4058  logical_7970a672aa  logical (
4059    .ce(1'b0),
4060    .clk(1'b0),
4061    .clr(1'b0),
4062    .d0(logical_y_net_x3),
4063    .d1(relational_op_net_x0),
4064    .y(logical_y_net)
4065  );
4066
4067  relational_d74f8dcf86  relational (
4068    .a(addsub_s_net),
4069    .b(counter2_op_net),
4070    .ce(ce_1_sg_x2),
4071    .clk(clk_1_sg_x2),
4072    .clr(1'b0),
4073    .op(relational_op_net_x0)
4074  );
4075endmodule
4076// Generated from Simulink block "hex_out/ConfigDataMuxCtrl"
4077
4078module configdatamuxctrl_module_dd079a15a5 (
4079  ce_1,
4080  clk_1,
4081  configrising,
4082  enable31falling,
4083  mux_sel
4084);
4085
4086  input [0:0] ce_1;
4087  input [0:0] clk_1;
4088  input [0:0] configrising;
4089  input [0:0] enable31falling;
4090  output [0:0] mux_sel;
4091
4092  wire [0:0] ce_1_sg_x3;
4093  wire [0:0] clk_1_sg_x3;
4094  wire [0:0] delay1_q_net;
4095  wire [0:0] delay1_q_net_x1;
4096  wire [0:0] inverter1_op_net;
4097  wire [0:0] inverter_op_net;
4098  wire [0:0] logical1_y_net;
4099  wire [0:0] logical2_y_net_x0;
4100  wire [0:0] logical_y_net;
4101  wire [0:0] logical_y_net_x1;
4102  wire [0:0] register1_q_net;
4103  wire [0:0] register2_q_net;
4104  wire [0:0] register3_q_net;
4105  wire [0:0] register_q_net;
4106
4107  assign ce_1_sg_x3 = ce_1;
4108  assign clk_1_sg_x3 = clk_1;
4109  assign delay1_q_net_x1 = configrising;
4110  assign logical_y_net_x1 = enable31falling;
4111  assign mux_sel = logical2_y_net_x0;
4112
4113
4114  xldelay #(
4115
4116    .latency(1),
4117    .reg_retiming(0),
4118    .width(1))
4119  delay1 (
4120    .ce(ce_1_sg_x3),
4121    .clk(clk_1_sg_x3),
4122    .d(delay1_q_net_x1),
4123    .en(1'b1),
4124    .q(delay1_q_net)
4125  );
4126
4127  inverter_33a63b558a  inverter (
4128    .ce(ce_1_sg_x3),
4129    .clk(clk_1_sg_x3),
4130    .clr(1'b0),
4131    .ip(register2_q_net),
4132    .op(inverter_op_net)
4133  );
4134
4135  inverter_33a63b558a  inverter1 (
4136    .ce(ce_1_sg_x3),
4137    .clk(clk_1_sg_x3),
4138    .clr(1'b0),
4139    .ip(register1_q_net),
4140    .op(inverter1_op_net)
4141  );
4142
4143  logical_818bd6d54b  logical (
4144    .ce(1'b0),
4145    .clk(1'b0),
4146    .clr(1'b0),
4147    .d0(inverter_op_net),
4148    .d1(register1_q_net),
4149    .d2(register_q_net),
4150    .d3(register3_q_net),
4151    .y(logical_y_net)
4152  );
4153
4154  logical_818bd6d54b  logical1 (
4155    .ce(1'b0),
4156    .clk(1'b0),
4157    .clr(1'b0),
4158    .d0(inverter_op_net),
4159    .d1(inverter1_op_net),
4160    .d2(register_q_net),
4161    .d3(register3_q_net),
4162    .y(logical1_y_net)
4163  );
4164
4165  logical_7970a672aa  logical2 (
4166    .ce(1'b0),
4167    .clk(1'b0),
4168    .clr(1'b0),
4169    .d0(logical_y_net),
4170    .d1(logical1_y_net),
4171    .y(logical2_y_net_x0)
4172  );
4173
4174  xlregister #(
4175
4176    .d_width(1),
4177    .init_value(1'b0))
4178  register1 (
4179    .ce(ce_1_sg_x3),
4180    .clk(clk_1_sg_x3),
4181    .d(register_q_net),
4182    .en(logical_y_net_x1),
4183    .rst(delay1_q_net_x1),
4184    .q(register1_q_net)
4185  );
4186
4187  xlregister #(
4188
4189    .d_width(1),
4190    .init_value(1'b0))
4191  register2 (
4192    .ce(ce_1_sg_x3),
4193    .clk(clk_1_sg_x3),
4194    .d(register1_q_net),
4195    .en(logical_y_net_x1),
4196    .rst(delay1_q_net_x1),
4197    .q(register2_q_net)
4198  );
4199
4200  xlregister #(
4201
4202    .d_width(1),
4203    .init_value(1'b0))
4204  register3 (
4205    .ce(ce_1_sg_x3),
4206    .clk(clk_1_sg_x3),
4207    .d(delay1_q_net),
4208    .en(delay1_q_net),
4209    .rst(delay1_q_net_x1),
4210    .q(register3_q_net)
4211  );
4212
4213  xlregister #(
4214
4215    .d_width(1),
4216    .init_value(1'b0))
4217  register_x0 (
4218    .ce(ce_1_sg_x3),
4219    .clk(clk_1_sg_x3),
4220    .d(logical_y_net_x1),
4221    .en(logical_y_net_x1),
4222    .rst(delay1_q_net_x1),
4223    .q(register_q_net)
4224  );
4225endmodule
4226// Generated from Simulink block "hex_out/SCLGenerate"
4227
4228module sclgenerate_module_463ec6aa7d (
4229  ce,
4230  ce4,
4231  ce_1,
4232  clk_1,
4233  enable31,
4234  reset_rising,
4235  scl
4236);
4237
4238  input [0:0] ce;
4239  input [0:0] ce4;
4240  input [0:0] ce_1;
4241  input [0:0] clk_1;
4242  input [0:0] enable31;
4243  input [0:0] reset_rising;
4244  output [0:0] scl;
4245
4246  wire [0:0] ce_1_sg_x4;
4247  wire [0:0] clk_1_sg_x4;
4248  wire [0:0] constant2_op_net;
4249  wire [1:0] counter1_op_net;
4250  wire [0:0] delay2_q_net;
4251  wire [0:0] delay3_q_net;
4252  wire [0:0] logical_y_net_x4;
4253  wire [0:0] mux2_y_net_x0;
4254  wire [0:0] relational1_op_net_x1;
4255  wire [0:0] relational_op_net_x3;
4256  wire [0:0] relational_op_net_x4;
4257  wire [0:0] slice1_y_net;
4258
4259  assign relational_op_net_x3 = ce;
4260  assign relational_op_net_x4 = ce4;
4261  assign ce_1_sg_x4 = ce_1;
4262  assign clk_1_sg_x4 = clk_1;
4263  assign relational1_op_net_x1 = enable31;
4264  assign logical_y_net_x4 = reset_rising;
4265  assign scl = mux2_y_net_x0;
4266
4267
4268  constant_9cf45430cd  constant2 (
4269    .ce(1'b0),
4270    .clk(1'b0),
4271    .clr(1'b0),
4272    .op(constant2_op_net)
4273  );
4274
4275  xlcounter_free #(
4276
4277    .core_name0("binary_counter_virtex4_10_0_407917162894eacc"),
4278    .op_arith(`xlUnsigned),
4279    .op_width(2))
4280  counter1 (
4281    .ce(ce_1_sg_x4),
4282    .clk(clk_1_sg_x4),
4283    .clr(1'b0),
4284    .en(relational_op_net_x4),
4285    .rst(logical_y_net_x4),
4286    .op(counter1_op_net)
4287  );
4288
4289  xldelay #(
4290
4291    .latency(4),
4292    .reg_retiming(0),
4293    .width(1))
4294  delay2 (
4295    .ce(ce_1_sg_x4),
4296    .clk(clk_1_sg_x4),
4297    .d(slice1_y_net),
4298    .en(relational_op_net_x4),
4299    .q(delay2_q_net)
4300  );
4301
4302  xldelay #(
4303
4304    .latency(1),
4305    .reg_retiming(0),
4306    .width(1))
4307  delay3 (
4308    .ce(ce_1_sg_x4),
4309    .clk(clk_1_sg_x4),
4310    .d(relational1_op_net_x1),
4311    .en(relational_op_net_x3),
4312    .q(delay3_q_net)
4313  );
4314
4315  mux_485ea02169  mux2 (
4316    .ce(1'b0),
4317    .clk(1'b0),
4318    .clr(1'b0),
4319    .d0(constant2_op_net),
4320    .d1(delay2_q_net),
4321    .sel(delay3_q_net),
4322    .y(mux2_y_net_x0)
4323  );
4324
4325  xlslice #(
4326
4327    .new_lsb(1),
4328    .new_msb(1),
4329    .x_width(2),
4330    .y_width(1))
4331  slice1 (
4332    .x(counter1_op_net),
4333    .y(slice1_y_net)
4334  );
4335endmodule
4336// Generated from Simulink block "hex_out/SDAGenerate/inputdata_write"
4337
4338module inputdata_write_module_008cea4600 (
4339  address0,
4340  address1,
4341  ce_1,
4342  ce_8,
4343  clk_1,
4344  clk_8,
4345  config_writedata,
4346  data_writedata,
4347  hex_l,
4348  hex_m,
4349  hex_r,
4350  led8,
4351  mux_select
4352);
4353
4354  input [7:0] address0;
4355  input [7:0] address1;
4356  input [0:0] ce_1;
4357  input [0:0] ce_8;
4358  input [0:0] clk_1;
4359  input [0:0] clk_8;
4360  input [7:0] hex_l;
4361  input [7:0] hex_m;
4362  input [7:0] hex_r;
4363  input [7:0] led8;
4364  input [2:0] mux_select;
4365  output [0:0] config_writedata;
4366  output [0:0] data_writedata;
4367
4368  wire [7:0] address0_net_x0;
4369  wire [7:0] address1_net_x0;
4370  wire [0:0] ce_1_sg_x5;
4371  wire [0:0] ce_8_sg_x0;
4372  wire [0:0] clk_1_sg_x5;
4373  wire [0:0] clk_8_sg_x0;
4374  wire [7:0] constant10_op_net;
4375  wire [7:0] constant12_op_net;
4376  wire [7:0] constant13_op_net;
4377  wire [7:0] constant4_op_net;
4378  wire [7:0] constant5_op_net;
4379  wire [7:0] constant6_op_net;
4380  wire [7:0] constant7_op_net;
4381  wire [7:0] constant9_op_net;
4382  wire [7:0] hex_l_net_x0;
4383  wire [7:0] hex_m_net_x0;
4384  wire [7:0] hex_r_net_x0;
4385  wire [7:0] led8_net_x0;
4386  wire [7:0] mux3_y_net;
4387  wire [7:0] mux_y_net;
4388  wire [0:0] parallel_to_serial1_dout_net_x0;
4389  wire [0:0] parallel_to_serial2_dout_net_x0;
4390  wire [2:0] slice_y_net_x0;
4391
4392  assign address0_net_x0 = address0;
4393  assign address1_net_x0 = address1;
4394  assign ce_1_sg_x5 = ce_1;
4395  assign ce_8_sg_x0 = ce_8;
4396  assign clk_1_sg_x5 = clk_1;
4397  assign clk_8_sg_x0 = clk_8;
4398  assign config_writedata = parallel_to_serial2_dout_net_x0;
4399  assign data_writedata = parallel_to_serial1_dout_net_x0;
4400  assign hex_l_net_x0 = hex_l;
4401  assign hex_m_net_x0 = hex_m;
4402  assign hex_r_net_x0 = hex_r;
4403  assign led8_net_x0 = led8;
4404  assign slice_y_net_x0 = mux_select;
4405
4406
4407  constant_4ffad13294  constant10 (
4408    .ce(1'b0),
4409    .clk(1'b0),
4410    .clr(1'b0),
4411    .op(constant10_op_net)
4412  );
4413
4414  constant_11c05a5fb4  constant12 (
4415    .ce(1'b0),
4416    .clk(1'b0),
4417    .clr(1'b0),
4418    .op(constant12_op_net)
4419  );
4420
4421  constant_11c05a5fb4  constant13 (
4422    .ce(1'b0),
4423    .clk(1'b0),
4424    .clr(1'b0),
4425    .op(constant13_op_net)
4426  );
4427
4428  constant_11c05a5fb4  constant4 (
4429    .ce(1'b0),
4430    .clk(1'b0),
4431    .clr(1'b0),
4432    .op(constant4_op_net)
4433  );
4434
4435  constant_67d0b5242e  constant5 (
4436    .ce(1'b0),
4437    .clk(1'b0),
4438    .clr(1'b0),
4439    .op(constant5_op_net)
4440  );
4441
4442  constant_67d0b5242e  constant6 (
4443    .ce(1'b0),
4444    .clk(1'b0),
4445    .clr(1'b0),
4446    .op(constant6_op_net)
4447  );
4448
4449  constant_11c05a5fb4  constant7 (
4450    .ce(1'b0),
4451    .clk(1'b0),
4452    .clr(1'b0),
4453    .op(constant7_op_net)
4454  );
4455
4456  constant_4ffad13294  constant9 (
4457    .ce(1'b0),
4458    .clk(1'b0),
4459    .clr(1'b0),
4460    .op(constant9_op_net)
4461  );
4462
4463  mux_f80a0abc7d  mux (
4464    .ce(1'b0),
4465    .clk(1'b0),
4466    .clr(1'b0),
4467    .d0(address0_net_x0),
4468    .d1(constant5_op_net),
4469    .d2(hex_l_net_x0),
4470    .d3(hex_m_net_x0),
4471    .d4(address1_net_x0),
4472    .d5(constant6_op_net),
4473    .d6(hex_r_net_x0),
4474    .d7(led8_net_x0),
4475    .sel(slice_y_net_x0),
4476    .y(mux_y_net)
4477  );
4478
4479  mux_f80a0abc7d  mux3 (
4480    .ce(1'b0),
4481    .clk(1'b0),
4482    .clr(1'b0),
4483    .d0(address0_net_x0),
4484    .d1(constant9_op_net),
4485    .d2(constant4_op_net),
4486    .d3(constant7_op_net),
4487    .d4(address1_net_x0),
4488    .d5(constant10_op_net),
4489    .d6(constant12_op_net),
4490    .d7(constant13_op_net),
4491    .sel(slice_y_net_x0),
4492    .y(mux3_y_net)
4493  );
4494
4495  xlp2s #(
4496
4497    .din_arith(`xlUnsigned),
4498    .din_bin_pt(0),
4499    .din_width(8),
4500    .dout_arith(`xlUnsigned),
4501    .dout_bin_pt(0),
4502    .dout_width(1),
4503    .latency(0),
4504    .lsb_first(0),
4505    .num_outputs(8))
4506  parallel_to_serial1 (
4507    .dest_ce(ce_1_sg_x5),
4508    .dest_clk(clk_1_sg_x5),
4509    .dest_clr(1'b0),
4510    .din(mux_y_net),
4511    .en(1'b1),
4512    .rst(1'b0),
4513    .src_ce(ce_8_sg_x0),
4514    .src_clk(clk_8_sg_x0),
4515    .src_clr(1'b0),
4516    .dout(parallel_to_serial1_dout_net_x0)
4517  );
4518
4519  xlp2s #(
4520
4521    .din_arith(`xlUnsigned),
4522    .din_bin_pt(0),
4523    .din_width(8),
4524    .dout_arith(`xlUnsigned),
4525    .dout_bin_pt(0),
4526    .dout_width(1),
4527    .latency(0),
4528    .lsb_first(0),
4529    .num_outputs(8))
4530  parallel_to_serial2 (
4531    .dest_ce(ce_1_sg_x5),
4532    .dest_clk(clk_1_sg_x5),
4533    .dest_clr(1'b0),
4534    .din(mux3_y_net),
4535    .en(1'b1),
4536    .rst(1'b0),
4537    .src_ce(ce_8_sg_x0),
4538    .src_clk(clk_8_sg_x0),
4539    .src_clr(1'b0),
4540    .dout(parallel_to_serial2_dout_net_x0)
4541  );
4542endmodule
4543// Generated from Simulink block "hex_out/SDAGenerate"
4544
4545module sdagenerate_module_bc7d2cf62c (
4546  addrb,
4547  address0,
4548  address1,
4549  ce,
4550  ce4,
4551  ce_1,
4552  ce_8,
4553  clk_1,
4554  clk_8,
4555  enable7,
4556  hex_l,
4557  hex_m,
4558  hex_r,
4559  led8,
4560  outselect,
4561  sda
4562);
4563
4564  input [5:0] addrb;
4565  input [7:0] address0;
4566  input [7:0] address1;
4567  input [0:0] ce;
4568  input [0:0] ce4;
4569  input [0:0] ce_1;
4570  input [0:0] ce_8;
4571  input [0:0] clk_1;
4572  input [0:0] clk_8;
4573  input [0:0] enable7;
4574  input [7:0] hex_l;
4575  input [7:0] hex_m;
4576  input [7:0] hex_r;
4577  input [7:0] led8;
4578  input [0:0] outselect;
4579  output [0:0] sda;
4580
4581  wire [7:0] address0_net_x1;
4582  wire [7:0] address1_net_x1;
4583  wire [0:0] ce_1_sg_x6;
4584  wire [0:0] ce_8_sg_x1;
4585  wire [0:0] clk_1_sg_x6;
4586  wire [0:0] clk_8_sg_x1;
4587  wire [0:0] config_doutb_net;
4588  wire [0:0] constant11_op_net;
4589  wire [0:0] constant14_op_net;
4590  wire [0:0] constant1_op_net;
4591  wire [0:0] constant8_op_net;
4592  wire [5:0] counter3_op_net;
4593  wire [5:0] counter4_op_net_x1;
4594  wire [0:0] data_doutb_net;
4595  wire [0:0] delay1_q_net_x0;
4596  wire [0:0] delay4_q_net_x0;
4597  wire [5:0] delay_q_net;
4598  wire [5:0] down_sample_q_net;
4599  wire [7:0] hex_l_net_x1;
4600  wire [7:0] hex_m_net_x1;
4601  wire [7:0] hex_r_net_x1;
4602  wire [7:0] led8_net_x1;
4603  wire [0:0] logical2_y_net_x1;
4604  wire [0:0] mux1_y_net;
4605  wire [0:0] mux4_y_net;
4606  wire [0:0] mux5_y_net;
4607  wire [0:0] parallel_to_serial1_dout_net_x0;
4608  wire [0:0] parallel_to_serial2_dout_net_x0;
4609  wire [0:0] relational_op_net_x5;
4610  wire [0:0] relational_op_net_x6;
4611  wire [2:0] slice_y_net_x0;
4612
4613  assign counter4_op_net_x1 = addrb;
4614  assign address0_net_x1 = address0;
4615  assign address1_net_x1 = address1;
4616  assign relational_op_net_x5 = ce;
4617  assign relational_op_net_x6 = ce4;
4618  assign ce_1_sg_x6 = ce_1;
4619  assign ce_8_sg_x1 = ce_8;
4620  assign clk_1_sg_x6 = clk_1;
4621  assign clk_8_sg_x1 = clk_8;
4622  assign delay4_q_net_x0 = enable7;
4623  assign hex_l_net_x1 = hex_l;
4624  assign hex_m_net_x1 = hex_m;
4625  assign hex_r_net_x1 = hex_r;
4626  assign led8_net_x1 = led8;
4627  assign logical2_y_net_x1 = outselect;
4628  assign sda = delay1_q_net_x0;
4629
4630
4631  xldpram_dist #(
4632
4633    .addr_width(6),
4634    .c_address_width(6),
4635    .c_width(1),
4636    .core_name0("dmg_33_vx4_dcb0c4b6adf24a19"),
4637    .latency(1))
4638  config_x0 (
4639    .a_ce(ce_1_sg_x6),
4640    .a_clk(clk_1_sg_x6),
4641    .addra(delay_q_net),
4642    .addrb(counter4_op_net_x1),
4643    .b_ce(ce_1_sg_x6),
4644    .b_clk(clk_1_sg_x6),
4645    .dina(parallel_to_serial2_dout_net_x0),
4646    .ena(1'b1),
4647    .enb(relational_op_net_x5),
4648    .wea(constant11_op_net),
4649    .doutb(config_doutb_net)
4650  );
4651
4652  constant_9cf45430cd  constant1 (
4653    .ce(1'b0),
4654    .clk(1'b0),
4655    .clr(1'b0),
4656    .op(constant1_op_net)
4657  );
4658
4659  constant_5e90e4a8ec  constant11 (
4660    .ce(1'b0),
4661    .clk(1'b0),
4662    .clr(1'b0),
4663    .op(constant11_op_net)
4664  );
4665
4666  constant_9cf45430cd  constant14 (
4667    .ce(1'b0),
4668    .clk(1'b0),
4669    .clr(1'b0),
4670    .op(constant14_op_net)
4671  );
4672
4673  constant_5e90e4a8ec  constant8 (
4674    .ce(1'b0),
4675    .clk(1'b0),
4676    .clr(1'b0),
4677    .op(constant8_op_net)
4678  );
4679
4680  xlcounter_free #(
4681
4682    .core_name0("binary_counter_virtex4_10_0_7f29bec8df1c7606"),
4683    .op_arith(`xlUnsigned),
4684    .op_width(6))
4685  counter3 (
4686    .ce(ce_1_sg_x6),
4687    .clk(clk_1_sg_x6),
4688    .clr(1'b0),
4689    .en(1'b1),
4690    .rst(1'b0),
4691    .op(counter3_op_net)
4692  );
4693
4694  xldpram_dist #(
4695
4696    .addr_width(6),
4697    .c_address_width(6),
4698    .c_width(1),
4699    .core_name0("dmg_33_vx4_dcb0c4b6adf24a19"),
4700    .latency(1))
4701  data (
4702    .a_ce(ce_1_sg_x6),
4703    .a_clk(clk_1_sg_x6),
4704    .addra(delay_q_net),
4705    .addrb(counter4_op_net_x1),
4706    .b_ce(ce_1_sg_x6),
4707    .b_clk(clk_1_sg_x6),
4708    .dina(parallel_to_serial1_dout_net_x0),
4709    .ena(1'b1),
4710    .enb(relational_op_net_x5),
4711    .wea(constant8_op_net),
4712    .doutb(data_doutb_net)
4713  );
4714
4715  xldelay #(
4716
4717    .latency(8),
4718    .reg_retiming(0),
4719    .width(6))
4720  delay (
4721    .ce(ce_1_sg_x6),
4722    .clk(clk_1_sg_x6),
4723    .d(counter3_op_net),
4724    .en(1'b1),
4725    .q(delay_q_net)
4726  );
4727
4728  xldelay #(
4729
4730    .latency(1),
4731    .reg_retiming(0),
4732    .width(1))
4733  delay1 (
4734    .ce(ce_1_sg_x6),
4735    .clk(clk_1_sg_x6),
4736    .d(mux5_y_net),
4737    .en(relational_op_net_x6),
4738    .q(delay1_q_net_x0)
4739  );
4740
4741  xldsamp #(
4742
4743    .d_arith(`xlUnsigned),
4744    .d_bin_pt(0),
4745    .d_width(6),
4746    .ds_ratio(8),
4747    .latency(1),
4748    .phase(7),
4749    .q_arith(`xlUnsigned),
4750    .q_bin_pt(0),
4751    .q_width(6))
4752  down_sample (
4753    .d(counter3_op_net),
4754    .dest_ce(ce_8_sg_x1),
4755    .dest_clk(clk_8_sg_x1),
4756    .dest_clr(1'b0),
4757    .en(1'b1),
4758    .src_ce(ce_1_sg_x6),
4759    .src_clk(clk_1_sg_x6),
4760    .src_clr(1'b0),
4761    .q(down_sample_q_net)
4762  );
4763
4764  inputdata_write_module_008cea4600  inputdata_write_008cea4600 (
4765    .address0(address0_net_x1),
4766    .address1(address1_net_x1),
4767    .ce_1(ce_1_sg_x6),
4768    .ce_8(ce_8_sg_x1),
4769    .clk_1(clk_1_sg_x6),
4770    .clk_8(clk_8_sg_x1),
4771    .hex_l(hex_l_net_x1),
4772    .hex_m(hex_m_net_x1),
4773    .hex_r(hex_r_net_x1),
4774    .led8(led8_net_x1),
4775    .mux_select(slice_y_net_x0),
4776    .config_writedata(parallel_to_serial2_dout_net_x0),
4777    .data_writedata(parallel_to_serial1_dout_net_x0)
4778  );
4779
4780  mux_485ea02169  mux1 (
4781    .ce(1'b0),
4782    .clk(1'b0),
4783    .clr(1'b0),
4784    .d0(constant1_op_net),
4785    .d1(data_doutb_net),
4786    .sel(delay4_q_net_x0),
4787    .y(mux1_y_net)
4788  );
4789
4790  mux_485ea02169  mux4 (
4791    .ce(1'b0),
4792    .clk(1'b0),
4793    .clr(1'b0),
4794    .d0(constant14_op_net),
4795    .d1(config_doutb_net),
4796    .sel(delay4_q_net_x0),
4797    .y(mux4_y_net)
4798  );
4799
4800  mux_485ea02169  mux5 (
4801    .ce(1'b0),
4802    .clk(1'b0),
4803    .clr(1'b0),
4804    .d0(mux1_y_net),
4805    .d1(mux4_y_net),
4806    .sel(logical2_y_net_x1),
4807    .y(mux5_y_net)
4808  );
4809
4810  xlslice #(
4811
4812    .new_lsb(3),
4813    .new_msb(5),
4814    .x_width(6),
4815    .y_width(3))
4816  slice (
4817    .x(down_sample_q_net),
4818    .y(slice_y_net_x0)
4819  );
4820endmodule
4821// Generated from Simulink block "hex_out/fallingedge"
4822
4823module fallingedge_module_0bebb75311 (
4824  ce_1,
4825  clk_1,
4826  edge_x0,
4827  in_x0
4828);
4829
4830  input [0:0] ce_1;
4831  input [0:0] clk_1;
4832  input [0:0] in_x0;
4833  output [0:0] edge_x0;
4834
4835  wire [0:0] ce_1_sg_x7;
4836  wire [0:0] clk_1_sg_x7;
4837  wire [0:0] delay4_q_net;
4838  wire [0:0] inverter_op_net;
4839  wire [0:0] logical_y_net_x2;
4840  wire [0:0] relational1_op_net_x2;
4841
4842  assign ce_1_sg_x7 = ce_1;
4843  assign clk_1_sg_x7 = clk_1;
4844  assign edge_x0 = logical_y_net_x2;
4845  assign relational1_op_net_x2 = in_x0;
4846
4847
4848  xldelay #(
4849
4850    .latency(1),
4851    .reg_retiming(0),
4852    .width(1))
4853  delay4 (
4854    .ce(ce_1_sg_x7),
4855    .clk(clk_1_sg_x7),
4856    .d(relational1_op_net_x2),
4857    .en(1'b1),
4858    .q(delay4_q_net)
4859  );
4860
4861  inverter_33a63b558a  inverter (
4862    .ce(ce_1_sg_x7),
4863    .clk(clk_1_sg_x7),
4864    .clr(1'b0),
4865    .ip(relational1_op_net_x2),
4866    .op(inverter_op_net)
4867  );
4868
4869  logical_28d385d867  logical (
4870    .ce(1'b0),
4871    .clk(1'b0),
4872    .clr(1'b0),
4873    .d0(inverter_op_net),
4874    .d1(delay4_q_net),
4875    .y(logical_y_net_x2)
4876  );
4877endmodule
4878// Generated from Simulink block "hex_out/risingedge"
4879
4880module risingedge_module_530dab4a3f (
4881  ce_1,
4882  clk_1,
4883  edge_x0,
4884  in_x0
4885);
4886
4887  input [0:0] ce_1;
4888  input [0:0] clk_1;
4889  input [0:0] in_x0;
4890  output [0:0] edge_x0;
4891
4892  wire [0:0] ce_1_sg_x9;
4893  wire [0:0] clk_1_sg_x9;
4894  wire [0:0] delay4_q_net;
4895  wire [0:0] inverter_op_net;
4896  wire [0:0] logical_y_net_x5;
4897  wire [0:0] reset_net_x1;
4898
4899  assign ce_1_sg_x9 = ce_1;
4900  assign clk_1_sg_x9 = clk_1;
4901  assign edge_x0 = logical_y_net_x5;
4902  assign reset_net_x1 = in_x0;
4903
4904
4905  xldelay #(
4906
4907    .latency(1),
4908    .reg_retiming(0),
4909    .width(1))
4910  delay4 (
4911    .ce(ce_1_sg_x9),
4912    .clk(clk_1_sg_x9),
4913    .d(inverter_op_net),
4914    .en(1'b1),
4915    .q(delay4_q_net)
4916  );
4917
4918  inverter_33a63b558a  inverter (
4919    .ce(ce_1_sg_x9),
4920    .clk(clk_1_sg_x9),
4921    .clr(1'b0),
4922    .ip(reset_net_x1),
4923    .op(inverter_op_net)
4924  );
4925
4926  logical_28d385d867  logical (
4927    .ce(1'b0),
4928    .clk(1'b0),
4929    .clr(1'b0),
4930    .d0(reset_net_x1),
4931    .d1(delay4_q_net),
4932    .y(logical_y_net_x5)
4933  );
4934endmodule
4935// Generated from Simulink block "hex_out"
4936
4937(* core_generation_info = "hex_out,sysgen_core_10_1_3_1386,{total_blocks=164,xilinx_adder_subtractor_block=2,xilinx_arithmetic_relational_operator_block=4,xilinx_bit_slice_extractor_block=4,xilinx_bus_concatenator_block=2,xilinx_bus_multiplexer_block=6,xilinx_constant_block_block=19,xilinx_counter_block=5,xilinx_delay_block=11,xilinx_down_sampler_block=1,xilinx_dual_port_random_access_memory_block=2,xilinx_gateway_in_block=8,xilinx_gateway_out_block=2,xilinx_inverter_block=5,xilinx_logical_block_block=10,xilinx_parallel_to_serial_converter_block=2,xilinx_register_block=4,xilinx_resource_estimator_block=1,xilinx_system_generator_block=1,}" *)
4938module hex_out (
4939  address0,
4940  address1,
4941  ce_1,
4942  ce_8,
4943  clk_1,
4944  clk_8,
4945  divider,
4946  hex_l,
4947  hex_m,
4948  hex_r,
4949  led8,
4950  reset,
4951  scl,
4952  sda
4953);
4954
4955  input [7:0] address0;
4956  input [7:0] address1;
4957  input [0:0] ce_1;
4958  input [0:0] ce_8;
4959  input [0:0] clk_1;
4960  input [0:0] clk_8;
4961  input [7:0] divider;
4962  input [7:0] hex_l;
4963  input [7:0] hex_m;
4964  input [7:0] hex_r;
4965  input [7:0] led8;
4966  input [0:0] reset;
4967  output [0:0] scl;
4968  output [0:0] sda;
4969
4970  wire [7:0] address0_net;
4971  wire [7:0] address1_net;
4972  wire [0:0] ce_1_sg_x10;
4973  wire [0:0] ce_8_sg_x2;
4974  wire [0:0] clk_1_sg_x10;
4975  wire [0:0] clk_8_sg_x2;
4976  wire [5:0] counter4_op_net_x1;
4977  wire [0:0] delay1_q_net_x1;
4978  wire [0:0] delay4_q_net_x0;
4979  wire [7:0] divider_net;
4980  wire [7:0] hex_l_net;
4981  wire [7:0] hex_m_net;
4982  wire [7:0] hex_r_net;
4983  wire [7:0] led8_net;
4984  wire [0:0] logical2_y_net_x1;
4985  wire [0:0] logical_y_net_x0;
4986  wire [0:0] logical_y_net_x2;
4987  wire [0:0] logical_y_net_x5;
4988  wire [0:0] relational1_op_net_x2;
4989  wire [0:0] relational_op_net_x2;
4990  wire [0:0] relational_op_net_x5;
4991  wire [0:0] relational_op_net_x6;
4992  wire [0:0] reset_net;
4993  wire [0:0] scl_net;
4994  wire [0:0] sda_net;
4995
4996  assign address0_net = address0;
4997  assign address1_net = address1;
4998  assign ce_1_sg_x10 = ce_1;
4999  assign ce_8_sg_x2 = ce_8;
5000  assign clk_1_sg_x10 = clk_1;
5001  assign clk_8_sg_x2 = clk_8;
5002  assign divider_net = divider;
5003  assign hex_l_net = hex_l;
5004  assign hex_m_net = hex_m;
5005  assign hex_r_net = hex_r;
5006  assign led8_net = led8;
5007  assign reset_net = reset;
5008  assign scl = scl_net;
5009  assign sda = sda_net;
5010
5011
5012  clockenablegen_module_78134ac374  clockenablegen_78134ac374 (
5013    .ce_1(ce_1_sg_x10),
5014    .clk_1(clk_1_sg_x10),
5015    .divider(divider_net),
5016    .reset(logical_y_net_x5),
5017    .ce(relational_op_net_x5)
5018  );
5019
5020  clockenablegen_div4_module_fa193c9017  clockenablegen_div4_fa193c9017 (
5021    .ce_1(ce_1_sg_x10),
5022    .clk_1(clk_1_sg_x10),
5023    .divider(divider_net),
5024    .reset(logical_y_net_x5),
5025    .ce4(relational_op_net_x6)
5026  );
5027
5028  configdatamuxctrl_module_dd079a15a5  configdatamuxctrl_dd079a15a5 (
5029    .ce_1(ce_1_sg_x10),
5030    .clk_1(clk_1_sg_x10),
5031    .configrising(delay1_q_net_x1),
5032    .enable31falling(logical_y_net_x2),
5033    .mux_sel(logical2_y_net_x1)
5034  );
5035
5036  xldelay #(
5037
5038    .latency(80),
5039    .reg_retiming(0),
5040    .width(1))
5041  delay1 (
5042    .ce(ce_1_sg_x10),
5043    .clk(clk_1_sg_x10),
5044    .d(logical_y_net_x0),
5045    .en(1'b1),
5046    .q(delay1_q_net_x1)
5047  );
5048
5049  xldelay #(
5050
5051    .latency(1),
5052    .reg_retiming(0),
5053    .width(1))
5054  delay4 (
5055    .ce(ce_1_sg_x10),
5056    .clk(clk_1_sg_x10),
5057    .d(relational_op_net_x2),
5058    .en(relational_op_net_x5),
5059    .q(delay4_q_net_x0)
5060  );
5061
5062  fallingedge_module_0bebb75311  fallingedge1_caf59c31b2 (
5063    .ce_1(ce_1_sg_x10),
5064    .clk_1(clk_1_sg_x10),
5065    .in_x0(reset_net),
5066    .edge_x0(logical_y_net_x0)
5067  );
5068
5069  fallingedge_module_0bebb75311  fallingedge_0bebb75311 (
5070    .ce_1(ce_1_sg_x10),
5071    .clk_1(clk_1_sg_x10),
5072    .in_x0(relational1_op_net_x2),
5073    .edge_x0(logical_y_net_x2)
5074  );
5075
5076  risingedge_module_530dab4a3f  risingedge_530dab4a3f (
5077    .ce_1(ce_1_sg_x10),
5078    .clk_1(clk_1_sg_x10),
5079    .in_x0(reset_net),
5080    .edge_x0(logical_y_net_x5)
5081  );
5082
5083  sclgenerate_module_463ec6aa7d  sclgenerate_463ec6aa7d (
5084    .ce(relational_op_net_x5),
5085    .ce4(relational_op_net_x6),
5086    .ce_1(ce_1_sg_x10),
5087    .clk_1(clk_1_sg_x10),
5088    .enable31(relational1_op_net_x2),
5089    .reset_rising(logical_y_net_x5),
5090    .scl(scl_net)
5091  );
5092
5093  sdagenerate_module_bc7d2cf62c  sdagenerate_bc7d2cf62c (
5094    .addrb(counter4_op_net_x1),
5095    .address0(address0_net),
5096    .address1(address1_net),
5097    .ce(relational_op_net_x5),
5098    .ce4(relational_op_net_x6),
5099    .ce_1(ce_1_sg_x10),
5100    .ce_8(ce_8_sg_x2),
5101    .clk_1(clk_1_sg_x10),
5102    .clk_8(clk_8_sg_x2),
5103    .enable7(delay4_q_net_x0),
5104    .hex_l(hex_l_net),
5105    .hex_m(hex_m_net),
5106    .hex_r(hex_r_net),
5107    .led8(led8_net),
5108    .outselect(logical2_y_net_x1),
5109    .sda(sda_net)
5110  );
5111
5112  x2wire_count_gen_module_02dae4398f  x2wire_count_gen_02dae4398f (
5113    .ce(relational_op_net_x5),
5114    .ce_1(ce_1_sg_x10),
5115    .clk_1(clk_1_sg_x10),
5116    .reset(logical_y_net_x5),
5117    .addr(counter4_op_net_x1),
5118    .enable31(relational1_op_net_x2),
5119    .enable7(relational_op_net_x2)
5120  );
5121endmodule
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