[1331] | 1 | //---------------------------------------------------------------------------- |
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| 2 | // user_logic.vhd - module |
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| 3 | //---------------------------------------------------------------------------- |
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| 4 | // |
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| 5 | // *************************************************************************** |
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| 6 | // ** Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. ** |
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| 7 | // ** ** |
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| 8 | // ** Xilinx, Inc. ** |
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| 9 | // ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** |
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| 10 | // ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** |
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| 11 | // ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** |
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| 12 | // ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** |
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| 13 | // ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** |
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| 14 | // ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** |
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| 15 | // ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** |
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| 16 | // ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** |
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| 17 | // ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** |
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| 18 | // ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** |
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| 19 | // ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** |
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| 20 | // ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** |
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| 21 | // ** FOR A PARTICULAR PURPOSE. ** |
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| 22 | // ** ** |
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| 23 | // *************************************************************************** |
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| 24 | // |
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| 25 | //---------------------------------------------------------------------------- |
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| 26 | // Filename: user_logic.vhd |
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| 27 | // Version: 1.00.a |
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| 28 | // Description: User logic module. |
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| 29 | // Date: Mon Oct 5 10:19:40 2009 (by Create and Import Peripheral Wizard) |
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| 30 | // Verilog Standard: Verilog-2001 |
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| 31 | //---------------------------------------------------------------------------- |
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| 32 | // Naming Conventions: |
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| 33 | // active low signals: "*_n" |
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| 34 | // clock signals: "clk", "clk_div#", "clk_#x" |
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| 35 | // reset signals: "rst", "rst_n" |
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| 36 | // generics: "C_*" |
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| 37 | // user defined types: "*_TYPE" |
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| 38 | // state machine next state: "*_ns" |
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| 39 | // state machine current state: "*_cs" |
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| 40 | // combinatorial signals: "*_com" |
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| 41 | // pipelined or register delay signals: "*_d#" |
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| 42 | // counter signals: "*cnt*" |
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| 43 | // clock enable signals: "*_ce" |
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| 44 | // internal version of output port: "*_i" |
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| 45 | // device pins: "*_pin" |
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| 46 | // ports: "- Names begin with Uppercase" |
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| 47 | // processes: "*_PROCESS" |
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| 48 | // component instantiations: "<ENTITY_>I_<#|FUNC>" |
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| 49 | //---------------------------------------------------------------------------- |
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| 50 | |
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| 51 | // Ideal layout |
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| 52 | // |
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| 53 | // 5 |
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| 54 | // --- |
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| 55 | // 0 | | 4 |
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| 56 | // | 6 | |
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| 57 | // --- |
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| 58 | // 1 | | 3 |
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| 59 | // | 2 | |
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| 60 | // --- o 7 |
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| 61 | // |
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| 62 | // |
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| 63 | |
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| 64 | module user_logic |
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| 65 | ( |
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| 66 | leds, |
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| 67 | hex_sda, |
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| 68 | hex_scl, |
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| 69 | pushbuttons, |
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| 70 | dipsw, |
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| 71 | Bus2IP_Clk, // Bus to IP clock |
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| 72 | Bus2IP_Reset, // Bus to IP reset |
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| 73 | Bus2IP_Data, // Bus to IP data bus |
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| 74 | Bus2IP_BE, // Bus to IP byte enables |
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| 75 | Bus2IP_RdCE, // Bus to IP read chip enable |
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| 76 | Bus2IP_WrCE, // Bus to IP write chip enable |
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| 77 | IP2Bus_Data, // IP to Bus data bus |
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| 78 | IP2Bus_RdAck, // IP to Bus read transfer acknowledgement |
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| 79 | IP2Bus_WrAck, // IP to Bus write transfer acknowledgement |
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| 80 | IP2Bus_Error // IP to Bus error response |
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| 81 | ); // user_logic |
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| 82 | |
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| 83 | parameter C_ADDRESS_0 = 8'h40; |
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| 84 | parameter C_ADDRESS_1 = 8'h50; |
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| 85 | parameter C_I2C_DIVIDER = 8'h40; |
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| 86 | parameter C_SLV_DWIDTH = 32; |
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| 87 | parameter C_NUM_REG = 5; |
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| 88 | |
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| 89 | output [0:7] leds; |
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| 90 | output hex_sda; |
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| 91 | output hex_scl; |
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| 92 | input [0:3] pushbuttons; |
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| 93 | input [0:3] dipsw; |
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| 94 | |
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| 95 | // -- Bus protocol ports, do not add to or delete |
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| 96 | input Bus2IP_Clk; |
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| 97 | input Bus2IP_Reset; |
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| 98 | input [0 : C_SLV_DWIDTH-1] Bus2IP_Data; |
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| 99 | input [0 : C_SLV_DWIDTH/8-1] Bus2IP_BE; |
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| 100 | input [0 : C_NUM_REG-1] Bus2IP_RdCE; |
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| 101 | input [0 : C_NUM_REG-1] Bus2IP_WrCE; |
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| 102 | output [0 : C_SLV_DWIDTH-1] IP2Bus_Data; |
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| 103 | output IP2Bus_RdAck; |
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| 104 | output IP2Bus_WrAck; |
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| 105 | output IP2Bus_Error; |
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| 106 | |
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| 107 | //---------------------------------------------------------------------------- |
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| 108 | // Implementation |
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| 109 | //---------------------------------------------------------------------------- |
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| 110 | |
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| 111 | wire [0:7] addr0; |
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| 112 | wire [0:7] addr1; |
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| 113 | wire [0:7] divider; |
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| 114 | assign addr0 = C_ADDRESS_0; |
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| 115 | assign addr1 = C_ADDRESS_1; |
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| 116 | assign divider = C_I2C_DIVIDER; |
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| 117 | |
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| 118 | // Nets for user logic slave model s/w accessible register example |
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| 119 | reg [0 : C_SLV_DWIDTH-1] slv_reg0; |
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| 120 | reg [0 : C_SLV_DWIDTH-1] slv_reg1; |
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| 121 | reg [0 : C_SLV_DWIDTH-1] slv_reg2; |
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| 122 | reg [0 : C_SLV_DWIDTH-1] slv_reg3; |
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| 123 | reg [0 : C_SLV_DWIDTH-1] slv_reg4; |
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| 124 | wire [0 : 4] slv_reg_write_sel; |
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| 125 | wire [0 : 4] slv_reg_read_sel; |
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| 126 | reg [0 : C_SLV_DWIDTH-1] slv_ip2bus_data; |
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| 127 | wire slv_read_ack; |
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| 128 | wire slv_write_ack; |
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| 129 | integer byte_index, bit_index; |
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| 130 | |
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| 131 | |
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| 132 | // All IO except io expander assignment. Debouncing pushbuttons |
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| 133 | |
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| 134 | reg [0:3] push_de0; |
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| 135 | reg [0:3] push_de1; |
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| 136 | reg [0:3] push_de2; |
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| 137 | reg [0:3] push_de3; |
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| 138 | reg [0:3] dip_de0; |
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| 139 | reg [0:3] dip_de1; |
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| 140 | reg [0:3] dip_de2; |
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| 141 | reg [0:3] dip_de3; |
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| 142 | |
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| 143 | reg [0:7] hex_l_local; |
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| 144 | wire [0:7] hex_l_hw; |
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| 145 | reg [0:7] hex_m_local; |
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| 146 | wire [0:7] hex_m_hw; |
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| 147 | reg [0:7] hex_r_local; |
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| 148 | wire [0:7] hex_r_hw; |
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| 149 | wire [0:7] hex_led; |
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| 150 | |
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[1335] | 151 | assign leds = slv_reg0[24:31]; |
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[1331] | 152 | |
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| 153 | always @( posedge Bus2IP_Clk ) |
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| 154 | begin |
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| 155 | push_de0 <= (push_de0 << 1) | {3'b0, pushbuttons[0]}; |
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| 156 | push_de1 <= (push_de1 << 1) | {3'b0, pushbuttons[1]}; |
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| 157 | push_de2 <= (push_de2 << 1) | {3'b0, pushbuttons[2]}; |
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| 158 | push_de3 <= (push_de3 << 1) | {3'b0, pushbuttons[3]}; |
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| 159 | |
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[1335] | 160 | slv_reg1[28] <= &push_de0; |
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| 161 | slv_reg1[29] <= &push_de1; |
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| 162 | slv_reg1[30] <= &push_de2; |
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| 163 | slv_reg1[31] <= &push_de3; |
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[1331] | 164 | |
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| 165 | dip_de0 <= (dip_de0 << 1) | {3'b0, dipsw[0]}; |
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| 166 | dip_de1 <= (dip_de1 << 1) | {3'b0, dipsw[1]}; |
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| 167 | dip_de2 <= (dip_de2 << 1) | {3'b0, dipsw[2]}; |
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| 168 | dip_de3 <= (dip_de3 << 1) | {3'b0, dipsw[3]}; |
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| 169 | |
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[1335] | 170 | slv_reg1[24] <= &dip_de0; |
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| 171 | slv_reg1[25] <= &dip_de1; |
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| 172 | slv_reg1[26] <= &dip_de2; |
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| 173 | slv_reg1[27] <= &dip_de3; |
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[1331] | 174 | |
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| 175 | if (slv_reg4[31] == 1'b1) |
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| 176 | begin |
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| 177 | // hex_right |
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| 178 | case ({slv_reg2[26], slv_reg2[28:31]}) |
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| 179 | 5'b00000: |
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| 180 | hex_r_local <= 8'b11111100; |
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| 181 | 5'b00001: |
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| 182 | hex_r_local <= 8'b00011000; |
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| 183 | 5'b00010: |
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| 184 | hex_r_local <= 8'b01101110; |
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| 185 | 5'b00011: |
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| 186 | hex_r_local <= 8'b00111110; |
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| 187 | 5'b00100: |
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| 188 | hex_r_local <= 8'b10011010; |
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| 189 | 5'b00101: |
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| 190 | hex_r_local <= 8'b10110110; |
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| 191 | 5'b00110: |
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| 192 | hex_r_local <= 8'b11110110; |
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| 193 | 5'b00111: |
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| 194 | hex_r_local <= 8'b00011100; |
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| 195 | 5'b01000: |
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| 196 | hex_r_local <= 8'b11111110; |
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| 197 | 5'b01001: |
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| 198 | hex_r_local <= 8'b10111110; |
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| 199 | 5'b01010: |
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| 200 | hex_r_local <= 8'b11011110; |
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| 201 | 5'b01011: |
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| 202 | hex_r_local <= 8'b11111110; |
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| 203 | 5'b01100: |
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| 204 | hex_r_local <= 8'b11100100; |
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| 205 | 5'b01101: |
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| 206 | hex_r_local <= 8'b11111100; |
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| 207 | 5'b01110: |
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| 208 | hex_r_local <= 8'b11100110; |
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| 209 | 5'b01111: |
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| 210 | hex_r_local <= 8'b11000110; |
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| 211 | default: |
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| 212 | hex_r_local <= 8'b00000000; |
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| 213 | endcase |
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| 214 | hex_r_local[7] <= slv_reg2[27]; |
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| 215 | end |
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| 216 | else |
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| 217 | begin |
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| 218 | // if not in number mode, map slv_reg3 bits directly to hex_local |
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| 219 | hex_r_local <= slv_reg3[16:23]; |
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| 220 | end |
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| 221 | |
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| 222 | if (slv_reg4[30] == 1'b1) |
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| 223 | begin |
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| 224 | // hex_mid |
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| 225 | case ({slv_reg2[18], slv_reg2[20:23]}) |
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| 226 | 5'b00000: |
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| 227 | hex_m_local <= 8'b11111100; |
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| 228 | 5'b00001: |
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| 229 | hex_m_local <= 8'b00011000; |
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| 230 | 5'b00010: |
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| 231 | hex_m_local <= 8'b01101110; |
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| 232 | 5'b00011: |
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| 233 | hex_m_local <= 8'b00111110; |
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| 234 | 5'b00100: |
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| 235 | hex_m_local <= 8'b10011010; |
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| 236 | 5'b00101: |
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| 237 | hex_m_local <= 8'b10110110; |
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| 238 | 5'b00110: |
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| 239 | hex_m_local <= 8'b11110110; |
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| 240 | 5'b00111: |
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| 241 | hex_m_local <= 8'b00011100; |
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| 242 | 5'b01000: |
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| 243 | hex_m_local <= 8'b11111110; |
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| 244 | 5'b01001: |
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| 245 | hex_m_local <= 8'b10111110; |
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| 246 | 5'b01010: |
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| 247 | hex_m_local <= 8'b11011110; |
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| 248 | 5'b01011: |
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| 249 | hex_m_local <= 8'b11111110; |
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| 250 | 5'b01100: |
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| 251 | hex_m_local <= 8'b11100100; |
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| 252 | 5'b01101: |
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| 253 | hex_m_local <= 8'b11111100; |
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| 254 | 5'b01110: |
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| 255 | hex_m_local <= 8'b11100110; |
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| 256 | 5'b01111: |
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| 257 | hex_m_local <= 8'b11000110; |
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| 258 | default: |
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| 259 | hex_m_local <= 8'b00000000; |
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| 260 | endcase |
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| 261 | hex_m_local[7] <= slv_reg2[19]; |
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| 262 | end |
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| 263 | else |
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| 264 | begin |
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| 265 | // if not in number mode, map slv_reg3 bits directly to hex_local |
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| 266 | hex_m_local <= slv_reg3[8:15]; |
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| 267 | end |
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| 268 | |
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| 269 | if (slv_reg4[29] == 1'b1) |
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| 270 | begin |
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| 271 | // hex_left |
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| 272 | case ({slv_reg2[10], slv_reg2[12:15]}) |
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| 273 | 5'b00000: |
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| 274 | hex_l_local <= 8'b11111100; |
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| 275 | 5'b00001: |
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| 276 | hex_l_local <= 8'b00011000; |
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| 277 | 5'b00010: |
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| 278 | hex_l_local <= 8'b01101110; |
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| 279 | 5'b00011: |
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| 280 | hex_l_local <= 8'b00111110; |
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| 281 | 5'b00100: |
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| 282 | hex_l_local <= 8'b10011010; |
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| 283 | 5'b00101: |
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| 284 | hex_l_local <= 8'b10110110; |
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| 285 | 5'b00110: |
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| 286 | hex_l_local <= 8'b11110110; |
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| 287 | 5'b00111: |
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| 288 | hex_l_local <= 8'b00011100; |
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| 289 | 5'b01000: |
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| 290 | hex_l_local <= 8'b11111110; |
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| 291 | 5'b01001: |
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| 292 | hex_l_local <= 8'b10111110; |
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| 293 | 5'b01010: |
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| 294 | hex_l_local <= 8'b11011110; |
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| 295 | 5'b01011: |
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| 296 | hex_l_local <= 8'b11111110; |
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| 297 | 5'b01100: |
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| 298 | hex_l_local <= 8'b11100100; |
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| 299 | 5'b01101: |
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| 300 | hex_l_local <= 8'b11111100; |
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| 301 | 5'b01110: |
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| 302 | hex_l_local <= 8'b11100110; |
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| 303 | 5'b01111: |
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| 304 | hex_l_local <= 8'b11000110; |
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| 305 | default: |
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| 306 | hex_l_local <= 8'b00000000; |
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| 307 | endcase |
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| 308 | hex_l_local[7] <= slv_reg2[11]; |
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| 309 | end |
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| 310 | else |
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| 311 | begin |
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| 312 | // if not in number mode, map slv_reg3 bits directly to hex_local |
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| 313 | hex_l_local <= slv_reg3[0:7]; |
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| 314 | end |
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| 315 | end |
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| 316 | |
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| 317 | // perform crazy mapping of ideal layout of bits to actual hardware bits |
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| 318 | assign hex_r_hw = {hex_r_local[0], hex_r_local[6], hex_r_local[1], hex_r_local[2], hex_r_local[7], hex_r_local[3], hex_r_local[4], hex_r_local[5]}; |
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| 319 | assign hex_m_hw = {hex_m_local[0], hex_m_local[6], hex_m_local[1], hex_m_local[2], hex_m_local[7], hex_m_local[3], hex_m_local[4], hex_m_local[5]}; |
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| 320 | assign hex_l_hw = {hex_l_local[5], hex_l_local[4], hex_l_local[3], hex_l_local[7], hex_l_local[2], hex_l_local[1], hex_l_local[6], hex_l_local[0]}; |
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| 321 | assign hex_led = slv_reg3[24:31]; |
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| 322 | |
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| 323 | assign |
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| 324 | slv_reg_write_sel = Bus2IP_WrCE[0:4], |
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| 325 | slv_reg_read_sel = Bus2IP_RdCE[0:4], |
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| 326 | slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[1] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3] || Bus2IP_WrCE[4], |
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| 327 | slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3] || Bus2IP_RdCE[4]; |
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| 328 | |
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| 329 | // implement slave model register(s) |
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| 330 | always @( posedge Bus2IP_Clk ) |
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| 331 | begin: SLAVE_REG_WRITE_PROC |
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| 332 | |
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| 333 | if ( Bus2IP_Reset == 1 ) |
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| 334 | begin |
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| 335 | slv_reg0 <= 0; |
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| 336 | //slv_reg1 <= 0; |
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| 337 | slv_reg2 <= 0; |
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| 338 | slv_reg3 <= 0; |
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| 339 | slv_reg4 <= 0; |
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| 340 | end |
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| 341 | else |
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| 342 | case (slv_reg_write_sel) |
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| 343 | 5'b10000 : |
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| 344 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 345 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 346 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
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| 347 | slv_reg0[bit_index] <= Bus2IP_Data[bit_index]; |
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| 348 | //5'b01000 : |
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| 349 | // for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 350 | // if ( Bus2IP_BE[byte_index] == 1 ) |
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| 351 | // for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
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| 352 | // slv_reg1[bit_index] <= Bus2IP_Data[bit_index]; |
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| 353 | 5'b00100 : |
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| 354 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 355 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 356 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
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| 357 | slv_reg2[bit_index] <= Bus2IP_Data[bit_index]; |
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| 358 | 5'b00010 : |
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| 359 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 360 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 361 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
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| 362 | slv_reg3[bit_index] <= Bus2IP_Data[bit_index]; |
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| 363 | 5'b00001 : |
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| 364 | for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) |
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| 365 | if ( Bus2IP_BE[byte_index] == 1 ) |
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| 366 | for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 ) |
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| 367 | slv_reg4[bit_index] <= Bus2IP_Data[bit_index]; |
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| 368 | default : ; |
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| 369 | endcase |
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| 370 | |
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| 371 | end // SLAVE_REG_WRITE_PROC |
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| 372 | |
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| 373 | // implement slave model register read mux |
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| 374 | always @( slv_reg_read_sel or slv_reg0 or slv_reg1 or slv_reg2 or slv_reg3 or slv_reg4 ) |
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| 375 | begin: SLAVE_REG_READ_PROC |
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| 376 | |
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| 377 | case ( slv_reg_read_sel ) |
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| 378 | 5'b10000 : slv_ip2bus_data <= slv_reg0; |
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| 379 | 5'b01000 : slv_ip2bus_data <= slv_reg1; |
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| 380 | 5'b00100 : slv_ip2bus_data <= slv_reg2; |
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| 381 | 5'b00010 : slv_ip2bus_data <= {hex_l_local, hex_m_local, hex_r_local, hex_led}; |
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| 382 | 5'b00001 : slv_ip2bus_data <= slv_reg4; |
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| 383 | default : slv_ip2bus_data <= 0; |
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| 384 | endcase |
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| 385 | end // SLAVE_REG_READ_PROC |
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| 386 | |
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| 387 | // ------------------------------------------------------------ |
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| 388 | // Example code to drive IP to Bus signals |
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| 389 | // ------------------------------------------------------------ |
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| 390 | |
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| 391 | assign IP2Bus_Data = slv_ip2bus_data; |
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| 392 | assign IP2Bus_WrAck = slv_write_ack; |
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| 393 | assign IP2Bus_RdAck = slv_read_ack; |
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| 394 | assign IP2Bus_Error = 0; |
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| 395 | |
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| 396 | hex_out_cw hex_io ( |
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| 397 | .clk(Bus2IP_Clk), |
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| 398 | .ce(1'b1), |
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| 399 | .address0(addr0), |
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| 400 | .address1(addr1), |
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| 401 | .divider(divider), |
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| 402 | .hex_l(hex_m_hw), // naming error in sysgen. port corresponds to bits 0-7 of addr0 expander which is middle display |
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| 403 | .hex_m(hex_l_hw), // naming error in sysgen. port corresponds to bits 8-15 of addr0 expander which is left display |
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| 404 | .hex_r(hex_r_hw), |
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| 405 | .led8(hex_led), |
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| 406 | .reset(Bus2IP_Reset), |
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| 407 | .scl(hex_scl), |
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| 408 | .sda(hex_sda) |
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| 409 | ); |
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| 410 | |
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| 411 | endmodule |
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