source: PlatformSupport/CustomPeripherals/pcores/warp_v4_userio_v1_00_a/netlist/dmg_33_vx4_dcb0c4b6adf24a19.edn

Last change on this file was 1331, checked in by sgupta, 14 years ago

userio core for V4

  • Property svn:executable set to *
File size: 10.1 KB
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1(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
2(status (written (timeStamp 2009 10 1 13 35 22)
3   (author "Xilinx, Inc.")
4   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 10.1.03; Cores Update # 3"))))
5   (comment "                                                                               
6      This file is owned and controlled by Xilinx and must be used             
7      solely for design, simulation, implementation and creation of             
8      design files limited to Xilinx devices or technologies. Use               
9      with non-Xilinx devices or technologies is expressly prohibited           
10      and immediately terminates your license.                                 
11                                                                               
12      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
13      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
14      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
15      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
16      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
17      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
18      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         
19      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 
20      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
21      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           
22      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
23      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
24      FOR A PARTICULAR PURPOSE.                                                 
25                                                                               
26      Xilinx products are not intended for use in life support                 
27      appliances, devices, or systems. Use in such applications are             
28      expressly prohibited.                                                     
29                                                                               
30      (c) Copyright 1995-2007 Xilinx, Inc.                                     
31      All rights reserved.                                                     
32                                                                               
33   ")
34   (comment "Core parameters: ")
35       (comment "c_has_clk = 1 ")
36       (comment "c_has_qdpo_clk = 0 ")
37       (comment "c_has_qdpo_ce = 0 ")
38       (comment "c_has_d = 1 ")
39       (comment "c_elaboration_dir = C:\localhome\sgupta\userIOcontroller\netlist01\sysgen\coregen_xp... ")
40       (comment "                 ...yP\coregen_tmp\.\tmp\_cg\ ")
41       (comment "c_has_spo = 1 ")
42       (comment "c_read_mif = 1 ")
43       (comment "c_has_qspo = 0 ")
44       (comment "c_width = 1 ")
45       (comment "c_reg_a_d_inputs = 0 ")
46       (comment "c_has_we = 1 ")
47       (comment "c_pipeline_stages = 0 ")
48       (comment "c_has_qdpo_rst = 0 ")
49       (comment "c_reg_dpra_input = 0 ")
50       (comment "c_qualify_we = 0 ")
51       (comment "InstanceName = dmg_33_vx4_dcb0c4b6adf24a19 ")
52       (comment "c_sync_enable = 1 ")
53       (comment "c_depth = 64 ")
54       (comment "c_has_qspo_srst = 0 ")
55       (comment "c_has_qdpo_srst = 0 ")
56       (comment "c_has_dpra = 1 ")
57       (comment "c_qce_joined = 0 ")
58       (comment "c_mem_type = 2 ")
59       (comment "c_has_i_ce = 0 ")
60       (comment "c_has_dpo = 1 ")
61       (comment "c_mem_init_file = dmg_33_vx4_dcb0c4b6adf24a19.mif ")
62       (comment "c_default_data = 0 ")
63       (comment "c_has_spra = 0 ")
64       (comment "c_has_qspo_ce = 0 ")
65       (comment "c_addr_width = 6 ")
66       (comment "c_has_qdpo = 0 ")
67       (comment "c_has_qspo_rst = 0 ")
68   (external xilinxun (edifLevel 0)
69      (technology (numberDefinition))
70       (cell VCC (cellType GENERIC)
71           (view view_1 (viewType NETLIST)
72               (interface
73                   (port P (direction OUTPUT))
74               )
75           )
76       )
77       (cell GND (cellType GENERIC)
78           (view view_1 (viewType NETLIST)
79               (interface
80                   (port G (direction OUTPUT))
81               )
82           )
83       )
84   )
85   (external dmg_33_vx4_dcb0c4b6adf24a19_dist_mem_gen_v3_3_xst_1_lib (edifLevel 0)
86       (technology (numberDefinition))
87       (cell dmg_33_vx4_dcb0c4b6adf24a19_dist_mem_gen_v3_3_xst_1 (cellType GENERIC)
88           (view view_1 (viewType NETLIST)
89               (interface
90                   (port ( array ( rename a "a(5:0)") 6 ) (direction INPUT))
91                   (port ( array ( rename d "d(0:0)") 1 ) (direction INPUT))
92                   (port ( array ( rename dpra "dpra(5:0)") 6 ) (direction INPUT))
93                   (port ( array ( rename spra "spra(5:0)") 6 ) (direction INPUT))
94                   (port clk (direction INPUT))
95                   (port we (direction INPUT))
96                   (port i_ce (direction INPUT))
97                   (port qspo_ce (direction INPUT))
98                   (port qdpo_ce (direction INPUT))
99                   (port qdpo_clk (direction INPUT))
100                   (port qspo_rst (direction INPUT))
101                   (port qdpo_rst (direction INPUT))
102                   (port qspo_srst (direction INPUT))
103                   (port qdpo_srst (direction INPUT))
104                   (port ( array ( rename spo "spo(0:0)") 1 ) (direction OUTPUT))
105                   (port ( array ( rename dpo "dpo(0:0)") 1 ) (direction OUTPUT))
106                   (port ( array ( rename qspo "qspo(0:0)") 1 ) (direction OUTPUT))
107                   (port ( array ( rename qdpo "qdpo(0:0)") 1 ) (direction OUTPUT))
108               )
109           )
110       )
111   )
112(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
113(cell dmg_33_vx4_dcb0c4b6adf24a19
114 (cellType GENERIC) (view view_1 (viewType NETLIST)
115  (interface
116   (port ( array ( rename a "a(5:0)") 6 ) (direction INPUT))
117   (port ( array ( rename d "d(0:0)") 1 ) (direction INPUT))
118   (port ( array ( rename dpra "dpra(5:0)") 6 ) (direction INPUT))
119   (port ( rename clk "clk") (direction INPUT))
120   (port ( rename we "we") (direction INPUT))
121   (port ( array ( rename spo "spo(0:0)") 1 ) (direction OUTPUT))
122   (port ( array ( rename dpo "dpo(0:0)") 1 ) (direction OUTPUT))
123   )
124  (contents
125   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
126   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
127   (instance BU2
128      (viewRef view_1 (cellRef dmg_33_vx4_dcb0c4b6adf24a19_dist_mem_gen_v3_3_xst_1 (libraryRef dmg_33_vx4_dcb0c4b6adf24a19_dist_mem_gen_v3_3_xst_1_lib)))
129   )
130   (net N0
131    (joined
132      (portRef G (instanceRef GND))
133      (portRef (member spra 0) (instanceRef BU2))
134      (portRef (member spra 1) (instanceRef BU2))
135      (portRef (member spra 2) (instanceRef BU2))
136      (portRef (member spra 3) (instanceRef BU2))
137      (portRef (member spra 4) (instanceRef BU2))
138      (portRef (member spra 5) (instanceRef BU2))
139      (portRef qdpo_clk (instanceRef BU2))
140      (portRef qspo_rst (instanceRef BU2))
141      (portRef qdpo_rst (instanceRef BU2))
142      (portRef qspo_srst (instanceRef BU2))
143      (portRef qdpo_srst (instanceRef BU2))
144    )
145   )
146   (net N1
147    (joined
148      (portRef P (instanceRef VCC))
149      (portRef i_ce (instanceRef BU2))
150      (portRef qspo_ce (instanceRef BU2))
151      (portRef qdpo_ce (instanceRef BU2))
152    )
153   )
154   (net (rename N2087 "a(5)")
155    (joined
156      (portRef (member a 0))
157      (portRef (member a 0) (instanceRef BU2))
158    )
159   )
160   (net (rename N2088 "a(4)")
161    (joined
162      (portRef (member a 1))
163      (portRef (member a 1) (instanceRef BU2))
164    )
165   )
166   (net (rename N2089 "a(3)")
167    (joined
168      (portRef (member a 2))
169      (portRef (member a 2) (instanceRef BU2))
170    )
171   )
172   (net (rename N2090 "a(2)")
173    (joined
174      (portRef (member a 3))
175      (portRef (member a 3) (instanceRef BU2))
176    )
177   )
178   (net (rename N2091 "a(1)")
179    (joined
180      (portRef (member a 4))
181      (portRef (member a 4) (instanceRef BU2))
182    )
183   )
184   (net (rename N2092 "a(0)")
185    (joined
186      (portRef (member a 5))
187      (portRef (member a 5) (instanceRef BU2))
188    )
189   )
190   (net (rename N2093 "d(0)")
191    (joined
192      (portRef (member d 0))
193      (portRef (member d 0) (instanceRef BU2))
194    )
195   )
196   (net (rename N2094 "dpra(5)")
197    (joined
198      (portRef (member dpra 0))
199      (portRef (member dpra 0) (instanceRef BU2))
200    )
201   )
202   (net (rename N2095 "dpra(4)")
203    (joined
204      (portRef (member dpra 1))
205      (portRef (member dpra 1) (instanceRef BU2))
206    )
207   )
208   (net (rename N2096 "dpra(3)")
209    (joined
210      (portRef (member dpra 2))
211      (portRef (member dpra 2) (instanceRef BU2))
212    )
213   )
214   (net (rename N2097 "dpra(2)")
215    (joined
216      (portRef (member dpra 3))
217      (portRef (member dpra 3) (instanceRef BU2))
218    )
219   )
220   (net (rename N2098 "dpra(1)")
221    (joined
222      (portRef (member dpra 4))
223      (portRef (member dpra 4) (instanceRef BU2))
224    )
225   )
226   (net (rename N2099 "dpra(0)")
227    (joined
228      (portRef (member dpra 5))
229      (portRef (member dpra 5) (instanceRef BU2))
230    )
231   )
232   (net (rename N2106 "clk")
233    (joined
234      (portRef clk)
235      (portRef clk (instanceRef BU2))
236    )
237   )
238   (net (rename N2107 "we")
239    (joined
240      (portRef we)
241      (portRef we (instanceRef BU2))
242    )
243   )
244   (net (rename N2116 "spo(0)")
245    (joined
246      (portRef (member spo 0))
247      (portRef (member spo 0) (instanceRef BU2))
248    )
249   )
250   (net (rename N2117 "dpo(0)")
251    (joined
252      (portRef (member dpo 0))
253      (portRef (member dpo 0) (instanceRef BU2))
254    )
255   )
256))))
257(design dmg_33_vx4_dcb0c4b6adf24a19 (cellRef dmg_33_vx4_dcb0c4b6adf24a19 (libraryRef test_lib))
258  (property X_CORE_INFO (string "dist_mem_gen_v3_3, Xilinx CORE Generator 10.1.03_ip3"))
259  (property PART (string "xc4vfx12-sf363-12") (owner "Xilinx"))
260))
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