source: PlatformSupport/CustomPeripherals/pcores/warp_v4_userio_v1_00_a/src/warp_v4_userio.h

Last change on this file was 1583, checked in by murphpo, 14 years ago

adding missing #defines to fpga v2 user IO driver
  • Property svn:executable set to *
File size: 12.8 KB
Line 
1/*****************************************************************************
2* Filename:          /home/sgupta/edkwork/hex_disp_ise/custom_periph/MyProcessorIPLib/drivers/warp_v4_userio_v1_00_a/src/warp_v4_userio.h
3* Version:           1.00.a
4* Description:       warp_v4_userio Driver Header File
5* Date:              Mon Oct  5 10:19:41 2009 (by Create and Import Peripheral Wizard)
6*****************************************************************************/
7
8#ifndef WARP_V4_USERIO_H
9#define WARP_V4_USERIO_H
10
11/***************************** Include Files *******************************/
12
13#include "xbasic_types.h"
14#include "xstatus.h"
15#include "xio.h"
16
17/************************** Constant Definitions ***************************/
18
19
20/**
21 * User Logic Slave Space Offsets
22 * -- SLV_REG0 : user logic slave module register 0
23 * -- SLV_REG1 : user logic slave module register 1
24 * -- SLV_REG2 : user logic slave module register 2
25 * -- SLV_REG3 : user logic slave module register 3
26 * -- SLV_REG4 : user logic slave module register 4
27 */
28#define WARP_V4_USERIO_USER_SLV_SPACE_OFFSET (0x00000000)
29#define WARP_V4_USERIO_SLV_REG0_OFFSET (WARP_V4_USERIO_USER_SLV_SPACE_OFFSET + 0x00000000)
30#define WARP_V4_USERIO_SLV_REG1_OFFSET (WARP_V4_USERIO_USER_SLV_SPACE_OFFSET + 0x00000004)
31#define WARP_V4_USERIO_SLV_REG2_OFFSET (WARP_V4_USERIO_USER_SLV_SPACE_OFFSET + 0x00000008)
32#define WARP_V4_USERIO_SLV_REG3_OFFSET (WARP_V4_USERIO_USER_SLV_SPACE_OFFSET + 0x0000000C)
33#define WARP_V4_USERIO_SLV_REG4_OFFSET (WARP_V4_USERIO_USER_SLV_SPACE_OFFSET + 0x00000010)
34
35
36/**************************** Type Definitions *****************************/
37
38
39/***************** Macros (Inline Functions) Definitions *******************/
40
41/**
42 *
43 * Write a value to a WARP_V4_USERIO register. A 32 bit write is performed.
44 * If the component is implemented in a smaller width, only the least
45 * significant data is written.
46 *
47 * @param   BaseAddress is the base address of the WARP_V4_USERIO device.
48 * @param   RegOffset is the register offset from the base to write to.
49 * @param   Data is the data written to the register.
50 *
51 * @return  None.
52 *
53 * @note
54 * C-style signature:
55 *  void WARP_V4_USERIO_mWriteReg(Xuint32 BaseAddress, unsigned RegOffset, Xuint32 Data)
56 *
57 */
58#define WARP_V4_USERIO_mWriteReg(BaseAddress, RegOffset, Data) \
59    XIo_Out32((BaseAddress) + (RegOffset), (Xuint32)(Data))
60
61/**
62 *
63 * Read a value from a WARP_V4_USERIO register. A 32 bit read is performed.
64 * If the component is implemented in a smaller width, only the least
65 * significant data is read from the register. The most significant data
66 * will be read as 0.
67 *
68 * @param   BaseAddress is the base address of the WARP_V4_USERIO device.
69 * @param   RegOffset is the register offset from the base to write to.
70 *
71 * @return  Data is the data from the register.
72 *
73 * @note
74 * C-style signature:
75 *  Xuint32 WARP_V4_USERIO_mReadReg(Xuint32 BaseAddress, unsigned RegOffset)
76 *
77 */
78#define WARP_V4_USERIO_mReadReg(BaseAddress, RegOffset) \
79    XIo_In32((BaseAddress) + (RegOffset))
80
81
82/**
83 *
84 * Write/Read 32 bit value to/from WARP_V4_USERIO user logic slave registers.
85 *
86 * @param   BaseAddress is the base address of the WARP_V4_USERIO device.
87 * @param   RegOffset is the offset from the slave register to write to or read from.
88 * @param   Value is the data written to the register.
89 *
90 * @return  Data is the data from the user logic slave register.
91 *
92 * @note
93 * C-style signature:
94 *  void WARP_V4_USERIO_mWriteSlaveRegn(Xuint32 BaseAddress, unsigned RegOffset, Xuint32 Value)
95 *  Xuint32 WARP_V4_USERIO_mReadSlaveRegn(Xuint32 BaseAddress, unsigned RegOffset)
96 *
97 */
98#define WARP_V4_USERIO_mWriteSlaveReg0(BaseAddress, RegOffset, Value) \
99    XIo_Out32((BaseAddress) + (WARP_V4_USERIO_SLV_REG0_OFFSET) + (RegOffset), (Xuint32)(Value))
100#define WARP_V4_USERIO_mWriteSlaveReg1(BaseAddress, RegOffset, Value) \
101    XIo_Out32((BaseAddress) + (WARP_V4_USERIO_SLV_REG1_OFFSET) + (RegOffset), (Xuint32)(Value))
102#define WARP_V4_USERIO_mWriteSlaveReg2(BaseAddress, RegOffset, Value) \
103    XIo_Out32((BaseAddress) + (WARP_V4_USERIO_SLV_REG2_OFFSET) + (RegOffset), (Xuint32)(Value))
104#define WARP_V4_USERIO_mWriteSlaveReg3(BaseAddress, RegOffset, Value) \
105    XIo_Out32((BaseAddress) + (WARP_V4_USERIO_SLV_REG3_OFFSET) + (RegOffset), (Xuint32)(Value))
106#define WARP_V4_USERIO_mWriteSlaveReg4(BaseAddress, RegOffset, Value) \
107    XIo_Out32((BaseAddress) + (WARP_V4_USERIO_SLV_REG4_OFFSET) + (RegOffset), (Xuint32)(Value))
108
109#define WARP_V4_USERIO_mReadSlaveReg0(BaseAddress, RegOffset) \
110    XIo_In32((BaseAddress) + (WARP_V4_USERIO_SLV_REG0_OFFSET) + (RegOffset))
111#define WARP_V4_USERIO_mReadSlaveReg1(BaseAddress, RegOffset) \
112    XIo_In32((BaseAddress) + (WARP_V4_USERIO_SLV_REG1_OFFSET) + (RegOffset))
113#define WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, RegOffset) \
114    XIo_In32((BaseAddress) + (WARP_V4_USERIO_SLV_REG2_OFFSET) + (RegOffset))
115#define WARP_V4_USERIO_mReadSlaveReg3(BaseAddress, RegOffset) \
116    XIo_In32((BaseAddress) + (WARP_V4_USERIO_SLV_REG3_OFFSET) + (RegOffset))
117#define WARP_V4_USERIO_mReadSlaveReg4(BaseAddress, RegOffset) \
118    XIo_In32((BaseAddress) + (WARP_V4_USERIO_SLV_REG4_OFFSET) + (RegOffset))
119
120
121/* Register descriptions
122 * SlaveReg0 - Output register: 8 LSB bits output to the LEDs
123 * SlaveReg1 - Input register: 4 LSB are pushbuttons and 4 above that are dip switches
124 * SlaveReg2 - Hex displays in number mode. When in number mode
125               the bits in this register are mapped to numbers on the displays
126 * SlaveReg3 - Hex displays in raw mode. When in raw mode, the bits are directly
127               output to the hex displays
128 * SlaveReg4 - Control register: Setup parameters for hex display control
129 
130 Refer to http://warp.rice.edu/trac/wiki/HardwareUsersGuides/FPGABoard_v2.2/UserIO for details.
131*/
132
133#define LEFTHEX_OFFSET_NUM 16
134#define MIDHEX_OFFSET_NUM 8
135#define RIGHTHEX_OFFSET_NUM 0
136
137#define LEFTHEX_OFFSET_RAW 24
138#define MIDHEX_OFFSET_RAW 16
139#define RIGHTHEX_OFFSET_RAW 8
140#define IOEX_LEDS_OFFSET_RAW 0
141
142#define LEDMASK 0x000000FF
143#define PBMASK 0x0000000F
144#define DIPMASK 0x000000F0
145
146//Bit masks for user inputs (buttons & switches)
147#define USERIO_MASK_DIPSW   0xF0
148#define USERIO_MASK_PB      0x0F
149#define USERIO_MASK_PBC     0x01
150#define USERIO_MASK_PBR     0x02
151#define USERIO_MASK_PBL     0x04
152#define USERIO_MASK_PBU     0x08
153
154
155#define LED_OFFSET 0
156#define PB_OFFSET 0
157#define DIP_OFFSET 4
158
159#define LEFTHEX_NUM_MODE 0x00000004
160#define MIDHEX_NUM_MODE 0x00000002
161#define RIGHTHEX_NUM_MODE 0x00000001
162
163#define LEFTHEX_NUM_VAL 0x001F0000
164#define MIDHEX_NUM_VAL 0x00001F00
165#define RIGHTHEX_NUM_VAL 0x0000001F
166
167#define HEX_OFF_ON 0x00000020
168
169
170#define WarpV4_UserIO_Leds(BaseAddress, Value) \
171    WARP_V4_USERIO_mWriteSlaveReg0(BaseAddress, 0, (Value & LEDMASK))
172#define WarpV4_UserIO_PushB(BaseAddress) \
173    ((WARP_V4_USERIO_mReadSlaveReg1(BaseAddress, 0) & PBMASK) >> PB_OFFSET)
174#define WarpV4_UserIO_DipSw(BaseAddress) \
175    ((WARP_V4_USERIO_mReadSlaveReg1(BaseAddress, 0) & DIPMASK) >> DIP_OFFSET)
176   
177#define WarpV4_UserIO_NumberMode_All(BaseAddress) \
178    WARP_V4_USERIO_mWriteSlaveReg4(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg4(BaseAddress, 0) | (LEFTHEX_NUM_MODE | MIDHEX_NUM_MODE | RIGHTHEX_NUM_MODE)))
179#define WarpV4_UserIO_NumberMode_LeftHex(BaseAddress) \
180    WARP_V4_USERIO_mWriteSlaveReg4(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg4(BaseAddress, 0) | LEFTHEX_NUM_MODE))
181#define WarpV4_UserIO_NumberMode_MiddleHex(BaseAddress) \
182    WARP_V4_USERIO_mWriteSlaveReg4(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg4(BaseAddress, 0) | MIDHEX_NUM_MODE))
183#define WarpV4_UserIO_NumberMode_RightHex(BaseAddress) \
184    WARP_V4_USERIO_mWriteSlaveReg4(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg4(BaseAddress, 0) | RIGHTHEX_NUM_MODE))
185
186#define WarpV4_UserIO_WriteNumber_LeftHex(BaseAddress, NumberTW, DecimalPoint) \
187    WARP_V4_USERIO_mWriteSlaveReg2(BaseAddress, 0, (((WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, 0) & ~LEFTHEX_NUM_VAL) | ((NumberTW & 0x0000000F) << LEFTHEX_OFFSET_NUM)) | ((DecimalPoint & 0x00000001) << (LEFTHEX_OFFSET_NUM+4))))
188#define WarpV4_UserIO_WriteNumber_MiddleHex(BaseAddress, NumberTW, DecimalPoint) \
189    WARP_V4_USERIO_mWriteSlaveReg2(BaseAddress, 0, (((WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, 0) & ~MIDHEX_NUM_VAL) | ((NumberTW & 0x0000000F) << MIDHEX_OFFSET_NUM)) | ((DecimalPoint & 0x00000001) << (MIDHEX_OFFSET_NUM+4))))
190#define WarpV4_UserIO_WriteNumber_RightHex(BaseAddress, NumberTW, DecimalPoint) \
191    WARP_V4_USERIO_mWriteSlaveReg2(BaseAddress, 0, (((WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, 0) & ~RIGHTHEX_NUM_VAL) | ((NumberTW & 0x0000000F) << RIGHTHEX_OFFSET_NUM)) | ((DecimalPoint & 0x00000001) << (RIGHTHEX_OFFSET_NUM+4))))
192
193#define WarpV4_UserIO_ReadNumber_LeftHex(BaseAddress) \
194    ((WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, 0) & LEFTHEX_NUM_VAL) >> LEFTHEX_OFFSET_NUM)
195#define WarpV4_UserIO_ReadNumber_MiddleHex(BaseAddress) \
196    ((WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, 0) & MIDHEX_NUM_VAL) >> MIDHEX_OFFSET_NUM)
197#define WarpV4_UserIO_ReadNumber_RightHex(BaseAddress) \
198    ((WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, 0) & RIGHTHEX_NUM_VAL) >> RIGHTHEX_OFFSET_NUM)
199
200#define WarpV4_UserIO_LeftHex_Off(BaseAddress) \
201    WARP_V4_USERIO_mWriteSlaveReg2(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, 0) | (HEX_OFF_ON << LEFTHEX_OFFSET_NUM)))
202#define WarpV4_UserIO_MiddleHex_Off(BaseAddress) \
203    WARP_V4_USERIO_mWriteSlaveReg2(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, 0) | (HEX_OFF_ON << MIDHEX_OFFSET_NUM)))
204#define WarpV4_UserIO_RightHex_Off(BaseAddress) \
205    WARP_V4_USERIO_mWriteSlaveReg2(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, 0) | (HEX_OFF_ON << RIGHTHEX_OFFSET_NUM)))
206
207#define WarpV4_UserIO_LeftHex_On(BaseAddress) \
208    WARP_V4_USERIO_mWriteSlaveReg2(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, 0) & ~(HEX_OFF_ON << LEFTHEX_OFFSET_NUM)))
209#define WarpV4_UserIO_MiddleHex_On(BaseAddress) \
210    WARP_V4_USERIO_mWriteSlaveReg2(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, 0) & ~(HEX_OFF_ON << MIDHEX_OFFSET_NUM)))
211#define WarpV4_UserIO_RightHex_On(BaseAddress) \
212    WARP_V4_USERIO_mWriteSlaveReg2(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, 0) & ~(HEX_OFF_ON << RIGHTHEX_OFFSET_NUM)))
213
214#define WarpV4_UserIO_Write_ExtraLeds(BaseAddress, Value) \
215    WARP_V4_USERIO_mWriteSlaveReg3(BaseAddress, 0, ((WARP_V4_USERIO_mReadSlaveReg3(BaseAddress, 0) & ~(LEDMASK << IOEX_LEDS_OFFSET_RAW)) | ((Value & LEDMASK) << IOEX_LEDS_OFFSET_RAW)))
216#define WarpV4_UserIO_WriteRaw_LeftHex(BaseAddress, Value) \
217    WARP_V4_USERIO_mWriteSlaveReg3(BaseAddress, 0, ((WARP_V4_USERIO_mReadSlaveReg3(BaseAddress, 0) & ~(LEDMASK << LEFTHEX_OFFSET_RAW)) | ((Value & LEDMASK) << LEFTHEX_OFFSET_RAW)))
218#define WarpV4_UserIO_WriteRaw_MiddleHex(BaseAddress, Value) \
219    WARP_V4_USERIO_mWriteSlaveReg3(BaseAddress, 0, ((WARP_V4_USERIO_mReadSlaveReg3(BaseAddress, 0) & ~(LEDMASK << MIDHEX_OFFSET_RAW)) | ((Value & LEDMASK) << MIDHEX_OFFSET_RAW)))
220#define WarpV4_UserIO_WriteRaw_RightHex(BaseAddress, Value) \
221    WARP_V4_USERIO_mWriteSlaveReg3(BaseAddress, 0, ((WARP_V4_USERIO_mReadSlaveReg3(BaseAddress, 0) & ~(LEDMASK << RIGHTHEX_OFFSET_RAW)) | ((Value & LEDMASK) << RIGHTHEX_OFFSET_RAW)))
222
223#define WarpV4_UserIO_Read_ExtraLeds(BaseAddress) \
224    ((WARP_V4_USERIO_mReadSlaveReg3(BaseAddress, 0) >> IOEX_LEDS_OFFSET_RAW) & LEDMASK)
225#define WarpV4_UserIO_ReadRaw_LeftHex(BaseAddress) \
226    ((WARP_V4_USERIO_mReadSlaveReg3(BaseAddress, 0) >> LEFTHEX_OFFSET_RAW) & LEDMASK)
227#define WarpV4_UserIO_ReadRaw_MiddleHex(BaseAddress) \
228    ((WARP_V4_USERIO_mReadSlaveReg3(BaseAddress, 0) >> MIDHEX_OFFSET_RAW) & LEDMASK)
229#define WarpV4_UserIO_ReadRaw_RightHex(BaseAddress) \
230    ((WARP_V4_USERIO_mReadSlaveReg3(BaseAddress, 0) >> RIGHTHEX_OFFSET_RAW) & LEDMASK)
231
232#define WarpV4_UserIO_RawMode_All(BaseAddress) \
233    { \
234        WarpV4_UserIO_WriteRaw_LeftHex(BaseAddress, WarpV4_UserIO_ReadRaw_LeftHex(BaseAddress)); \
235        WarpV4_UserIO_WriteRaw_MiddleHex(BaseAddress, WarpV4_UserIO_ReadRaw_MiddleHex(BaseAddress)); \
236        WarpV4_UserIO_WriteRaw_RightHex(BaseAddress, WarpV4_UserIO_ReadRaw_RightHex(BaseAddress)); \
237        WARP_V4_USERIO_mWriteSlaveReg4(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg4(BaseAddress, 0) & ~(LEFTHEX_NUM_MODE | MIDHEX_NUM_MODE | RIGHTHEX_NUM_MODE))); \
238    }
239#define WarpV4_UserIO_RawMode_LeftHex(BaseAddress) \
240    { \
241        WarpV4_UserIO_WriteRaw_LeftHex(BaseAddress, WarpV4_UserIO_ReadRaw_LeftHex(BaseAddress)); \
242        WARP_V4_USERIO_mWriteSlaveReg4(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg4(BaseAddress, 0) & ~LEFTHEX_NUM_MODE)); \
243    }
244#define WarpV4_UserIO_RawMode_MiddleHex(BaseAddress) \
245    { \
246        WarpV4_UserIO_WriteRaw_MiddleHex(BaseAddress, WarpV4_UserIO_ReadRaw_MiddleHex(BaseAddress)); \
247        WARP_V4_USERIO_mWriteSlaveReg4(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg4(BaseAddress, 0) & ~MIDHEX_NUM_MODE)); \
248    }
249#define WarpV4_UserIO_RawMode_RightHex(BaseAddress) \
250    { \
251        WarpV4_UserIO_WriteRaw_RightHex(BaseAddress, WarpV4_UserIO_ReadRaw_RightHex(BaseAddress)); \
252        WARP_V4_USERIO_mWriteSlaveReg4(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg4(BaseAddress, 0) & ~RIGHTHEX_NUM_MODE)); \
253    }
254
255
256/************************** Function Prototypes ****************************/
257
258
259
260#endif /** WARP_V4_USERIO_H */
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