source: PlatformSupport/WARPMAC/util/ofdm_agc_mimo_regMacros.h

Last change on this file was 1712, checked in by murphpo, 12 years ago

Updating code for OFDM ref design v17 in ISE 13.4 tools
  • Property svn:executable set to *
File size: 4.5 KB
Line 
1/*! \file ofdm_txrx_mimo_regMacros.h
2\brief Header file for PHY register access
3
4@author Patrick Murphy
5
6This header file contains macros using the naming scheme previously used by sysgen2opb. These are the macros warpphy/warpmac call to interact with the PHY.
7This file will only be used with EDK 10.1+ designs. For projects built using sysgen2opb and EDK 9.1, these macros will be defined by the ofdm_txrx_mimo.h header
8created by sysgen2opb during the EDK export from sysgen.
9*/
10
11#include "xbasic_types.h"
12#include "xstatus.h"
13#include "xio.h"
14
15//Macros to write PHY registers, using naming scheme from sysgen2opb's auto-generated driver header
16#define OFDM_AGC_MIMO_WriteReg_SRESET_IN(BaseAddress, Value)    XIo_Out32(XPAR_OFDM_AGC_MIMO_PLBW_0_MEMMAP_SRESET_IN, (Xuint32)(Value))
17#define OFDM_AGC_MIMO_WriteReg_MRESET_IN(BaseAddress, Value)    XIo_Out32(XPAR_OFDM_AGC_MIMO_PLBW_0_MEMMAP_MRESET_IN, (Xuint32)(Value))
18#define OFDM_AGC_MIMO_WriteReg_T_dB(BaseAddress, Value)     XIo_Out32(XPAR_OFDM_AGC_MIMO_PLBW_0_MEMMAP_T_DB, (Xuint32)(Value))
19#define OFDM_AGC_MIMO_WriteReg_DCO_Timing(BaseAddress, Value)   XIo_Out32(XPAR_OFDM_AGC_MIMO_PLBW_0_MEMMAP_DCO_TIMING, (Xuint32)(Value))
20#define OFDM_AGC_MIMO_WriteReg_AGC_EN(BaseAddress, Value)   XIo_Out32(XPAR_OFDM_AGC_MIMO_PLBW_0_MEMMAP_AGC_EN, (Xuint32)(Value))
21#define OFDM_AGC_MIMO_WriteReg_AVG_LEN(BaseAddress, Value)  XIo_Out32(XPAR_OFDM_AGC_MIMO_PLBW_0_MEMMAP_AVG_LEN, (Xuint32)(Value))
22#define OFDM_AGC_MIMO_WriteReg_Timing(BaseAddress, Value)   XIo_Out32(XPAR_OFDM_AGC_MIMO_PLBW_0_MEMMAP_TIMING, (Xuint32)(Value))
23#define OFDM_AGC_MIMO_WriteReg_Thresholds(BaseAddress, Value)   XIo_Out32(XPAR_OFDM_AGC_MIMO_PLBW_0_MEMMAP_THRESHOLDS, (Xuint32)(Value))
24#define OFDM_AGC_MIMO_WriteReg_ADJ(BaseAddress, Value)  XIo_Out32(XPAR_OFDM_AGC_MIMO_PLBW_0_MEMMAP_ADJ, (Xuint32)(Value))
25#define OFDM_AGC_MIMO_WriteReg_GBB_init(BaseAddress, Value)     XIo_Out32(XPAR_OFDM_AGC_MIMO_PLBW_0_MEMMAP_GBB_INIT, (Xuint32)(Value))
26#define OFDM_AGC_MIMO_WriteReg_Bits(BaseAddress, Value)     XIo_Out32(XPAR_OFDM_AGC_MIMO_PLBW_0_MEMMAP_BITS_W, (Xuint32)(Value))
27
28//Macros to read PHY registers, using naming scheme from sysgen2opb's auto-generated driver header
29#define OFDM_AGC_MIMO_ReadReg_GBB_A(BaseAddress)    XIo_In32(XPAR_OFDM_AGC_MIMO_PLBW_0_MEMMAP_GBB_A)
30#define OFDM_AGC_MIMO_ReadReg_GBB_B(BaseAddress)    XIo_In32(XPAR_OFDM_AGC_MIMO_PLBW_0_MEMMAP_GBB_B)
31#define OFDM_AGC_MIMO_ReadReg_GRF_A(BaseAddress)    XIo_In32(XPAR_OFDM_AGC_MIMO_PLBW_0_MEMMAP_GRF_A)
32#define OFDM_AGC_MIMO_ReadReg_GRF_B(BaseAddress)    XIo_In32(XPAR_OFDM_AGC_MIMO_PLBW_0_MEMMAP_GRF_B)
33#define OFDM_AGC_MIMO_ReadReg_Bits(BaseAddress)     XIo_In32(XPAR_OFDM_AGC_MIMO_PLBW_0_MEMMAP_BITS_R)
34
35//Macros that were defined in the sysgen2opb driver, but were never used; these are not defined for the PLB46 version of the core
36//#define OFDM_AGC_MIMO_WriteReg_GBB_A(BaseAddress, Value)  XIo_Out32((BaseAddress) + (OFDM_AGC_MIMO_GBB_A_OFFSET), (Xuint32)(Value))
37//#define OFDM_AGC_MIMO_WriteReg_GBB_B(BaseAddress, Value)  XIo_Out32((BaseAddress) + (OFDM_AGC_MIMO_GBB_B_OFFSET), (Xuint32)(Value))
38//#define OFDM_AGC_MIMO_WriteReg_GRF_B(BaseAddress, Value)  XIo_Out32((BaseAddress) + (OFDM_AGC_MIMO_GRF_B_OFFSET), (Xuint32)(Value))
39//#define OFDM_AGC_MIMO_WriteReg_GRF_A(BaseAddress, Value)  XIo_Out32((BaseAddress) + (OFDM_AGC_MIMO_GRF_A_OFFSET), (Xuint32)(Value))
40//#define OFDM_AGC_MIMO_ReadReg_SRESET_IN(BaseAddress)  XIo_In32((BaseAddress) + (OFDM_AGC_MIMO_SRESET_IN_OFFSET))
41//#define OFDM_AGC_MIMO_ReadReg_MRESET_IN(BaseAddress)  XIo_In32((BaseAddress) + (OFDM_AGC_MIMO_MRESET_IN_OFFSET))
42//#define OFDM_AGC_MIMO_ReadReg_T_dB(BaseAddress)   XIo_In32((BaseAddress) + (OFDM_AGC_MIMO_T_dB_OFFSET))
43//#define OFDM_AGC_MIMO_ReadReg_DCO_Timing(BaseAddress)     XIo_In32((BaseAddress) + (OFDM_AGC_MIMO_DCO_Timing_OFFSET))
44//#define OFDM_AGC_MIMO_ReadReg_AGC_EN(BaseAddress)     XIo_In32((BaseAddress) + (OFDM_AGC_MIMO_AGC_EN_OFFSET))
45//#define OFDM_AGC_MIMO_ReadReg_AVG_LEN(BaseAddress)    XIo_In32((BaseAddress) + (OFDM_AGC_MIMO_AVG_LEN_OFFSET))
46//#define OFDM_AGC_MIMO_ReadReg_Bits(BaseAddress)   XIo_In32((BaseAddress) + (OFDM_AGC_MIMO_Bits_OFFSET))
47//#define OFDM_AGC_MIMO_ReadReg_Timing(BaseAddress)     XIo_In32((BaseAddress) + (OFDM_AGC_MIMO_Timing_OFFSET))
48//#define OFDM_AGC_MIMO_ReadReg_Thresholds(BaseAddress)     XIo_In32((BaseAddress) + (OFDM_AGC_MIMO_Thresholds_OFFSET))
49//#define OFDM_AGC_MIMO_ReadReg_ADJ(BaseAddress)    XIo_In32((BaseAddress) + (OFDM_AGC_MIMO_ADJ_OFFSET))
50//#define OFDM_AGC_MIMO_ReadReg_GBB_init(BaseAddress)   XIo_In32((BaseAddress) + (OFDM_AGC_MIMO_GBB_init_OFFSET))
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