source: PlatformSupport/WARPMAC/warp_v3/warpphy.h

Last change on this file was 1815, checked in by murphpo, 12 years ago
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1/*! \file warpphy.h
2\brief Header file for the WARPPHY functions
3
4@version 15.22
5@author Patrick Murphy and Chris Hunter
6
7This header file contains the macros, function prototypes, and typedefs required for WARPPHY.
8*/
9
10//WARPPHY Interface
11/***************CHANGELOG*****************
12
13******************************************/
14/*****************WARPPHY*****************
15Description: This file specifies the
16interface between to the PHY.
17******************************************/
18
19#ifndef WARPPHY_H
20#define WARPPHY_H
21
22//Flag to include a bunch of low-level debugging functions
23// for tweaking values in the PHY cores
24// These can be excluded for most applications, saving a lot of code space
25#define INCLUDE_WARPPHY_DEBUG_FUNCTIONS 0
26
27//Old design flow used OFDM_BASEADDR to refer to the PHY's base address
28// New flow addresses registers directly, not relative to a base address
29// This value is still defined to keep code from breaking
30#define OFDM_BASEADDR 0
31
32//PHY packet buffer is actually a PLB BRAM
33// The base address is the address of the PLB BRAM controller
34#define OFDM_PKTBUFF_BASEADDR XPAR_XPS_BRAM_IF_CNTLR_2_BASEADDR
35
36//Masks for configuring modulation settings in the PHY
37//Each is 8 copies of a 4-bit modulation value
38#define MODMASK_BPSK 0x11111111
39#define MODMASK_QPSK 0x22222222
40#define MODMASK_16QAM 0x44444444
41#define MODMASK_64QAM 0x66666666
42
43#define MOD_UNCHANGED 0xFF
44
45#define NUM_BASERATE_SYMBOLS_BPSK_CODED 8
46#define NUM_BASERATE_SYMBOLS_QPSK_CODED 4
47#define NUM_BASERATE_SYMBOLS_BPSK_UNCODED 4
48#define NUM_BASERATE_SYMBOLS_QPSK_UNCODED 2
49
50//Number of base rate OFDM symbols per packet
51// Must correspond to base rate modulation, number of header bytes and header coding rate
52#define NUM_BASERATE_SYMBOLS NUM_BASERATE_SYMBOLS_QPSK_CODED
53
54//Define number of channel training symbols per packet - must be even!
55// In SISO mode all symbols are used to train the H_AA channel
56// In Alamouti, alternate symbols train H_AA and H_BA
57// In 2x2, alternate symbols train H_AA/H_AB and H_BA/H_BB
58#define NUM_TRAINING_SYMBOLS    2
59
60//Number of packet buffers; each sub-buffer is 2KB, so a 64KB PLB BRAM hold 32 buffers
61#define NUMPKTBUFFS 32
62
63//Length of the running RSSI sum in the pkt detector
64// #define'd here so it can be used again below
65#define PKTDET_RSSI_SUMLEN      16
66
67//Define an RSSI threshold big enough so that carrier sensing will never assert
68// This is used to "disable" carrier sensing at run time
69#define CSMA_DISABLED_THRESH    (1023*PKTDET_RSSI_SUMLEN)
70
71//Initial FFT window offset (number of CP samples to use per Rx FFT)
72#define INIT_RXFFTOFSET 10
73
74//Code rate selection values, used in header.codeRate field per-packet
75//#define CONVCODED_PHY 1
76#define HDR_CODE_RATE_12 0
77#define HDR_CODE_RATE_23 1
78#define HDR_CODE_RATE_34 2
79#define HDR_CODE_RATE_NONE 3
80
81#define TIMER_MODE_CARRIERSENSE     1
82#define TIMER_MODE_NOCARRIERSENSE   0
83
84//Define scaling values for the PHY's FFT cores
85#define TX_FFT_SCALING_STAGE1 1
86#define TX_FFT_SCALING_STAGE2 2
87#define TX_FFT_SCALING_STAGE3 3
88
89// Was 1 2 1
90#define RX_FFT_SCALING_STAGE1 0
91#define RX_FFT_SCALING_STAGE2 1
92#define RX_FFT_SCALING_STAGE3 1
93
94//Define thresholds for the AGC
95#define AGC_THRESH_1 (256-24)
96#define AGC_THRESH_2 (256-55)
97#define AGC_THRESH_3 (256-127)
98
99/*#define AGC_THRESH_1 0xE2 //-30
100//#define AGC_THRESH_2 0xCB //-53
101//#define AGC_THRESH_2 0xC6 //-58
102#define AGC_THRESH_2 0xB0 //-x
103//#define AGC_THRESH_3 0xA6 //-90
104#define AGC_THRESH_3 0x81 //-127
105*/
106
107//RX Status register values
108#define PHYRXSTATUS_INCOMPLETE 0
109#define PHYRXSTATUS_GOOD 0x5
110#define PHYRXSTATUS_BAD 0xA
111#define PHYRXSTATUS_PAYLOAD 0x3
112#define PHYRXSTATUS_HEADER 0xC
113
114//Antenna configuration constants
115#define ANTMODE_UNCHANGED           0
116
117#define ANTMODE_MASK_ANTSEL         0x00F
118#define ANTMODE_MASK_PHYMODE        0x0F0
119#define ANTMODE_MASK_PHYANTCFG      0xF00
120
121#define ANTMODE_ANTSEL_RADA         0x001
122#define ANTMODE_ANTSEL_RADB         0x002
123#define ANTMODE_ANTSEL_BOTHRADS     (ANTMODE_ANTSEL_RADA | ANTMODE_ANTSEL_RADB)
124
125#define PHYMODE_SISO                0x010
126#define PHYMODE_ALAMOUTI            0x020
127#define PHYMODE_2X2MULT             0x040
128
129#define PHYANTCFG_TX_NORMAL         0x100
130#define PHYANTCFG_TX_SWAPPED        0x200
131
132#define PHYANTCFG_RX_NORMAL         0x100
133#define PHYANTCFG_RX_SWAPPED        0x200
134#define PHYANTCFG_RX_SELDIV         0x400
135
136#define TX_ANTMODE_SISO_ANTA                (ANTMODE_ANTSEL_RADA | PHYMODE_SISO | PHYANTCFG_TX_NORMAL)
137#define TX_ANTMODE_SISO_ANTB                (ANTMODE_ANTSEL_RADB | PHYMODE_SISO | PHYANTCFG_TX_SWAPPED)
138#define TX_ANTMODE_MULTPLX                  (ANTMODE_ANTSEL_BOTHRADS | PHYMODE_2X2MULT | PHYANTCFG_TX_NORMAL)
139#define TX_ANTMODE_MULTPLX_SWAPPED          (ANTMODE_ANTSEL_BOTHRADS | PHYMODE_2X2MULT | PHYANTCFG_TX_SWAPPED)
140#define TX_ANTMODE_ALAMOUTI_2ANT            (ANTMODE_ANTSEL_BOTHRADS | PHYMODE_ALAMOUTI | PHYANTCFG_TX_NORMAL)
141#define TX_ANTMODE_ALAMOUTI_2ANT_SWAPPED    (ANTMODE_ANTSEL_BOTHRADS | PHYMODE_ALAMOUTI | PHYANTCFG_TX_SWAPPED)
142#define TX_ANTMODE_ALAMOUTI_ANTA            (ANTMODE_ANTSEL_RADA | PHYMODE_ALAMOUTI | PHYANTCFG_TX_NORMAL)
143#define TX_ANTMODE_ALAMOUTI_ANTB            (ANTMODE_ANTSEL_RADB | PHYMODE_ALAMOUTI | PHYANTCFG_TX_NORMAL)
144#define TX_ANTMODE_ALAMOUTI_ANTA_SWAPPED    (ANTMODE_ANTSEL_RADA | PHYMODE_ALAMOUTI | PHYANTCFG_TX_SWAPPED)
145#define TX_ANTMODE_ALAMOUTI_ANTB_SWAPPED    (ANTMODE_ANTSEL_RADB | PHYMODE_ALAMOUTI | PHYANTCFG_TX_SWAPPED)
146
147#define RX_ANTMODE_SISO_ANTA                (ANTMODE_ANTSEL_RADA | PHYMODE_SISO | PHYANTCFG_RX_NORMAL)
148#define RX_ANTMODE_SISO_ANTB                (ANTMODE_ANTSEL_RADB | PHYMODE_SISO | PHYANTCFG_RX_SWAPPED)
149#define RX_ANTMODE_SISO_SELDIV              (ANTMODE_ANTSEL_BOTHRADS | PHYMODE_SISO | PHYANTCFG_RX_SELDIV)
150#define RX_ANTMODE_MULTPLX                  (ANTMODE_ANTSEL_BOTHRADS | PHYMODE_2X2MULT | PHYANTCFG_RX_NORMAL)
151#define RX_ANTMODE_ALAMOUTI_ANTA            (ANTMODE_ANTSEL_RADA | PHYMODE_ALAMOUTI | PHYANTCFG_RX_NORMAL)
152#define RX_ANTMODE_ALAMOUTI_ANTB            (ANTMODE_ANTSEL_RADB | PHYMODE_ALAMOUTI | PHYANTCFG_RX_SWAPPED)
153#define RX_ANTMODE_ALAMOUTI_SELDIV          (ANTMODE_ANTSEL_BOTHRADS | PHYMODE_ALAMOUTI | PHYANTCFG_RX_SELDIV)
154
155//Bit masks for the options configured in Rx_ControlBits
156#define RESET_BER           0x1
157#define REQ_LONG_CORR       0x2
158//#define UNUSED            0x4
159#define BIG_PKTBUF_MODE     0x8
160#define RX_SISO_MODE        0x10
161//#define UNUSED            0x20
162//#define UNUSED            0x40
163#define RECORD_CHAN_ESTS    0x80
164#define RECORD_CHAN_ESTMAGS 0x100
165#define BYPASS_CARR_REC     0x200
166#define COARSE_CFO_EN       0x400
167#define EXT_PKTDETRESET_EN  0x800
168#define RSSI_GAIN_ADJ       0x1000
169#define EQ_BYPASS_DIVISION  0x4000
170#define TX_DISABLE_PKTDET   0x8000
171#define SIMPLE_DYN_MOD_EN   0x10000
172#define SWITCHING_DIV_EN    0x20000
173#define SISO_ON_ANTB        0x40000
174#define RESET_ON_BAD_HDR    0x80000
175#define RX_ALAMOUTI_MODE    0x100000
176#define FLEX_BER_MODE       0x200000
177#define BER_IGNORE_HDR      0x400000
178#define PHY_RADIO_RXEN      0x1000000
179#define AF_SAVEWAVEFORM     0x2000000
180#define AUTORESP_FLAGA_RST  0x4000000
181#define AUTORESP_FLAGB_RST  0x8000000
182#define COARSECFO_PKTDET_EN 0x10000000
183#define CHANMAG_MASKING_EN  0x20000000
184//#define UNUSED            0x40000000
185#define RX_GLOBAL_RESET     0x80000000
186
187//Bit masks for PreCFO_Options register
188#define PRECFO_USECOARSE    0x00000001
189#define PRECFO_USEPILOTS    0x00000002
190
191//Bit masks for Tx Start/Reset register
192#define TX_MASTER_RESET     0x1
193#define TX_START            0x2
194
195//Bit masks for OFDM Tx options
196#define TX_SISO_MODE                0x00000001
197#define TX_ALAMOUTI_MODE            0x00000002
198#define TX_DISABLE_ANTB_PREAMBLE    0x00000004
199#define TX_PILOT_SCRAMBLING         0x00000008
200#define TX_PREAMBLE_B_DLY           0x000000F0 //4-bit value
201#define TX_RANDOM_PAYLOAD           0x00000100
202#define TX_SWAP_ANTENNAS            0x00000200
203#define TX_SOFTWARE_TXEN            0x00000400
204#define TX_EXTERNAL_TXEN            0x00000800
205#define TX_ALWAYS_USE_PRECFO        0x00001000
206#define TX_CAPTURE_RANDOM_PAYLOAD   0x00002000
207#define TX_AUTO_TWOTX_EN            0x00004000
208#define TX_START_D0_OUT_EN          0x00008000
209#define TX_START_D1_OUT_EN          0x00010000
210#define TX_ALT_INTERPFILT           0x00020000
211#define TX_CONJ_ANTB_STS            0x00040000
212#define TX_CONJ_ANTB_LTS            0x00080000
213
214//Bit masks for Tx_Delays register
215#define TX_EXTAUTO_TXEN_DLY_LSB     0 //0x000000FF //8-bit value
216#define TX_AUTOTX_EXTRA_DLY_LSB     8 //0x00000F00 //4-bit value
217#define TX_START_D_OUTPUTS_DLY_LSB  12 //0x000FF000 //8-bit value
218
219//Bit masks for the Tx/Rx status bits
220#define RXSTATUS_PKTDONE_RST    0x1
221#define RXSTATUS_HEADER_RST     0x2
222#define TXSTATUS_DONE_RST       0x4
223
224#define RXSTATUS_GOODPKT        0x8
225#define RXSTATUS_BADPKT         0x10
226#define RXSTATUS_GOODHEADER     0x20
227#define RXSTATUS_BADHEADER      0x40
228#define TXSTATUS_DONE           0x80
229
230#define ALL_STATUSBITS_ENABLE (RXSTATUS_GOODHEADER|RXSTATUS_BADHEADER|RXSTATUS_BADPKT|RXSTATUS_GOODPKT|TXSTATUS_DONE)
231#define DEFAULT_STATUSBITS (RXSTATUS_GOODHEADER|RXSTATUS_BADHEADER|RXSTATUS_BADPKT|RXSTATUS_GOODPKT)
232#define DEFAULT_STATUSBITRESETS (RXSTATUS_HEADER_RST|RXSTATUS_PKTDONE_RST|TXSTATUS_DONE_RST)
233
234//Define which radios get used
235//RADIOx_ADDR are defined by the radio controller driver
236//#define FIRST_RADIO RADIO2_ADDR
237//#define SECOND_RADIO RADIO3_ADDR
238#define BOTH_RADIOS (FIRST_RADIO | SECOND_RADIO)
239
240//Shorthand for configuring the radio controller's selected band
241#define GHZ_5 0
242#define GHZ_2 1
243
244//Bit masks for OFDM Tx status register
245#define OFDM_TX_BUSY        0x1
246#define OFDM_TX_HEADERBUSY  0x2
247
248//Bits 0xF0 are used for 4-bit preable shift value
249#define TX_SISO_ON_ANTB 0x100
250
251//MAC2PHY Options
252#define TXBLOCK     0x0
253#define TXNOBLOCK   0x1
254
255//Macros for accessing the OFDM packet buffer; buff is an integer in [0,NUMPKTBUFFS-1]
256#define warpphy_copyBytesToPhy(buff,src,len) memcpy(OFDM_PKTBUFF_BASEADDR + buff * 0x1000,(src),(len))
257#define warpphy_copyBytesFromPhy(buff,dest,len) memcpy((dest), OFDM_PKTBUFF_BASEADDR + buff * 0x1000, (len))
258
259//Macro to retrieve the physical memory address for a given packet buffer index
260// PHY packet buffers are 2048 bytes (0x800) each
261// The current PHY has 32 buffers, so the buffer index is masked to 5 bits
262//   here to avoid returning bogus buffer addresses
263#define warpphy_getBuffAddr(c) (OFDM_PKTBUFF_BASEADDR + (c & 0x1F)*(0x800))
264
265//Macros to read/write PHY registers
266#define mimo_ofdmTx_setStartTx(c)   ofdm_txrx_mimo_WriteReg_Tx_Start_Reset_Control(OFDM_BASEADDR, ( (c<<1) & TX_START) )
267#define mimo_ofdmRx_setByteNums(c) ofdm_txrx_mimo_WriteReg_Rx_pktByteNums(OFDM_BASEADDR, c)
268#define mimo_ofdmRx_setRxScaling(c) ofdm_txrx_mimo_WriteReg_Rx_Constellation_Scaling(OFDM_BASEADDR, c)
269#define mimo_ofdmRx_setLongCorrParams(c) ofdm_txrx_mimo_WriteReg_Rx_PktDet_LongCorr_Params(OFDM_BASEADDR, c)
270
271#define mimo_ofdmTx_setPilotIndcies(c) ofdm_txrx_mimo_WriteReg_TxRx_Pilots_Index(0, c)
272#define mimo_ofdmTxRx_setPilotValues(c) ofdm_txrx_mimo_WriteReg_TxRx_Pilots_Values(0, c)
273
274#define mimo_ofdmTxRx_setFECoptions(codingEn, softEn, zeroTail, scale_qpsk, scale_16qam) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_FEC_CONFIG, ( \
275    ((codingEn<<0)  & 0x1) | \
276    ((softEn<<1)    & 0x2) | \
277    ((zeroTail<<2)  & 0x4) | \
278    ((scale_qpsk<<4) & 0xF0) | \
279    ((scale_16qam<<8) & 0x1F00)))
280
281//#define warpphy_setChanEstMinMags(chanAA, chanBA) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_CHANEST_MINMAG, ( (chanAA & 0xFFFF) | ( (chanBA & 0xFFFF)<<16)))
282#define warpphy_setChanEstMinMags(estmag) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_CHANEST_MINMAG, (estmag))
283
284#define warpphy_setAFblanking(start, stop) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_AF_BLANKING, ( (start & 0xFFF) | ( (stop & 0xFFF) << 16)))
285
286#define warpphy_setTxNumSyms(numBR, numT) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TX_OFDM_SYMCOUNTS, ( (numT & 0xF) | ( (numBR & 0x1F)<<8) ) )
287#define warpphy_setRxNumSyms(numBR, numT) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_OFDM_SYMBOLCOUNTS, ( (numT & 0xF) | ( (numBR & 0x1F)<<16) ) )
288
289#define warpphy_setPreCFOoptions(c) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_PRECFO_OPTIONS, c)
290#define warpphy_getPreCFO_pktBuf(bufInd) XIo_In32( (XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTBUFFREQOFFSETS + (4*((bufInd)&0x1F))) )
291#define warpphy_setPreCFO_pktBuf(bufInd, cfoVal) XIo_Out32( (XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTBUFFREQOFFSETS + (4*((bufInd)&0x1F))), cfoVal)
292
293#define warpphy_getPreCFO_pkt_coarse() XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_COARSECFOEST)
294#define warpphy_getPreCFO_pkt_pilots() XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_PILOTCFOEST)
295#define warpphy_setPilotCFOCorrection(c) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_PRECFO_PILOTCALCCORRECTION, c)
296
297#define warpphy_setCoarseCFOCorrection(c) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_COARSECFO_CORRECTION, c)
298
299#define mimo_ofdmTx_setTxScaling(pre, pay) ofdm_txrx_mimo_WriteReg_Tx_Scaling(OFDM_BASEADDR, ((0xFFFF & pre) | (0xFFFF0000 & (pay<<16))) )
300
301#define mimo_ofdmTx_setControlBits(c) ofdm_txrx_mimo_WriteReg_Tx_ControlBits(OFDM_BASEADDR, c)
302#define mimo_ofdmTx_getOptions() ofdm_txrx_mimo_ReadReg_Tx_ControlBits(OFDM_BASEADDR)
303
304#define mimo_ofdmTx_setDelays(extTxEn, extraAutoTx, txStartOut) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TX_DELAYS, ( \
305    ( (extTxEn&0xFF)    << TX_EXTAUTO_TXEN_DLY_LSB) | \
306    ( (extraAutoTx&0xF) << TX_AUTOTX_EXTRA_DLY_LSB) | \
307    ( (txStartOut&0xFF) << TX_START_D_OUTPUTS_DLY_LSB)))
308
309#define mimo_ofdmTxRx_setFFTScaling(c) ofdm_txrx_mimo_WriteReg_TxRx_FFT_Scaling(OFDM_BASEADDR, c)
310#define mimo_ofdmRx_setFFTWindowOffset(c) ofdm_txrx_mimo_WriteReg_Rx_PktDet_Delay(OFDM_BASEADDR, (ofdm_txrx_mimo_ReadReg_Rx_PktDet_Delay(OFDM_BASEADDR) & 0xFFFFE07F) | ((c&0x3F)<<7))
311
312#define mimo_ofdmRx_setPktDetDly(c) ofdm_txrx_mimo_WriteReg_Rx_PktDet_Delay(OFDM_BASEADDR, (ofdm_txrx_mimo_ReadReg_Rx_PktDet_Delay(OFDM_BASEADDR) & 0xFFFFFF80)| (c&0x7F))
313#define mimo_ofdmRx_setCFOCalcDly(c) ofdm_txrx_mimo_WriteReg_Rx_PktDet_Delay(OFDM_BASEADDR, (ofdm_txrx_mimo_ReadReg_Rx_PktDet_Delay(OFDM_BASEADDR) & ~0x001F0000) | ( (c&0x1F)<<16 ))
314#define mimo_ofdmRx_setCFOMaxDiff(c) ofdm_txrx_mimo_WriteReg_Rx_PktDet_Delay(OFDM_BASEADDR, (ofdm_txrx_mimo_ReadReg_Rx_PktDet_Delay(OFDM_BASEADDR) & ~0xFF000000) | ( (c&0xFF)<<24 ))
315
316#define mimo_ofdmTx_setPktDoneReset(c) ofdm_txrx_mimo_WriteReg_Tx_Start_Reset_Control(OFDM_BASEADDR, (c<<2)&0x4)
317#define mimo_ofdmRx_getPayloadStatus() (PHYRXSTATUS_PAYLOAD & ofdm_txrx_mimo_ReadReg_Rx_packet_done(OFDM_BASEADDR))
318#define mimo_ofdmRx_getHeaderStatus() ((PHYRXSTATUS_HEADER & ofdm_txrx_mimo_ReadReg_Rx_packet_done(OFDM_BASEADDR)))
319#define mimo_ofdmRx_getPktStatus()  (((PHYRXSTATUS_PAYLOAD | PHYRXSTATUS_HEADER) & ofdm_txrx_mimo_ReadReg_Rx_packet_done(OFDM_BASEADDR)))
320
321#define mimo_ofdmRx_setAFTxScaling(c) ofdm_rx_mimo_WriteReg_Rx_AFScaling(0, c)
322
323#define mimo_ofdmRx_setPilotCalcParams(minMag) ofdm_rx_mimo_WriteReg_Rx_PilotCalcParams(0, (minMag & 0xFFF))
324
325//Timer Defines
326#define TIMER_A 0
327#define TIMER_B 1
328#define TIMER_C 2
329#define TIMER_D 3
330
331#define TIMER_A_DONE 0x1
332#define TIMER_B_DONE 0x100
333#define TIMER_C_DONE 0x10000
334#define TIMER_D_DONE 0x1000000
335
336#define TIMER_A_ACTIVE 0x2
337#define TIMER_B_ACTIVE 0x200
338#define TIMER_C_ACTIVE 0x20000
339#define TIMER_D_ACTIVE 0x2000000
340
341#define TIMER_A_PAUSED 0x4
342#define TIMER_B_PAUSED 0x400
343#define TIMER_C_PAUSED 0x40000
344#define TIMER_D_PAUSED 0x4000000
345
346//Byte indicies of various header fields (used for the autoRepsonse setup)
347#define PKTHEADER_INDX_SRCADDR  4
348#define PKTHEADER_INDX_DSTADDR  6
349#define PKTHEADER_INDX_RLYADDR  8
350#define PKTHEADER_INDX_TYPE     10
351#define PKTHEADER_INDX_RETX     11
352#define PKTHEADER_INDX_SEQ      12
353#define PKTHEADER_INDX_PREVCHECK 20
354#define PKTHEADER_INDX_CHECK    22
355
356///Structure contains PHY header
357typedef struct {
358    ///Full-rate modulation order
359    unsigned char fullRate;     //0
360    ///Rate for convolutional error correction code
361    unsigned char codeRate;         //1
362    ///The length of the packet (in bytes). NOTE: This should only specify the length of the payload to-be-sent.
363    unsigned short int length;      //2
364    ///Source MAC address.
365    unsigned short int srcAddr;     //4
366    ///Destination MAC address.
367    unsigned short int destAddr;    //6
368    ///Relay MAC address.
369    unsigned short int relAddr;     //8
370    ///Type of packet this particular Macframe corresponds to (e.g. DATA, ACKPACKET, etc.)
371    unsigned char pktType;          //10
372    ///Reserved byte
373    unsigned char remainingTx;      //11
374    ///Sequence number of this packet
375    unsigned int seqNum;            //12-15
376    ///Reserved byte
377    unsigned short int timeLeft;
378    unsigned char cogParam;
379    unsigned char reserved0;
380    unsigned char reserved1; //20
381    unsigned char reserved2; //21
382
383    ///Checksum of the packet will be automatically inserted by PHY
384    unsigned short int checksum;    //22
385} phyHeader;
386
387//Prototypes for functions in warpphy.c
388int warpphy_init();
389void warpphy_clearRxInterrupts();
390void warpphy_clearTxInterrupts();
391int warpphy_pktTx(unsigned int block);
392void mimo_ofdmRx_enable();
393void mimo_ofdmRx_disable();
394void mimo_ofdmRx_setOptions(unsigned int someOptions, unsigned int intType);
395unsigned int mimo_ofdmRx_getOptions();
396void mimo_ofdmTx_disable();
397void mimo_ofdmTx_enable();
398void warpphy_setBuffs(unsigned char txBufOffset, unsigned char rxBufOffset);
399void warpphy_setNumTrainingSyms(unsigned int numTraining);
400void warpphy_setPktDlyPlus();
401void warpphy_setPktDlyMinus();
402void warpphy_set_PN_KPlus(unsigned int increment);
403void warpphy_set_PN_KMinus(unsigned int decrement);
404void warpphy_set_CFODebugOutput(unsigned char outputSel);
405void print_CFO_constants();
406void warpphy_set_B_KPPlus(unsigned int increment);
407void warpphy_set_B_KPMinus(unsigned int decrement);
408void warpphy_set_B_KIPlus(unsigned int increment);
409void warpphy_set_B_KIMinus(unsigned int decrement);
410void warpphy_set_FFTOffset_Plus();
411void warpphy_set_FFTOffset_Minus();
412void warpphy_setNoiseTargetPlus();
413void warpphy_setNoiseTargetMinus();
414void warpphy_setTargetPlus();
415void warpphy_setTargetMinus();
416void warpphy_set_modulation(unsigned char baseRate, unsigned char TxAntAFullRate, unsigned char TxAntBFullRate, unsigned char RxAntAFullRate, unsigned char RxAntBFullRate);
417int warpphy_setChannel(unsigned char band, unsigned int chan);
418int warpphy_applyTxDCOCorrection(unsigned int radioSelection);
419void warpphy_clearRxHeaderInterrupt();
420void warpphy_setPktDetPlus(unsigned int offset);
421void warpphy_setPktDetMinus(unsigned int offset);
422void warpphy_setCSMAPlus(unsigned int offset);
423void warpphy_setCSMAMinus(unsigned int offset);
424int warpphy_isFree();
425char warpphy_pollRxStatus(unsigned char type);
426void ofdm_AGC_SetTarget(unsigned int target);
427inline void ofdm_AGC_SetDCO(unsigned int AGCstate);
428void ofdm_AGC_Reset();
429void ofdm_AGC_MasterReset();
430void ofdm_AGC_Initialize(int noise_estimate);
431void ofdm_AGC_setNoiseEstimate(int noise_estimate);
432unsigned int ofdm_AGC_GetGains(void);
433void ofdm_timer_start();
434void ofdm_timer_stop();
435void ofdm_timer_clearInterrupt();
436int warpphy_setTxPower(unsigned char txPwr);
437int warpphy_setAntennaMode(unsigned int txMode, unsigned int rxMode);
438void warpphy_incrementTxScaling(int incr_preamble, int incr_payload);
439void warpphy_setLongCorrThresh(unsigned short thresh);
440void warpphy_setEnergyDetThresh(unsigned short thresh);
441void warpphy_clearAutoResponseFlag(unsigned char flagID);
442void warpphy_setAntBPreambleShift(unsigned char shift);
443void warpphy_AFrecordEnable(unsigned char recordEn);
444void warpphy_setNumBaseRateSyms(unsigned int numSyms);
445void warpphy_setAutoCorrDetParams(unsigned short corrThresh, unsigned short energyThresh);
446void warpphy_setCarrierSenseThresh(unsigned short thresh);
447void warpphy_clearRxPktStatus();
448int warpphy_waitForTx();
449int warpphy_applyTxDCOCalibration();
450
451//warp_timer function prototypes
452void warp_timer_start(unsigned char timer);
453void warp_timer_pause(unsigned char timer);
454void warp_timer_resume(unsigned char timer);
455void warp_timer_setMode(unsigned char timer, unsigned char mode);
456void warp_timer_resetDone(unsigned char timer);
457void warp_timer_resetAllDoneStatus();
458void warp_timer_setTimer(unsigned char timer, unsigned int slotTime, unsigned int slotCount);
459void warp_timer_init();
460unsigned char warp_timer_getStatus(unsigned char timer);
461unsigned char warp_timer_isDone(unsigned char timer);
462unsigned char warp_timer_isActive(unsigned char timer);
463unsigned char warp_timer_isPaused(unsigned char timer);
464unsigned int warp_timer_getStatuses();
465unsigned char warp_timer_getDoneStatus();
466void warpphy_saveAFpkt(unsigned char doSave);
467int warpphy_setTxAntennaSwap(unsigned int txMode);
468unsigned int warpphy_returnGainsDB();
469
470//Register access macros
471#define mimo_ofdmTxRx_getAction0() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION0))
472#define mimo_ofdmTxRx_getAction1() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION1))
473#define mimo_ofdmTxRx_getAction2() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION2))
474#define mimo_ofdmTxRx_getAction3() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION3))
475#define mimo_ofdmTxRx_getAction4() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION4))
476#define mimo_ofdmTxRx_getAction5() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION5))
477#define mimo_ofdmTxRx_getAction6() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION6))
478#define mimo_ofdmTxRx_getAction7() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION7))
479
480#define mimo_ofdmTxRx_setAction0(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION0, d))
481#define mimo_ofdmTxRx_setAction1(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION1, d))
482#define mimo_ofdmTxRx_setAction2(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION2, d))
483#define mimo_ofdmTxRx_setAction3(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION3, d))
484#define mimo_ofdmTxRx_setAction4(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION4, d))
485#define mimo_ofdmTxRx_setAction5(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION5, d))
486#define mimo_ofdmTxRx_setAction6(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION6, d))
487#define mimo_ofdmTxRx_setAction7(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION7, d))
488
489#define mimo_ofdmTxRx_getMatch0() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH0))
490#define mimo_ofdmTxRx_getMatch1() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH1))
491#define mimo_ofdmTxRx_getMatch2() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH2))
492#define mimo_ofdmTxRx_getMatch3() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH3))
493#define mimo_ofdmTxRx_getMatch4() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH4))
494#define mimo_ofdmTxRx_getMatch5() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH5))
495#define mimo_ofdmTxRx_getMatch6() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH6))
496#define mimo_ofdmTxRx_getMatch7() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH7))
497
498#define mimo_ofdmTxRx_setMatch0(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH0, d))
499#define mimo_ofdmTxRx_setMatch1(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH1, d))
500#define mimo_ofdmTxRx_setMatch2(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH2, d))
501#define mimo_ofdmTxRx_setMatch3(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH3, d))
502#define mimo_ofdmTxRx_setMatch4(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH4, d))
503#define mimo_ofdmTxRx_setMatch5(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH5, d))
504#define mimo_ofdmTxRx_setMatch6(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH6, d))
505#define mimo_ofdmTxRx_setMatch7(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH7, d))
506
507//Match definition fields for match units 0-5 (comparison of incoming header with static value)
508#define PHY_AUTORESPONSE_MATCH_BYTEADDR_MASK    0x0000001F
509#define PHY_AUTORESPONSE_MATCH_BYTEADDR_OFFSET  0
510
511#define PHY_AUTORESPONSE_MATCH_LENGTH_MASK      0x00000060
512#define PHY_AUTORESPONSE_MATCH_LENGTH_OFFSET    5
513
514#define PHY_AUTORESPONSE_MATCH_VALUE_MASK       0xFFFFFF00
515#define PHY_AUTORESPONSE_MATCH_VALUE_OFFSET     8
516
517#define PHY_AUTORESPONSE_MATCH_VALUE_MAP(c)     ((c<<PHY_AUTORESPONSE_MATCH_VALUE_OFFSET) & PHY_AUTORESPONSE_MATCH_VALUE_MASK)
518#define PHY_AUTORESPONSE_MATCH_LENGTH_MAP(c)    ((c<<PHY_AUTORESPONSE_MATCH_LENGTH_OFFSET) & PHY_AUTORESPONSE_MATCH_LENGTH_MASK)
519#define PHY_AUTORESPONSE_MATCH_BYTEADDR_MAP(c)  ((c<<PHY_AUTORESPONSE_MATCH_BYTEADDR_OFFSET) & PHY_AUTORESPONSE_MATCH_BYTEADDR_MASK)
520
521#define PHY_AUTORESPONSE_MATCH_CONFIG(addr, len, val) (PHY_AUTORESPONSE_MATCH_BYTEADDR_MAP(addr) | PHY_AUTORESPONSE_MATCH_LENGTH_MAP(len) | PHY_AUTORESPONSE_MATCH_VALUE_MAP(val))
522
523//Match definition fields for match units 6-7 (comparison of incoming header with previously received header corresponding to saved waveform)
524#define PHY_AUTORESPONSE_MATCH_RXADDR0_OFFSET       0
525#define PHY_AUTORESPONSE_MATCH_RXADDR0_MASK         (0x0000001F<< PHY_AUTORESPONSE_MATCH_RXADDR0_OFFSET)
526#define PHY_AUTORESPONSE_MATCH_PREVADDR0_OFFSET     5
527#define PHY_AUTORESPONSE_MATCH_PREVADDR0_MASK       (0x0000001F<< PHY_AUTORESPONSE_MATCH_PREVADDR0_OFFSET)
528
529#define PHY_AUTORESPONSE_MATCH_RXADDR1_OFFSET       10
530#define PHY_AUTORESPONSE_MATCH_RXADDR1_MASK         (0x0000001F<< PHY_AUTORESPONSE_MATCH_RXADDR1_OFFSET)
531#define PHY_AUTORESPONSE_MATCH_PREVADDR1_OFFSET     15
532#define PHY_AUTORESPONSE_MATCH_PREVADDR1_MASK       (0x0000001F<< PHY_AUTORESPONSE_MATCH_PREVADDR1_OFFSET)
533#define PHY_AUTORESPONSE_MATCH_ADDR1_EN             0x40000000
534
535#define PHY_AUTORESPONSE_MATCH_RXADDR2_OFFSET       20
536#define PHY_AUTORESPONSE_MATCH_RXADDR2_MASK         (0x0000001F<< PHY_AUTORESPONSE_MATCH_RXADDR2_OFFSET)
537#define PHY_AUTORESPONSE_MATCH_PREVADDR2_OFFSET     25
538#define PHY_AUTORESPONSE_MATCH_PREVADDR2_MASK       (0x0000001F<< PHY_AUTORESPONSE_MATCH_PREVADDR2_OFFSET)
539#define PHY_AUTORESPONSE_MATCH_ADDR2_EN             0x80000000
540
541//Macro to help define header comparison match configuration registers
542#define PHY_AUTORESPONSE_MATCH_HDRCOMP_CONFIG(rxAddr0, prevAddr0, rxAddr1, prevAddr1, useAddr1, rxAddr2, prevAddr2, useAddr2) (\
543( (rxAddr0 << PHY_AUTORESPONSE_MATCH_RXADDR0_OFFSET) & PHY_AUTORESPONSE_MATCH_RXADDR0_MASK) | \
544( (rxAddr1 << PHY_AUTORESPONSE_MATCH_RXADDR1_OFFSET) & PHY_AUTORESPONSE_MATCH_RXADDR1_MASK) | \
545( (rxAddr2 << PHY_AUTORESPONSE_MATCH_RXADDR2_OFFSET) & PHY_AUTORESPONSE_MATCH_RXADDR2_MASK) | \
546( (prevAddr0 << PHY_AUTORESPONSE_MATCH_PREVADDR0_OFFSET) & PHY_AUTORESPONSE_MATCH_PREVADDR0_MASK) | \
547( (prevAddr1 << PHY_AUTORESPONSE_MATCH_PREVADDR1_OFFSET) & PHY_AUTORESPONSE_MATCH_PREVADDR1_MASK) | \
548( (prevAddr2 << PHY_AUTORESPONSE_MATCH_PREVADDR2_OFFSET) & PHY_AUTORESPONSE_MATCH_PREVADDR2_MASK) | \
549( useAddr1 ? PHY_AUTORESPONSE_MATCH_ADDR1_EN : 0) | \
550( useAddr2 ? PHY_AUTORESPONSE_MATCH_ADDR2_EN : 0) )
551
552
553//Action fields
554#define PHY_AUTORESPONSE_ACT_ID_MASK    0x00FC0000
555#define PHY_AUTORESPONSE_ACT_ID_OFFSET  18
556
557#define PHY_AUTORESPONSE_ACT_PARAM_MASK     0xFF000000
558#define PHY_AUTORESPONSE_ACT_PARAM_OFFSET   24
559#define PHY_AUTORESPONSE_MAP_ACT_PARAM(c)   ((c<<PHY_AUTORESPONSE_ACT_PARAM_OFFSET) & PHY_AUTORESPONSE_ACT_PARAM_MASK)
560
561#define PHY_AUTORESPONSE_ACT_TRANS_HDR  0x00010000
562#define PHY_AUTORESPONSE_ACT_USE_PRECFO 0x00020000
563#define PHY_AUTORESPONSE_ACT_RETX_CRC   0x00000200
564#define PHY_AUTORESPONSE_ACT_SWAP_ANT   0x00000400
565
566#define PHY_AUTORESPONSE_REQ_GOODHDR    0x000800
567#define PHY_AUTORESPONSE_REQ_BADPKT     0x001000
568#define PHY_AUTORESPONSE_REQ_GOODPKT    0x002000
569
570#define PHY_AUTORESPONSE_REQ_FLAGA      0x004000
571#define PHY_AUTORESPONSE_REQ_FLAGB      0x008000
572
573#define PHY_AUTORESPONSE_REQ_MATCH0     0x001
574#define PHY_AUTORESPONSE_REQ_MATCH1     0x002
575#define PHY_AUTORESPONSE_REQ_MATCH2     0x004
576#define PHY_AUTORESPONSE_REQ_MATCH3     0x008
577#define PHY_AUTORESPONSE_REQ_MATCH4     0x010
578#define PHY_AUTORESPONSE_REQ_MATCH5     0x020
579#define PHY_AUTORESPONSE_REQ_MATCH6     0x040
580#define PHY_AUTORESPONSE_REQ_MATCH7     0x080
581
582#define PHY_AUTORESPONSE_REQ_MATCHALL   (PHY_AUTORESPONSE_REQ_MATCH0 | PHY_AUTORESPONSE_REQ_MATCH1 | PHY_AUTORESPONSE_REQ_MATCH2 | PHY_AUTORESPONSE_REQ_MATCH3 | PHY_AUTORESPONSE_REQ_MATCH4 | PHY_AUTORESPONSE_REQ_MATCH5 | PHY_AUTORESPONSE_REQ_MATCH6 | PHY_AUTORESPONSE_REQ_MATCH7)
583#define PHY_AUTORESPONSE_REQ_ALLCONDS   (PHY_AUTORESPONSE_REQ_MATCHALL | PHY_AUTORESPONSE_REQ_FLAGA | PHY_AUTORESPONSE_REQ_FLAGB | PHY_AUTORESPONSE_REQ_GOODHDR | PHY_AUTORESPONSE_REQ_BADPKT | PHY_AUTORESPONSE_REQ_GOODPKT)
584
585//ActionIDs
586#define PHY_AUTORESPONSE_ACTID_DISABLED     ((00<<PHY_AUTORESPONSE_ACT_ID_OFFSET) & PHY_AUTORESPONSE_ACT_ID_MASK)
587#define PHY_AUTORESPONSE_ACTID_SETFLAGA     ((62<<PHY_AUTORESPONSE_ACT_ID_OFFSET) & PHY_AUTORESPONSE_ACT_ID_MASK)
588#define PHY_AUTORESPONSE_ACTID_SETFLAGB     ((61<<PHY_AUTORESPONSE_ACT_ID_OFFSET) & PHY_AUTORESPONSE_ACT_ID_MASK)
589#define PHY_AUTORESPONSE_ACTID_TXPKTBUF(c)  ((   c<<PHY_AUTORESPONSE_ACT_ID_OFFSET) & PHY_AUTORESPONSE_ACT_ID_MASK)
590
591#define PHY_HEADERTRANSLATE_SET(actionBuf, txByteNum, srcBuf, srcByteNum) \
592    XIo_Out32(\
593    (XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXHEADERTRANSLATE + ((actionBuf)*32*sizeof(int)) + ((txByteNum)*sizeof(int))),\
594    (((srcBuf) & 0x1F)<<5) | ((srcByteNum) & 0x1F))
595
596//Macro to help construct autoResponse Tx actions
597#define PHY_AUTORESPONSE_TXACTION_CONFIG(pktBuf, actionOptions, delay, conditions) (\
598    (PHY_AUTORESPONSE_ACTID_TXPKTBUF(pktBuf) ) | \
599    (actionOptions & (PHY_AUTORESPONSE_ACT_SWAP_ANT | PHY_AUTORESPONSE_ACT_TRANS_HDR | PHY_AUTORESPONSE_ACT_USE_PRECFO)) | \
600    (PHY_AUTORESPONSE_MAP_ACT_PARAM(delay) ) | \
601    (conditions & (PHY_AUTORESPONSE_REQ_ALLCONDS)))
602
603//Macro to help construct autoResponse action for setting Flag A
604#define PHY_AUTORESPONSE_ACTION_SETFLAGA_CONFIG(conditions) (PHY_AUTORESPONSE_ACTID_SETFLAGA | (conditions & (PHY_AUTORESPONSE_REQ_ALLCONDS)))
605
606//Macro to help construct autoResponse action for setting Flag B
607#define PHY_AUTORESPONSE_ACTION_SETFLAGB_CONFIG(conditions) (PHY_AUTORESPONSE_ACTID_SETFLAGB | (conditions & (PHY_AUTORESPONSE_REQ_ALLCONDS)))
608
609//Flag IDs for user functions
610#define AUTORESP_FLAGID_A 1
611#define AUTORESP_FLAGID_B 2
612
613#endif
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