source: PlatformSupport/WARPMAC/warpphy.h

Last change on this file was 1712, checked in by murphpo, 8 years ago

Updating code for OFDM ref design v17 in ISE 13.4 tools

File size: 29.2 KB
Line 
1/*! \file warpphy.h
2\brief Header file for the WARPPHY functions
3
4@version 15.22
5@author Patrick Murphy and Chris Hunter
6
7This header file contains the macros, function prototypes, and typedefs required for WARPPHY.
8*/
9
10//WARPPHY Interface
11/***************CHANGELOG*****************
12
13******************************************/
14/*****************WARPPHY*****************
15Description: This file specifies the
16interface between to the PHY.
17******************************************/
18
19#ifndef WARPPHY_H
20#define WARPPHY_H
21
22//Flag to include a bunch of low-level debugging functions
23// for tweaking values in the PHY cores
24// These can be excluded for most applications, saving a lot of code space
25#define INCLUDE_WARPPHY_DEBUG_FUNCTIONS 0
26
27//Old design flow used OFDM_BASEADDR to refer to the PHY's base address
28// New flow addresses registers directly, not relative to a base address
29// This value is still defined to keep code from breaking
30#define OFDM_BASEADDR 0
31
32//PHY packet buffer is actually a PLB BRAM
33// The base address is the address of the PLB BRAM controller
34#define OFDM_PKTBUFF_BASEADDR XPAR_XPS_BRAM_IF_CNTLR_2_BASEADDR
35
36//Masks for configuring modulation settings in the PHY
37//Each is 8 copies of a 4-bit modulation value
38#define MODMASK_BPSK 0x11111111
39#define MODMASK_QPSK 0x22222222
40#define MODMASK_16QAM 0x44444444
41#define MODMASK_64QAM 0x66666666
42
43#define MOD_UNCHANGED 0xFF
44
45#define NUM_BASERATE_SYMBOLS_BPSK_CODED 8
46#define NUM_BASERATE_SYMBOLS_QPSK_CODED 4
47#define NUM_BASERATE_SYMBOLS_BPSK_UNCODED 4
48#define NUM_BASERATE_SYMBOLS_QPSK_UNCODED 2
49
50//Number of base rate OFDM symbols per packet
51// Must correspond to base rate modulation, number of header bytes and header coding rate
52#define NUM_BASERATE_SYMBOLS NUM_BASERATE_SYMBOLS_QPSK_CODED
53
54//Define number of channel training symbols per packet - must be even!
55// In SISO mode all symbols are used to train the H_AA channel
56// In Alamouti, alternate symbols train H_AA and H_BA
57// In 2x2, alternate symbols train H_AA/H_AB and H_BA/H_BB
58#define NUM_TRAINING_SYMBOLS    2
59
60//Number of packet buffers; each sub-buffer is 2KB, so a 64KB PLB BRAM hold 32 buffers
61#define NUMPKTBUFFS 32
62
63//Length of the running RSSI sum in the pkt detector
64// #define'd here so it can be used again below
65#define PKTDET_RSSI_SUMLEN      16
66
67//Define an RSSI threshold big enough so that carrier sensing will never assert
68// This is used to "disable" carrier sensing at run time
69#define CSMA_DISABLED_THRESH    (1023*PKTDET_RSSI_SUMLEN)
70
71//Initial FFT window offset (number of CP samples to use per Rx FFT)
72#define INIT_RXFFTOFSET 10
73
74//Code rate selection values, used in header.codeRate field per-packet
75//#define CONVCODED_PHY 1
76#define HDR_CODE_RATE_12 0
77#define HDR_CODE_RATE_23 1
78#define HDR_CODE_RATE_34 2
79#define HDR_CODE_RATE_NONE 3
80
81#define TIMER_MODE_CARRIERSENSE     1
82#define TIMER_MODE_NOCARRIERSENSE   0
83
84//Define scaling values for the PHY's FFT cores
85#define TX_FFT_SCALING_STAGE1 1
86#define TX_FFT_SCALING_STAGE2 2
87#define TX_FFT_SCALING_STAGE3 3
88
89// Was 1 2 1
90#define RX_FFT_SCALING_STAGE1 0
91#define RX_FFT_SCALING_STAGE2 1
92#define RX_FFT_SCALING_STAGE3 1
93
94//Define thresholds for the AGC
95#define AGC_THRESH_1 0xE2 //-30
96#define AGC_THRESH_2 0xCB //-53
97#define AGC_THRESH_3 0xA6 //-90
98
99//RX Status register values
100#define PHYRXSTATUS_INCOMPLETE 0
101#define PHYRXSTATUS_GOOD 0x5
102#define PHYRXSTATUS_BAD 0xA
103#define PHYRXSTATUS_PAYLOAD 0x3
104#define PHYRXSTATUS_HEADER 0xC
105
106//Antenna configuration constants
107#define ANTMODE_UNCHANGED           0
108
109#define ANTMODE_MASK_ANTSEL         0x00F
110#define ANTMODE_MASK_PHYMODE        0x0F0
111#define ANTMODE_MASK_PHYANTCFG      0xF00
112
113#define ANTMODE_ANTSEL_RADA         0x001
114#define ANTMODE_ANTSEL_RADB         0x002
115#define ANTMODE_ANTSEL_BOTHRADS     (ANTMODE_ANTSEL_RADA | ANTMODE_ANTSEL_RADB)
116
117#define PHYMODE_SISO                0x010
118#define PHYMODE_ALAMOUTI            0x020
119#define PHYMODE_2X2MULT             0x040
120
121#define PHYANTCFG_TX_NORMAL         0x100
122#define PHYANTCFG_TX_SWAPPED        0x200
123
124#define PHYANTCFG_RX_NORMAL         0x100
125#define PHYANTCFG_RX_SWAPPED        0x200
126#define PHYANTCFG_RX_SELDIV         0x400
127
128#define TX_ANTMODE_SISO_ANTA                (ANTMODE_ANTSEL_RADA | PHYMODE_SISO | PHYANTCFG_TX_NORMAL)
129#define TX_ANTMODE_SISO_ANTB                (ANTMODE_ANTSEL_RADB | PHYMODE_SISO | PHYANTCFG_TX_SWAPPED)
130#define TX_ANTMODE_MULTPLX                  (ANTMODE_ANTSEL_BOTHRADS | PHYMODE_2X2MULT | PHYANTCFG_TX_NORMAL)
131#define TX_ANTMODE_MULTPLX_SWAPPED          (ANTMODE_ANTSEL_BOTHRADS | PHYMODE_2X2MULT | PHYANTCFG_TX_SWAPPED)
132#define TX_ANTMODE_ALAMOUTI_2ANT            (ANTMODE_ANTSEL_BOTHRADS | PHYMODE_ALAMOUTI | PHYANTCFG_TX_NORMAL)
133#define TX_ANTMODE_ALAMOUTI_2ANT_SWAPPED    (ANTMODE_ANTSEL_BOTHRADS | PHYMODE_ALAMOUTI | PHYANTCFG_TX_SWAPPED)
134#define TX_ANTMODE_ALAMOUTI_ANTA            (ANTMODE_ANTSEL_RADA | PHYMODE_ALAMOUTI | PHYANTCFG_TX_NORMAL)
135#define TX_ANTMODE_ALAMOUTI_ANTB            (ANTMODE_ANTSEL_RADB | PHYMODE_ALAMOUTI | PHYANTCFG_TX_NORMAL)
136#define TX_ANTMODE_ALAMOUTI_ANTA_SWAPPED    (ANTMODE_ANTSEL_RADA | PHYMODE_ALAMOUTI | PHYANTCFG_TX_SWAPPED)
137#define TX_ANTMODE_ALAMOUTI_ANTB_SWAPPED    (ANTMODE_ANTSEL_RADB | PHYMODE_ALAMOUTI | PHYANTCFG_TX_SWAPPED)
138
139#define RX_ANTMODE_SISO_ANTA                (ANTMODE_ANTSEL_RADA | PHYMODE_SISO | PHYANTCFG_RX_NORMAL)
140#define RX_ANTMODE_SISO_ANTB                (ANTMODE_ANTSEL_RADB | PHYMODE_SISO | PHYANTCFG_RX_SWAPPED)
141#define RX_ANTMODE_SISO_SELDIV              (ANTMODE_ANTSEL_BOTHRADS | PHYMODE_SISO | PHYANTCFG_RX_SELDIV)
142#define RX_ANTMODE_MULTPLX                  (ANTMODE_ANTSEL_BOTHRADS | PHYMODE_2X2MULT | PHYANTCFG_RX_NORMAL)
143#define RX_ANTMODE_ALAMOUTI_ANTA            (ANTMODE_ANTSEL_RADA | PHYMODE_ALAMOUTI | PHYANTCFG_RX_NORMAL)
144#define RX_ANTMODE_ALAMOUTI_ANTB            (ANTMODE_ANTSEL_RADB | PHYMODE_ALAMOUTI | PHYANTCFG_RX_SWAPPED)
145#define RX_ANTMODE_ALAMOUTI_SELDIV          (ANTMODE_ANTSEL_BOTHRADS | PHYMODE_ALAMOUTI | PHYANTCFG_RX_SELDIV)
146
147//Bit masks for the options configured in Rx_ControlBits
148#define RESET_BER           0x1
149#define REQ_LONG_CORR       0x2
150//#define UNUSED            0x4
151#define BIG_PKTBUF_MODE     0x8
152#define RX_SISO_MODE        0x10
153//#define UNUSED            0x20
154//#define UNUSED            0x40
155#define RECORD_CHAN_ESTS    0x80
156#define RECORD_CHAN_ESTMAGS 0x100
157#define BYPASS_CARR_REC     0x200
158#define COARSE_CFO_EN       0x400
159#define EXT_PKTDETRESET_EN  0x800
160#define RSSI_GAIN_ADJ       0x1000
161#define EQ_BYPASS_DIVISION  0x4000
162#define TX_DISABLE_PKTDET   0x8000
163#define SIMPLE_DYN_MOD_EN   0x10000
164#define SWITCHING_DIV_EN    0x20000
165#define SISO_ON_ANTB        0x40000
166#define RESET_ON_BAD_HDR    0x80000
167#define RX_ALAMOUTI_MODE    0x100000
168#define FLEX_BER_MODE       0x200000
169#define BER_IGNORE_HDR      0x400000
170#define PHY_RADIO_RXEN      0x1000000
171#define AF_SAVEWAVEFORM     0x2000000
172#define AUTORESP_FLAGA_RST  0x4000000
173#define AUTORESP_FLAGB_RST  0x8000000
174#define COARSECFO_PKTDET_EN 0x10000000
175#define CHANMAG_MASKING_EN  0x20000000
176//#define UNUSED            0x40000000
177#define RX_GLOBAL_RESET     0x80000000
178
179//Bit masks for PreCFO_Options register
180#define PRECFO_USECOARSE    0x00000001
181#define PRECFO_USEPILOTS    0x00000002
182
183//Bit masks for Tx Start/Reset register
184#define TX_MASTER_RESET     0x1
185#define TX_START            0x2
186
187//Bit masks for OFDM Tx options
188#define TX_SISO_MODE                0x00000001
189#define TX_ALAMOUTI_MODE            0x00000002
190#define TX_DISABLE_ANTB_PREAMBLE    0x00000004
191#define TX_PILOT_SCRAMBLING         0x00000008
192#define TX_PREAMBLE_B_DLY           0x000000F0 //4-bit value
193#define TX_RANDOM_PAYLOAD           0x00000100
194#define TX_SWAP_ANTENNAS            0x00000200
195#define TX_SOFTWARE_TXEN            0x00000400
196#define TX_EXTERNAL_TXEN            0x00000800
197#define TX_ALWAYS_USE_PRECFO        0x00001000
198#define TX_CAPTURE_RANDOM_PAYLOAD   0x00002000
199#define TX_AUTO_TWOTX_EN            0x00004000
200#define TX_START_D0_OUT_EN          0x00008000
201#define TX_START_D1_OUT_EN          0x00010000
202#define TX_ALT_INTERPFILT           0x00020000
203#define TX_CONJ_ANTB_STS            0x00040000
204#define TX_CONJ_ANTB_LTS            0x00080000
205
206//Bit masks for Tx_Delays register
207#define TX_EXTAUTO_TXEN_DLY_LSB     0 //0x000000FF //8-bit value
208#define TX_AUTOTX_EXTRA_DLY_LSB     8 //0x00000F00 //4-bit value
209#define TX_START_D_OUTPUTS_DLY_LSB  12 //0x000FF000 //8-bit value
210
211//Bit masks for the Tx/Rx status bits
212#define RXSTATUS_PKTDONE_RST    0x1
213#define RXSTATUS_HEADER_RST     0x2
214#define TXSTATUS_DONE_RST       0x4
215
216#define RXSTATUS_GOODPKT        0x8
217#define RXSTATUS_BADPKT         0x10
218#define RXSTATUS_GOODHEADER     0x20
219#define RXSTATUS_BADHEADER      0x40
220#define TXSTATUS_DONE           0x80
221
222#define ALL_STATUSBITS_ENABLE (RXSTATUS_GOODHEADER|RXSTATUS_BADHEADER|RXSTATUS_BADPKT|RXSTATUS_GOODPKT|TXSTATUS_DONE)
223#define DEFAULT_STATUSBITS (RXSTATUS_GOODHEADER|RXSTATUS_BADHEADER|RXSTATUS_BADPKT|RXSTATUS_GOODPKT)
224#define DEFAULT_STATUSBITRESETS (RXSTATUS_HEADER_RST|RXSTATUS_PKTDONE_RST|TXSTATUS_DONE_RST)
225
226//Define which radios get used
227//RADIOx_ADDR are defined by the radio controller driver
228#define FIRST_RADIO RADIO2_ADDR
229#define SECOND_RADIO RADIO3_ADDR
230#define BOTH_RADIOS (FIRST_RADIO | SECOND_RADIO)
231
232//Shorthand for configuring the radio controller's selected band
233#define GHZ_5 0
234#define GHZ_2 1
235
236//Bit masks for OFDM Tx status register
237#define OFDM_TX_BUSY        0x1
238#define OFDM_TX_HEADERBUSY  0x2
239
240//Bits 0xF0 are used for 4-bit preable shift value
241#define TX_SISO_ON_ANTB 0x100
242
243//MAC2PHY Options
244#define TXBLOCK     0x0
245#define TXNOBLOCK   0x1
246
247//Macros for accessing the OFDM packet buffer; buff is an integer in [0,NUMPKTBUFFS-1]
248#define warpphy_copyBytesToPhy(buff,src,len) memcpy(OFDM_PKTBUFF_BASEADDR + buff * 0x1000,(src),(len))
249#define warpphy_copyBytesFromPhy(buff,dest,len) memcpy((dest), OFDM_PKTBUFF_BASEADDR + buff * 0x1000, (len))
250
251//Macro to retrieve the physical memory address for a given packet buffer index
252// PHY packet buffers are 2048 bytes (0x800) each
253// The current PHY has 32 buffers, so the buffer index is masked to 5 bits
254//   here to avoid returning bogus buffer addresses
255#define warpphy_getBuffAddr(c) (OFDM_PKTBUFF_BASEADDR + (c & 0x1F)*(0x800))
256
257//Macros to read/write PHY registers
258#define mimo_ofdmTx_setStartTx(c)   ofdm_txrx_mimo_WriteReg_Tx_Start_Reset_Control(OFDM_BASEADDR, ( (c<<1) & TX_START) )
259#define mimo_ofdmRx_setByteNums(c) ofdm_txrx_mimo_WriteReg_Rx_pktByteNums(OFDM_BASEADDR, c)
260#define mimo_ofdmRx_setRxScaling(c) ofdm_txrx_mimo_WriteReg_Rx_Constellation_Scaling(OFDM_BASEADDR, c)
261#define mimo_ofdmRx_setLongCorrParams(c) ofdm_txrx_mimo_WriteReg_Rx_PktDet_LongCorr_Params(OFDM_BASEADDR, c)
262
263#define mimo_ofdmTx_setPilotIndcies(c) ofdm_txrx_mimo_WriteReg_TxRx_Pilots_Index(0, c)
264#define mimo_ofdmTxRx_setPilotValues(c) ofdm_txrx_mimo_WriteReg_TxRx_Pilots_Values(0, c)
265
266#define mimo_ofdmTxRx_setFECoptions(codingEn, softEn, zeroTail, scale_qpsk, scale_16qam) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_FEC_CONFIG, ( \
267    ((codingEn<<0)  & 0x1) | \
268    ((softEn<<1)    & 0x2) | \
269    ((zeroTail<<2)  & 0x4) | \
270    ((scale_qpsk<<4) & 0xF0) | \
271    ((scale_16qam<<8) & 0x1F00)))
272
273//#define warpphy_setChanEstMinMags(chanAA, chanBA) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_CHANEST_MINMAG, ( (chanAA & 0xFFFF) | ( (chanBA & 0xFFFF)<<16)))
274#define warpphy_setChanEstMinMags(estmag) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_CHANEST_MINMAG, (estmag))
275
276#define warpphy_setAFblanking(start, stop) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_AF_BLANKING, ( (start & 0xFFF) | ( (stop & 0xFFF) << 16)))
277
278#define warpphy_setTxNumSyms(numBR, numT) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TX_OFDM_SYMCOUNTS, ( (numT & 0xF) | ( (numBR & 0x1F)<<8) ) )
279#define warpphy_setRxNumSyms(numBR, numT) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_OFDM_SYMBOLCOUNTS, ( (numT & 0xF) | ( (numBR & 0x1F)<<16) ) )
280
281#define warpphy_setPreCFOoptions(c) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_PRECFO_OPTIONS, c)
282#define warpphy_getPreCFO_pktBuf(bufInd) XIo_In32( (XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTBUFFREQOFFSETS + (4*((bufInd)&0x1F))) )
283#define warpphy_setPreCFO_pktBuf(bufInd, cfoVal) XIo_Out32( (XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTBUFFREQOFFSETS + (4*((bufInd)&0x1F))), cfoVal)
284
285#define warpphy_getPreCFO_pkt_coarse() XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_COARSECFOEST)
286#define warpphy_getPreCFO_pkt_pilots() XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_PILOTCFOEST)
287#define warpphy_setPilotCFOCorrection(c) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_PRECFO_PILOTCALCCORRECTION, c)
288
289#define warpphy_setCoarseCFOCorrection(c) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_COARSECFO_CORRECTION, c)
290
291#define mimo_ofdmTx_setTxScaling(pre, pay) ofdm_txrx_mimo_WriteReg_Tx_Scaling(OFDM_BASEADDR, ((0xFFFF & pre) | (0xFFFF0000 & (pay<<16))) )
292
293#define mimo_ofdmTx_setControlBits(c) ofdm_txrx_mimo_WriteReg_Tx_ControlBits(OFDM_BASEADDR, c)
294#define mimo_ofdmTx_getOptions() ofdm_txrx_mimo_ReadReg_Tx_ControlBits(OFDM_BASEADDR)
295
296#define mimo_ofdmTx_setDelays(extTxEn, extraAutoTx, txStartOut) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TX_DELAYS, ( \
297    ( (extTxEn&0xFF)    << TX_EXTAUTO_TXEN_DLY_LSB) | \
298    ( (extraAutoTx&0xF) << TX_AUTOTX_EXTRA_DLY_LSB) | \
299    ( (txStartOut&0xFF) << TX_START_D_OUTPUTS_DLY_LSB)))
300
301#define mimo_ofdmTxRx_setFFTScaling(c) ofdm_txrx_mimo_WriteReg_TxRx_FFT_Scaling(OFDM_BASEADDR, c)
302#define mimo_ofdmRx_setFFTWindowOffset(c) ofdm_txrx_mimo_WriteReg_Rx_PktDet_Delay(OFDM_BASEADDR, (ofdm_txrx_mimo_ReadReg_Rx_PktDet_Delay(OFDM_BASEADDR) & 0xFFFFE07F) | ((c&0x3F)<<7))
303
304#define mimo_ofdmRx_setPktDetDly(c) ofdm_txrx_mimo_WriteReg_Rx_PktDet_Delay(OFDM_BASEADDR, (ofdm_txrx_mimo_ReadReg_Rx_PktDet_Delay(OFDM_BASEADDR) & 0xFFFFFF80)| (c&0x7F))
305#define mimo_ofdmRx_setCFOCalcDly(c) ofdm_txrx_mimo_WriteReg_Rx_PktDet_Delay(OFDM_BASEADDR, (ofdm_txrx_mimo_ReadReg_Rx_PktDet_Delay(OFDM_BASEADDR) & ~0x001F0000) | ( (c&0x1F)<<16 ))
306#define mimo_ofdmRx_setCFOMaxDiff(c) ofdm_txrx_mimo_WriteReg_Rx_PktDet_Delay(OFDM_BASEADDR, (ofdm_txrx_mimo_ReadReg_Rx_PktDet_Delay(OFDM_BASEADDR) & ~0xFF000000) | ( (c&0xFF)<<24 ))
307
308#define mimo_ofdmTx_setPktDoneReset(c) ofdm_txrx_mimo_WriteReg_Tx_Start_Reset_Control(OFDM_BASEADDR, (c<<2)&0x4)
309#define mimo_ofdmRx_getPayloadStatus() (PHYRXSTATUS_PAYLOAD & ofdm_txrx_mimo_ReadReg_Rx_packet_done(OFDM_BASEADDR))
310#define mimo_ofdmRx_getHeaderStatus() ((PHYRXSTATUS_HEADER & ofdm_txrx_mimo_ReadReg_Rx_packet_done(OFDM_BASEADDR)))
311#define mimo_ofdmRx_getPktStatus()  (((PHYRXSTATUS_PAYLOAD | PHYRXSTATUS_HEADER) & ofdm_txrx_mimo_ReadReg_Rx_packet_done(OFDM_BASEADDR)))
312
313#define mimo_ofdmRx_setAFTxScaling(c) ofdm_rx_mimo_WriteReg_Rx_AFScaling(0, c)
314
315#define mimo_ofdmRx_setPilotCalcParams(minMag) ofdm_rx_mimo_WriteReg_Rx_PilotCalcParams(0, (minMag & 0xFFF))
316
317//Timer Defines
318#define TIMER_A 0
319#define TIMER_B 1
320#define TIMER_C 2
321#define TIMER_D 3
322
323#define TIMER_A_DONE 0x1
324#define TIMER_B_DONE 0x100
325#define TIMER_C_DONE 0x10000
326#define TIMER_D_DONE 0x1000000
327
328#define TIMER_A_ACTIVE 0x2
329#define TIMER_B_ACTIVE 0x200
330#define TIMER_C_ACTIVE 0x20000
331#define TIMER_D_ACTIVE 0x2000000
332
333#define TIMER_A_PAUSED 0x4
334#define TIMER_B_PAUSED 0x400
335#define TIMER_C_PAUSED 0x40000
336#define TIMER_D_PAUSED 0x4000000
337
338//Byte indicies of various header fields (used for the autoRepsonse setup)
339#define PKTHEADER_INDX_SRCADDR  4
340#define PKTHEADER_INDX_DSTADDR  6
341#define PKTHEADER_INDX_RLYADDR  8
342#define PKTHEADER_INDX_TYPE     10
343#define PKTHEADER_INDX_RETX     11
344#define PKTHEADER_INDX_SEQ      12
345#define PKTHEADER_INDX_PREVCHECK 20
346#define PKTHEADER_INDX_CHECK    22
347
348///Structure contains PHY header
349typedef struct {
350    ///Full-rate modulation order
351    unsigned char fullRate;     //0
352    ///Rate for convolutional error correction code
353    unsigned char codeRate;         //1
354    ///The length of the packet (in bytes). NOTE: This should only specify the length of the payload to-be-sent.
355    unsigned short int length;      //2
356    ///Source MAC address.
357    unsigned short int srcAddr;     //4
358    ///Destination MAC address.
359    unsigned short int destAddr;    //6
360    ///Relay MAC address.
361    unsigned short int relAddr;     //8
362    ///Type of packet this particular Macframe corresponds to (e.g. DATA, ACKPACKET, etc.)
363    unsigned char pktType;          //10
364    ///Reserved byte
365    unsigned char remainingTx;      //11
366    ///Sequence number of this packet
367    unsigned int seqNum;            //12-15
368    ///Reserved byte
369    unsigned short int timeLeft;
370    unsigned char cogParam;
371    unsigned char reserved0;
372    unsigned char reserved1; //20
373    unsigned char reserved2; //21
374
375    ///Checksum of the packet will be automatically inserted by PHY
376    unsigned short int checksum;    //22
377} phyHeader;
378
379//Prototypes for functions in warpphy.c
380int warpphy_init();
381void warpphy_clearRxInterrupts();
382void warpphy_clearTxInterrupts();
383int warpphy_pktTx(unsigned int block);
384void mimo_ofdmRx_enable();
385void mimo_ofdmRx_disable();
386void mimo_ofdmRx_setOptions(unsigned int someOptions, unsigned int intType);
387unsigned int mimo_ofdmRx_getOptions();
388void mimo_ofdmTx_disable();
389void mimo_ofdmTx_enable();
390void warpphy_setBuffs(unsigned char txBufOffset, unsigned char rxBufOffset);
391void warpphy_setNumTrainingSyms(unsigned int numTraining);
392void warpphy_setPktDlyPlus();
393void warpphy_setPktDlyMinus();
394void warpphy_set_PN_KPlus(unsigned int increment);
395void warpphy_set_PN_KMinus(unsigned int decrement);
396void warpphy_set_CFODebugOutput(unsigned char outputSel);
397void print_CFO_constants();
398void warpphy_set_B_KPPlus(unsigned int increment);
399void warpphy_set_B_KPMinus(unsigned int decrement);
400void warpphy_set_B_KIPlus(unsigned int increment);
401void warpphy_set_B_KIMinus(unsigned int decrement);
402void warpphy_set_FFTOffset_Plus();
403void warpphy_set_FFTOffset_Minus();
404void warpphy_setNoiseTargetPlus();
405void warpphy_setNoiseTargetMinus();
406void warpphy_setTargetPlus();
407void warpphy_setTargetMinus();
408void warpphy_set_modulation(unsigned char baseRate, unsigned char TxAntAFullRate, unsigned char TxAntBFullRate, unsigned char RxAntAFullRate, unsigned char RxAntBFullRate);
409int warpphy_setChannel(unsigned char band, unsigned int chan);
410int warpphy_applyTxDCOCorrection(unsigned int radioSelection);
411void warpphy_clearRxHeaderInterrupt();
412void warpphy_setPktDetPlus(unsigned int offset);
413void warpphy_setPktDetMinus(unsigned int offset);
414void warpphy_setCSMAPlus(unsigned int offset);
415void warpphy_setCSMAMinus(unsigned int offset);
416int warpphy_isFree();
417char warpphy_pollRxStatus(unsigned char type);
418void ofdm_AGC_SetTarget(unsigned int target);
419inline void ofdm_AGC_SetDCO(unsigned int AGCstate);
420void ofdm_AGC_Reset();
421void ofdm_AGC_MasterReset();
422void ofdm_AGC_Initialize(int noise_estimate);
423void ofdm_AGC_setNoiseEstimate(int noise_estimate);
424unsigned int ofdm_AGC_GetGains(void);
425void ofdm_timer_start();
426void ofdm_timer_stop();
427void ofdm_timer_clearInterrupt();
428int warpphy_setTxPower(unsigned char txPwr);
429int warpphy_setAntennaMode(unsigned int txMode, unsigned int rxMode);
430void warpphy_incrementTxScaling(int incr_preamble, int incr_payload);
431void warpphy_setLongCorrThresh(unsigned short thresh);
432void warpphy_setEnergyDetThresh(unsigned short thresh);
433void warpphy_clearAutoResponseFlag(unsigned char flagID);
434void warpphy_setAntBPreambleShift(unsigned char shift);
435void warpphy_AFrecordEnable(unsigned char recordEn);
436void warpphy_setNumBaseRateSyms(unsigned int numSyms);
437void warpphy_setAutoCorrDetParams(unsigned short corrThresh, unsigned short energyThresh);
438void warpphy_setCarrierSenseThresh(unsigned short thresh);
439void warpphy_clearRxPktStatus();
440int warpphy_waitForTx();
441int warpphy_applyTxDCOCalibration();
442
443//warp_timer function prototypes
444void warp_timer_start(unsigned char timer);
445void warp_timer_pause(unsigned char timer);
446void warp_timer_resume(unsigned char timer);
447void warp_timer_setMode(unsigned char timer, unsigned char mode);
448void warp_timer_resetDone(unsigned char timer);
449void warp_timer_resetAllDoneStatus();
450void warp_timer_setTimer(unsigned char timer, unsigned int slotTime, unsigned int slotCount);
451void warp_timer_init();
452unsigned char warp_timer_getStatus(unsigned char timer);
453unsigned char warp_timer_isDone(unsigned char timer);
454unsigned char warp_timer_isActive(unsigned char timer);
455unsigned char warp_timer_isPaused(unsigned char timer);
456unsigned int warp_timer_getStatuses();
457unsigned char warp_timer_getDoneStatus();
458void warpphy_saveAFpkt(unsigned char doSave);
459int warpphy_setTxAntennaSwap(unsigned int txMode);
460unsigned int warpphy_returnGainsDB();
461
462//Register access macros
463#define mimo_ofdmTxRx_getAction0() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION0))
464#define mimo_ofdmTxRx_getAction1() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION1))
465#define mimo_ofdmTxRx_getAction2() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION2))
466#define mimo_ofdmTxRx_getAction3() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION3))
467#define mimo_ofdmTxRx_getAction4() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION4))
468#define mimo_ofdmTxRx_getAction5() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION5))
469#define mimo_ofdmTxRx_getAction6() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION6))
470#define mimo_ofdmTxRx_getAction7() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION7))
471
472#define mimo_ofdmTxRx_setAction0(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION0, d))
473#define mimo_ofdmTxRx_setAction1(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION1, d))
474#define mimo_ofdmTxRx_setAction2(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION2, d))
475#define mimo_ofdmTxRx_setAction3(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION3, d))
476#define mimo_ofdmTxRx_setAction4(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION4, d))
477#define mimo_ofdmTxRx_setAction5(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION5, d))
478#define mimo_ofdmTxRx_setAction6(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION6, d))
479#define mimo_ofdmTxRx_setAction7(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION7, d))
480
481#define mimo_ofdmTxRx_getMatch0() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH0))
482#define mimo_ofdmTxRx_getMatch1() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH1))
483#define mimo_ofdmTxRx_getMatch2() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH2))
484#define mimo_ofdmTxRx_getMatch3() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH3))
485#define mimo_ofdmTxRx_getMatch4() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH4))
486#define mimo_ofdmTxRx_getMatch5() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH5))
487#define mimo_ofdmTxRx_getMatch6() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH6))
488#define mimo_ofdmTxRx_getMatch7() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH7))
489
490#define mimo_ofdmTxRx_setMatch0(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH0, d))
491#define mimo_ofdmTxRx_setMatch1(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH1, d))
492#define mimo_ofdmTxRx_setMatch2(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH2, d))
493#define mimo_ofdmTxRx_setMatch3(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH3, d))
494#define mimo_ofdmTxRx_setMatch4(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH4, d))
495#define mimo_ofdmTxRx_setMatch5(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH5, d))
496#define mimo_ofdmTxRx_setMatch6(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH6, d))
497#define mimo_ofdmTxRx_setMatch7(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH7, d))
498
499//Match definition fields for match units 0-5 (comparison of incoming header with static value)
500#define PHY_AUTORESPONSE_MATCH_BYTEADDR_MASK    0x0000001F
501#define PHY_AUTORESPONSE_MATCH_BYTEADDR_OFFSET  0
502
503#define PHY_AUTORESPONSE_MATCH_LENGTH_MASK      0x00000060
504#define PHY_AUTORESPONSE_MATCH_LENGTH_OFFSET    5
505
506#define PHY_AUTORESPONSE_MATCH_VALUE_MASK       0xFFFFFF00
507#define PHY_AUTORESPONSE_MATCH_VALUE_OFFSET     8
508
509#define PHY_AUTORESPONSE_MATCH_VALUE_MAP(c)     ((c<<PHY_AUTORESPONSE_MATCH_VALUE_OFFSET) & PHY_AUTORESPONSE_MATCH_VALUE_MASK)
510#define PHY_AUTORESPONSE_MATCH_LENGTH_MAP(c)    ((c<<PHY_AUTORESPONSE_MATCH_LENGTH_OFFSET) & PHY_AUTORESPONSE_MATCH_LENGTH_MASK)
511#define PHY_AUTORESPONSE_MATCH_BYTEADDR_MAP(c)  ((c<<PHY_AUTORESPONSE_MATCH_BYTEADDR_OFFSET) & PHY_AUTORESPONSE_MATCH_BYTEADDR_MASK)
512
513#define PHY_AUTORESPONSE_MATCH_CONFIG(addr, len, val) (PHY_AUTORESPONSE_MATCH_BYTEADDR_MAP(addr) | PHY_AUTORESPONSE_MATCH_LENGTH_MAP(len) | PHY_AUTORESPONSE_MATCH_VALUE_MAP(val))
514
515//Match definition fields for match units 6-7 (comparison of incoming header with previously received header corresponding to saved waveform)
516#define PHY_AUTORESPONSE_MATCH_RXADDR0_OFFSET       0
517#define PHY_AUTORESPONSE_MATCH_RXADDR0_MASK         (0x0000001F<< PHY_AUTORESPONSE_MATCH_RXADDR0_OFFSET)
518#define PHY_AUTORESPONSE_MATCH_PREVADDR0_OFFSET     5
519#define PHY_AUTORESPONSE_MATCH_PREVADDR0_MASK       (0x0000001F<< PHY_AUTORESPONSE_MATCH_PREVADDR0_OFFSET)
520
521#define PHY_AUTORESPONSE_MATCH_RXADDR1_OFFSET       10
522#define PHY_AUTORESPONSE_MATCH_RXADDR1_MASK         (0x0000001F<< PHY_AUTORESPONSE_MATCH_RXADDR1_OFFSET)
523#define PHY_AUTORESPONSE_MATCH_PREVADDR1_OFFSET     15
524#define PHY_AUTORESPONSE_MATCH_PREVADDR1_MASK       (0x0000001F<< PHY_AUTORESPONSE_MATCH_PREVADDR1_OFFSET)
525#define PHY_AUTORESPONSE_MATCH_ADDR1_EN             0x40000000
526
527#define PHY_AUTORESPONSE_MATCH_RXADDR2_OFFSET       20
528#define PHY_AUTORESPONSE_MATCH_RXADDR2_MASK         (0x0000001F<< PHY_AUTORESPONSE_MATCH_RXADDR2_OFFSET)
529#define PHY_AUTORESPONSE_MATCH_PREVADDR2_OFFSET     25
530#define PHY_AUTORESPONSE_MATCH_PREVADDR2_MASK       (0x0000001F<< PHY_AUTORESPONSE_MATCH_PREVADDR2_OFFSET)
531#define PHY_AUTORESPONSE_MATCH_ADDR2_EN             0x80000000
532
533//Macro to help define header comparison match configuration registers
534#define PHY_AUTORESPONSE_MATCH_HDRCOMP_CONFIG(rxAddr0, prevAddr0, rxAddr1, prevAddr1, useAddr1, rxAddr2, prevAddr2, useAddr2) (\
535( (rxAddr0 << PHY_AUTORESPONSE_MATCH_RXADDR0_OFFSET) & PHY_AUTORESPONSE_MATCH_RXADDR0_MASK) | \
536( (rxAddr1 << PHY_AUTORESPONSE_MATCH_RXADDR1_OFFSET) & PHY_AUTORESPONSE_MATCH_RXADDR1_MASK) | \
537( (rxAddr2 << PHY_AUTORESPONSE_MATCH_RXADDR2_OFFSET) & PHY_AUTORESPONSE_MATCH_RXADDR2_MASK) | \
538( (prevAddr0 << PHY_AUTORESPONSE_MATCH_PREVADDR0_OFFSET) & PHY_AUTORESPONSE_MATCH_PREVADDR0_MASK) | \
539( (prevAddr1 << PHY_AUTORESPONSE_MATCH_PREVADDR1_OFFSET) & PHY_AUTORESPONSE_MATCH_PREVADDR1_MASK) | \
540( (prevAddr2 << PHY_AUTORESPONSE_MATCH_PREVADDR2_OFFSET) & PHY_AUTORESPONSE_MATCH_PREVADDR2_MASK) | \
541( useAddr1 ? PHY_AUTORESPONSE_MATCH_ADDR1_EN : 0) | \
542( useAddr2 ? PHY_AUTORESPONSE_MATCH_ADDR2_EN : 0) )
543
544
545//Action fields
546#define PHY_AUTORESPONSE_ACT_ID_MASK    0x00FC0000
547#define PHY_AUTORESPONSE_ACT_ID_OFFSET  18
548
549#define PHY_AUTORESPONSE_ACT_PARAM_MASK     0xFF000000
550#define PHY_AUTORESPONSE_ACT_PARAM_OFFSET   24
551#define PHY_AUTORESPONSE_MAP_ACT_PARAM(c)   ((c<<PHY_AUTORESPONSE_ACT_PARAM_OFFSET) & PHY_AUTORESPONSE_ACT_PARAM_MASK)
552
553#define PHY_AUTORESPONSE_ACT_TRANS_HDR  0x00010000
554#define PHY_AUTORESPONSE_ACT_USE_PRECFO 0x00020000
555#define PHY_AUTORESPONSE_ACT_RETX_CRC   0x00000200
556#define PHY_AUTORESPONSE_ACT_SWAP_ANT   0x00000400
557
558#define PHY_AUTORESPONSE_REQ_GOODHDR    0x000800
559#define PHY_AUTORESPONSE_REQ_BADPKT     0x001000
560#define PHY_AUTORESPONSE_REQ_GOODPKT    0x002000
561
562#define PHY_AUTORESPONSE_REQ_FLAGA      0x004000
563#define PHY_AUTORESPONSE_REQ_FLAGB      0x008000
564
565#define PHY_AUTORESPONSE_REQ_MATCH0     0x001
566#define PHY_AUTORESPONSE_REQ_MATCH1     0x002
567#define PHY_AUTORESPONSE_REQ_MATCH2     0x004
568#define PHY_AUTORESPONSE_REQ_MATCH3     0x008
569#define PHY_AUTORESPONSE_REQ_MATCH4     0x010
570#define PHY_AUTORESPONSE_REQ_MATCH5     0x020
571#define PHY_AUTORESPONSE_REQ_MATCH6     0x040
572#define PHY_AUTORESPONSE_REQ_MATCH7     0x080
573
574#define PHY_AUTORESPONSE_REQ_MATCHALL   (PHY_AUTORESPONSE_REQ_MATCH0 | PHY_AUTORESPONSE_REQ_MATCH1 | PHY_AUTORESPONSE_REQ_MATCH2 | PHY_AUTORESPONSE_REQ_MATCH3 | PHY_AUTORESPONSE_REQ_MATCH4 | PHY_AUTORESPONSE_REQ_MATCH5 | PHY_AUTORESPONSE_REQ_MATCH6 | PHY_AUTORESPONSE_REQ_MATCH7)
575#define PHY_AUTORESPONSE_REQ_ALLCONDS   (PHY_AUTORESPONSE_REQ_MATCHALL | PHY_AUTORESPONSE_REQ_FLAGA | PHY_AUTORESPONSE_REQ_FLAGB | PHY_AUTORESPONSE_REQ_GOODHDR | PHY_AUTORESPONSE_REQ_BADPKT | PHY_AUTORESPONSE_REQ_GOODPKT)
576
577//ActionIDs
578#define PHY_AUTORESPONSE_ACTID_DISABLED     ((00<<PHY_AUTORESPONSE_ACT_ID_OFFSET) & PHY_AUTORESPONSE_ACT_ID_MASK)
579#define PHY_AUTORESPONSE_ACTID_SETFLAGA     ((62<<PHY_AUTORESPONSE_ACT_ID_OFFSET) & PHY_AUTORESPONSE_ACT_ID_MASK)
580#define PHY_AUTORESPONSE_ACTID_SETFLAGB     ((61<<PHY_AUTORESPONSE_ACT_ID_OFFSET) & PHY_AUTORESPONSE_ACT_ID_MASK)
581#define PHY_AUTORESPONSE_ACTID_TXPKTBUF(c)  ((   c<<PHY_AUTORESPONSE_ACT_ID_OFFSET) & PHY_AUTORESPONSE_ACT_ID_MASK)
582
583#define PHY_HEADERTRANSLATE_SET(actionBuf, txByteNum, srcBuf, srcByteNum) \
584    XIo_Out32(\
585    (XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXHEADERTRANSLATE + ((actionBuf)*32*sizeof(int)) + ((txByteNum)*sizeof(int))),\
586    (((srcBuf) & 0x1F)<<5) | ((srcByteNum) & 0x1F))
587
588//Macro to help construct autoResponse Tx actions
589#define PHY_AUTORESPONSE_TXACTION_CONFIG(pktBuf, actionOptions, delay, conditions) (\
590    (PHY_AUTORESPONSE_ACTID_TXPKTBUF(pktBuf) ) | \
591    (actionOptions & (PHY_AUTORESPONSE_ACT_SWAP_ANT | PHY_AUTORESPONSE_ACT_TRANS_HDR | PHY_AUTORESPONSE_ACT_USE_PRECFO)) | \
592    (PHY_AUTORESPONSE_MAP_ACT_PARAM(delay) ) | \
593    (conditions & (PHY_AUTORESPONSE_REQ_ALLCONDS)))
594
595//Macro to help construct autoResponse action for setting Flag A
596#define PHY_AUTORESPONSE_ACTION_SETFLAGA_CONFIG(conditions) (PHY_AUTORESPONSE_ACTID_SETFLAGA | (conditions & (PHY_AUTORESPONSE_REQ_ALLCONDS)))
597
598//Macro to help construct autoResponse action for setting Flag B
599#define PHY_AUTORESPONSE_ACTION_SETFLAGB_CONFIG(conditions) (PHY_AUTORESPONSE_ACTID_SETFLAGB | (conditions & (PHY_AUTORESPONSE_REQ_ALLCONDS)))
600
601//Flag IDs for user functions
602#define AUTORESP_FLAGID_A 1
603#define AUTORESP_FLAGID_B 2
604
605#endif
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