source: ReferenceDesigns/w3_802.11/c/high_periphs/eth/wlan_axi_ethernet_intr/wlan_axi_ethernet_intr.c

/*****************************************************************
* File: wlan_axi_ethernet_intr.c
* Copyright (c) 2019 Mango Communications, all rights reserved
*****************************************************************/

#include "wlan_axi_ethernet_intr.h"
#include "wlan_mac_common.h"
#include "wlan_mac_dl_list.h"
#include "wlan_mac_eth_util.h"
#include "wlan_mac_queue.h"
#include "wlan_mac_high.h"
#include "wlan_platform_high.h"
#include "wlan_platform_intc.h"
#include "wlan_common_types.h"

#include "xaxiethernet.h"
#include "xaxidma.h"
#include "xaxidma_hw.h"

// Local function declarations
static int _init_rx_bd(XAxiDma_Bd* bd_ptr, dl_entry* qe_ptr, u32 max_transfer_len, u32 LengthMask);
static u32 _wlan_axi_eth_intr_calc_num_bd(u32 mem_size);
static void _eth_rx_interrupt_handler(void *callback_arg);
static void _eth_tx_interrupt_handler(void *callback_arg);
inline void _wlan_axi_eth_intr_free_tx_bd(peripheral_args_t* peripheral_args);

/**
 * @brief Initialize AXI ETHERNET INTR with Interrupts
 *
 * This function initializes the AXI ETHERNET INTR peripheral.
 *
 * @param peripheral_args_t* peripheral_args
 *          - necessary arguments to distinguish between multiple instances of this peripheral
 *        u32 eth_device_id
 *          - The Device ID of the AXI ETHERNET known to platform code (typically from xparameters.h)
 *        u32 wlan_eth_link_speed
 *          - Link speed (Mbps)
 *        u32 wlan_eth_mdio_phyaddr
 *          - Offset of MDIO_PHYADDR register
 *        u32 eth_bd_mem_base
 *          - The base address where this peripheral can store Ethernet buffer descriptors
 *        u32 eth_bd_mem_size
 *          - The total space (in bytes) available at the provided base address
 *        u32 num_tx_bd
 *          - Number of Tx BDs that will be used. The remaining portion of eth_bd_mem_size
 *            will be used for Rx BDs
 *        u32 tx_coalescing_count
 *          - Number of Tx events that will be coalesced into a single interrupt
 *        u32 tx_coalescing_timer
 *          - If tx_coalescing_count is not achieved but there are complete Tx events, an interrupt
 *            will occur after this amount of time after the last reception. The units of this
 *            parameter are platform specific. Namely, the resolution is C_DLYTMR_RESOLUTION cycles
 *            of the m_axi_sg_aclk clock
 * @return intr_conn_params_t
 *          - A struct containing a pointer to a ISR handler and an ISR argument that platform code
 *            should use when connecting the peripheral to the interrupt controller
 */
intr_conn_params_t wlan_axi_eth_intr_init( peripheral_args_t* peripheral_args,
                                           u32 eth_device_id,
                                           u32 wlan_eth_link_speed,
                                           u32 wlan_eth_mdio_phyaddr,
                                           u32 eth_bd_mem_base,
                                           u32 eth_bd_mem_size,
                                           u32 num_tx_bd,
                                           u32 tx_coalescing_count,
                                           u32 tx_coalescing_timer ){
    intr_conn_params_t intr_conn_params;
    XAxiDma* eth_dma_instance_ptr;
    XAxiEthernet_Config* eth_cfg_ptr;
    XAxiEthernet eth_instance;
    XAxiDma_Config* eth_dma_cfg_ptr;
    XAxiDma_Bd eth_dma_bd_template;
    XAxiDma_BdRing* eth_tx_ring_ptr;
    XAxiDma_BdRing* eth_rx_ring_ptr;
    XAxiDma_Bd* bd_ptr;
    XAxiDma_Bd* first_bd_ptr;
    dl_list rx_queue_list;
    dl_entry* curr_queue_element;
    dl_entry* next_queue_element;
    u32 bd_count;
    u32 i;
    u32 eth_tx_bd_mem_base;
    u32 eth_tx_bd_mem_size;
    u32 eth_tx_bd_mem_high;
    u32 eth_rx_bd_mem_base;
    u32 eth_rx_bd_mem_size;
    u32 num_rx_bd;
    int status;

    intr_conn_params.intr_handler0 = NULL;
    intr_conn_params.intr_handler_arg0 = NULL;
    intr_conn_params.intr_handler1 = NULL;
    intr_conn_params.intr_handler_arg1 = NULL;

    eth_dma_instance_ptr = (XAxiDma*)peripheral_args->driver_instance;

    // Split up the memory set aside for us in eth_bd_mem_base
    eth_tx_bd_mem_base = eth_bd_mem_base;
    eth_tx_bd_mem_size = num_tx_bd*XAXIDMA_BD_MINIMUM_ALIGNMENT;
    eth_tx_bd_mem_high = CALC_MEM_HIGH_ADDR(eth_tx_bd_mem_base, eth_tx_bd_mem_size);
    eth_rx_bd_mem_base = eth_tx_bd_mem_high+1;
    eth_rx_bd_mem_size = eth_bd_mem_size - eth_tx_bd_mem_size;

    if(num_tx_bd == 0){
        xil_printf("WLAN_AXI_ETHERNET_INTR: Tx BD allocation failed, insufficient memory\n");
        wlan_platform_high_userio_disp_status(USERIO_DISP_STATUS_CPU_ERROR, WLAN_ERROR_CODE_INSUFFICIENT_BD_SIZE);
        return intr_conn_params;
    }

    num_rx_bd = _wlan_axi_eth_intr_calc_num_bd(eth_rx_bd_mem_size);
    if(num_rx_bd == 0){
        xil_printf("WLAN_AXI_ETHERNET_INTR: Rx BD allocation failed, insufficient memory\n");
        wlan_platform_high_userio_disp_status(USERIO_DISP_STATUS_CPU_ERROR, WLAN_ERROR_CODE_INSUFFICIENT_BD_SIZE);
        return intr_conn_params;
    }

    // Initialize buffer descriptor counts
    //xil_printf("WLAN_AXI_ETHERNET_INTR: %3d Eth Tx BDs placed in 0x%08x: using %d B\n", num_tx_bd, eth_tx_bd_mem_base, num_tx_bd*XAXIDMA_BD_MINIMUM_ALIGNMENT);
    //xil_printf("WLAN_AXI_ETHERNET_INTR: %3d Eth Rx BDs placed in 0x%08x: using %d kB\n", num_rx_bd, eth_rx_bd_mem_base, num_rx_bd*XAXIDMA_BD_MINIMUM_ALIGNMENT/1024);

    // Initialize Ethernet instance
    eth_cfg_ptr = XAxiEthernet_LookupConfig(eth_device_id);
    status = XAxiEthernet_CfgInitialize(&eth_instance, eth_cfg_ptr, eth_cfg_ptr->BaseAddress);
    if (status != XST_SUCCESS) {
        xil_printf("Error in XAxiEthernet_CfgInitialize! Err = %d\n", status);
        return intr_conn_params;
    };

    // Setup the Ethernet options
    //     NOTE:  This Ethernet driver does support jumbo Ethernet frames.  Only 2KB is allocated for each Rx buffer
    status  = XAxiEthernet_ClearOptions(&eth_instance, XAE_LENTYPE_ERR_OPTION | XAE_FLOW_CONTROL_OPTION );
    status |= XAxiEthernet_SetOptions(&eth_instance, XAE_JUMBO_OPTION | XAE_FCS_STRIP_OPTION | XAE_PROMISC_OPTION | XAE_MULTICAST_OPTION | XAE_BROADCAST_OPTION | XAE_FCS_INSERT_OPTION);
    status |= XAxiEthernet_SetOptions(&eth_instance, XAE_RECEIVER_ENABLE_OPTION | XAE_TRANSMITTER_ENABLE_OPTION);

    if (status != XST_SUCCESS){
        xil_printf("WLAN_AXI_ETHERNET_INTR: Error in XAxiEthernet_Set/ClearOptions! Err = %d\n", status);
        return intr_conn_params;
    };

    // Set the operating speed
    XAxiEthernet_SetOperatingSpeed(&eth_instance, wlan_eth_link_speed);

    // If the link speed is 1 Gbps, then only advertise and link to 1 Gbps connection
    //     See Ethernet PHY specification for documentation on the values used
    if (wlan_eth_link_speed == 1000) {
        XAxiEthernet_PhyWrite(&eth_instance, wlan_eth_mdio_phyaddr, 0, 0x0140);
        XAxiEthernet_PhyWrite(&eth_instance, wlan_eth_mdio_phyaddr, 0, 0x8140);
    }

    // Initialize the DMA

    // Initialize the DMA peripheral structures
    eth_dma_cfg_ptr = XAxiDma_LookupConfig(eth_device_id);
    status = XAxiDma_CfgInitialize(eth_dma_instance_ptr, eth_dma_cfg_ptr);
    if (status != XST_SUCCESS) {
        xil_printf("WLAN_AXI_ETHERNET_INTR: Error in XAxiDma_CfgInitialize! Err = %d\n", status);
        return intr_conn_params;
    }

    // Zero-out the template buffer descriptor
    XAxiDma_BdClear(&eth_dma_bd_template);

    // Fetch handles to the Tx and Rx BD rings
    eth_tx_ring_ptr = XAxiDma_GetTxRing(eth_dma_instance_ptr);
    eth_rx_ring_ptr = XAxiDma_GetRxRing(eth_dma_instance_ptr);

    // Disable all Tx/Rx DMA interrupts
    XAxiDma_BdRingIntDisable(eth_tx_ring_ptr, XAXIDMA_IRQ_ALL_MASK);
    XAxiDma_BdRingIntDisable(eth_rx_ring_ptr, XAXIDMA_IRQ_ALL_MASK);

    // Disable Rx delay and coalescing
    //  - We have tried having these on but have not observed any appreciable
    //    performance improvement
    //  - Intuitively, both sinks for Ethernet traffic (802.11 portal and wlan_exp
    //    processing are slower than the Ethernet line rate so there isn't much to
    //    gain
    XAxiDma_BdRingSetCoalesce(eth_rx_ring_ptr, 1, 0);

    // Enable Tx delay and coalescing.
    XAxiDma_BdRingSetCoalesce(eth_tx_ring_ptr, tx_coalescing_count, tx_coalescing_timer);

    // Setup Tx/Rx buffer descriptor rings in memory
    status  = XAxiDma_BdRingCreate(eth_tx_ring_ptr, eth_tx_bd_mem_base, eth_tx_bd_mem_base, XAXIDMA_BD_MINIMUM_ALIGNMENT, num_tx_bd);
    status |= XAxiDma_BdRingCreate(eth_rx_ring_ptr, eth_rx_bd_mem_base, eth_rx_bd_mem_base, XAXIDMA_BD_MINIMUM_ALIGNMENT, num_rx_bd);

    if (status != XST_SUCCESS) {
        xil_printf("WLAN_AXI_ETHERNET_INTR: Error creating DMA BD Rings! Err = %d\n", status);
        return intr_conn_params;
    }

    // Populate each ring with empty buffer descriptors
    status  = XAxiDma_BdRingClone(eth_tx_ring_ptr, &eth_dma_bd_template);
    status |= XAxiDma_BdRingClone(eth_rx_ring_ptr, &eth_dma_bd_template);
    if (status != XST_SUCCESS) {
        xil_printf("WLAN_AXI_ETHERNET_INTR: Error in XAxiDma_BdRingClone()! Err = %d\n", status);
        return intr_conn_params;
    }

    // Initialize the Rx buffer descriptors
    bd_count = XAxiDma_BdRingGetFreeCnt(eth_rx_ring_ptr);
    if (bd_count != num_rx_bd) {
        xil_printf("WLAN_AXI_ETHERNET_INTR: Error in Eth Rx DMA init - not all Rx BDs were free at boot\n");
    }

    status = XAxiDma_BdRingAlloc(eth_rx_ring_ptr, bd_count, &bd_ptr);
    if (status != XST_SUCCESS) {
        xil_printf("WLAN_AXI_ETHERNET_INTR: Error in XAxiDma_BdRingAlloc()! Err = %d\n", status);
        return intr_conn_params;
    }

    first_bd_ptr = bd_ptr; // We need to hold on to the first one when submitting the ring
                           //  to the hardware.

    // Checkout bd_count of free queue entries to attach to these buffer descriptors
    dl_list_init(&rx_queue_list);
    queue_checkout_list(&rx_queue_list, num_rx_bd);

    if(rx_queue_list.length != num_rx_bd){
        xil_printf("WLAN_AXI_ETHERNET_INTR: Error checking out queue entries during Eth peripheral init\n");
        queue_checkin_list(&rx_queue_list);
        return intr_conn_params;
    }


    next_queue_element = rx_queue_list.first;

    // Loop bd_count buffer descriptors and attach them to queue entries
    //  provided in rx_queue_list
    for (i = 0; i < num_rx_bd; i++) {
        // Take a queue element from the list provided as an argument
        curr_queue_element = next_queue_element;
        next_queue_element = dl_entry_next(next_queue_element);

        if (curr_queue_element == NULL) {
              xil_printf("WLAN_AXI_ETHERNET_INTR: Insufficient elements in rx_queue_list\n");
              queue_checkin_list(&rx_queue_list);
              return intr_conn_params;
         }

        // Remove the queue element from the list. Rx handling will be responsible for returning
        //  it to a list at some point
        dl_entry_remove(&rx_queue_list, curr_queue_element);


        // Initialize the Rx buffer descriptor
        status = _init_rx_bd(bd_ptr, curr_queue_element, WLAN_AXI_ETH_RX_INTR_BUF_SIZE, eth_rx_ring_ptr->MaxTransferLen);

        if (status != XST_SUCCESS) {
            xil_printf("Error initializing Rx BD %d\n", i);
            queue_checkin_list(&rx_queue_list);
            return intr_conn_params;
        }

        // Update bd_ptr to the next BD in the chain for the next iteration
        bd_ptr = XAxiDma_BdRingNext(eth_rx_ring_ptr, bd_ptr);
    }

    // Push the Rx BD ring to hardware and start receiving
    status = XAxiDma_BdRingToHw(eth_rx_ring_ptr, bd_count, first_bd_ptr);

    if (status != XST_SUCCESS) {
        xil_printf("WLAN_AXI_ETHERNET_INTR: Error submitting Rx BD ring to HW\n");
        queue_checkin_list(&rx_queue_list);
        return intr_conn_params;
    }

    // Enable Interrupts
    XAxiDma_BdRingIntEnable(eth_rx_ring_ptr, XAXIDMA_IRQ_ALL_MASK);
    XAxiDma_BdRingIntEnable(eth_tx_ring_ptr, XAXIDMA_IRQ_ALL_MASK);

    status |= XAxiDma_BdRingStart(eth_rx_ring_ptr);
    if (status != XST_SUCCESS){
        xil_printf("WLAN_AXI_ETHERNET_INTR: Error in XAxiDma BdRingToHw/BdRingStart! Err = %d\n", status);
        return intr_conn_params;
    }

    // Start the DMA Tx channel
    //     NOTE:  No Eth packets are transmitted until actual Tx BD's are pushed to the DMA hardware
    status = XAxiDma_BdRingStart(eth_tx_ring_ptr);


    // Start the Ethernet controller
    XAxiEthernet_Start(&eth_instance);

    // Fill in return values
    intr_conn_params.intr_handler0 = (function_ptr_t)_eth_rx_interrupt_handler;
    intr_conn_params.intr_handler_arg0 = (void*)peripheral_args;
    intr_conn_params.intr_handler1 = (function_ptr_t)_eth_tx_interrupt_handler;
    intr_conn_params.intr_handler_arg1 = (void*)peripheral_args;

    return intr_conn_params;
}

/**
 * @brief Send Ethernet Frame
 *
 * This function sends an Ethernet frame. It does not perform error checking on the validity
 * of the provided address. It is the responsibility of platform code to error check the arguments
 * provided to this function.
 *
 * @param peripheral_args_t* peripheral_args
 *          - necessary arguments to distinguish between multiple instances of this peripheral
 * @param eth_tx_queue_buffer_t* eth_tx_queue_buffer
 *          - Ethernet packet to send
 * @return u32 status
 *          - see header file
 */
inline u32 wlan_axi_eth_intr_send(peripheral_args_t* peripheral_args, eth_tx_queue_buffer_t* eth_tx_queue_buffer) {

    int status;
    XAxiDma_BdRing* tx_ring_ptr;
    XAxiDma_Bd* cur_bd_ptr;
    XAxiDma_Bd* first_bd_ptr;
    u8* bd_addr[2];
    u16 bd_len[2];
    u8 num_required_bd, idx_bd;
    u32 length;
    u32 ctrl;
    XAxiDma* eth_dma_instance_ptr;

    interrupt_state_t prev_interrupt_state;

    bd_addr[0] = NULL;
    bd_addr[1] = NULL;
    bd_len[0] = 0;
    bd_len[1] = 0;
    num_required_bd = 0;
    ctrl = 0;

    eth_dma_instance_ptr = (XAxiDma*)(peripheral_args->driver_instance);

    length = eth_tx_queue_buffer->seg0_len + eth_tx_queue_buffer->seg1_len;

    if( (length < 42) || (length > 9014) ){
        xil_printf("ERROR (wlan_axi_eth_intr_send): Length %d out of range\n", length);
        return WLAN_AXI_ETH_INTR_SEND_ERR_INVALID_ARGS;
    }


    prev_interrupt_state = wlan_platform_intc_stop();

    // Get pointer to the axi_dma Tx buffer descriptor ring
    tx_ring_ptr = XAxiDma_GetTxRing(eth_dma_instance_ptr);

    if(eth_tx_queue_buffer->seg0_len > 0){
        bd_addr[num_required_bd] = eth_tx_queue_buffer->seg0;
        bd_len[num_required_bd] = eth_tx_queue_buffer->seg0_len;
        num_required_bd++;
    }
    if(eth_tx_queue_buffer->seg1_len > 0){
        bd_addr[num_required_bd] = eth_tx_queue_buffer->seg1_addr;
        bd_len[num_required_bd] = eth_tx_queue_buffer->seg1_len;
        num_required_bd++;
    }

    // Allocate and setup one Tx BD
    status  = XAxiDma_BdRingAlloc(tx_ring_ptr, num_required_bd, &cur_bd_ptr);

    if(status != XST_SUCCESS) {
        // There are no free BDs. Rather than block here, we'll return and allow
        //  the calling context to try transmitting later
        wlan_platform_intc_set_state(prev_interrupt_state);
        return WLAN_AXI_ETH_INTR_SEND_ERR_NO_FREE_BD;
    }

    first_bd_ptr = cur_bd_ptr;

    for(idx_bd = 0; idx_bd < num_required_bd; idx_bd++){
        // If this is a single BD transmission, both flags will be raised.
        ctrl = 0;
        if(idx_bd == 0) ctrl |= XAXIDMA_BD_CTRL_TXSOF_MASK;
        if(idx_bd == (num_required_bd-1)) ctrl |= XAXIDMA_BD_CTRL_TXEOF_MASK;

        status = XAxiDma_BdSetBufAddr(cur_bd_ptr, (u32)bd_addr[idx_bd]);
        status |= XAxiDma_BdSetLength(cur_bd_ptr, bd_len[idx_bd], tx_ring_ptr->MaxTransferLen);

        // TODO: this is a cache-sensitive context. In architectures with the cache enabled,
        //  we should flush the cashe for the range covered in this BD.
        //XCACHE_FLUSH_DCACHE_RANGE(bd_addr[idx_bd], bd_len[idx_bd]);

        if(status != XST_SUCCESS) {
            xil_printf("WLAN_AXI_ETHERNET_INTR: ERROR setting ETH TX BD! Err = %d\n", status);
            status = XAxiDma_BdRingFree(tx_ring_ptr, num_required_bd, first_bd_ptr);
            wlan_platform_intc_set_state(prev_interrupt_state);
            return WLAN_AXI_ETH_INTR_SEND_ERR_OTHER;
        }

        XAxiDma_BdSetCtrl(cur_bd_ptr, ctrl);
        cur_bd_ptr = (XAxiDma_Bd*)XAxiDma_BdRingNext(tx_ring_ptr, cur_bd_ptr);
    }

    // Push the BD ring to hardware; this initiates the actual DMA transfer and Ethernet Tx
    status = XAxiDma_BdRingToHw(tx_ring_ptr, num_required_bd, first_bd_ptr);
    if(status != XST_SUCCESS){
        xil_printf("WLAN_AXI_ETHERNET_INTR: ERROR: TX XAxiDma_BdRingToHw! Err = %d\n", status);
        status = XAxiDma_BdRingFree(tx_ring_ptr, num_required_bd, first_bd_ptr);
        return WLAN_AXI_ETH_INTR_SEND_ERR_OTHER;
    }

    wlan_platform_intc_set_state(prev_interrupt_state);
    return WLAN_SUCCESS;
}


/**
 * @brief Attach any free buffer descriptors
 *
 * This function may be called at any time to attach any free buffer descriptors to free queue entries
 * provided by the High MAC Framework. If either no buffer descriptors are free or there are no free
 * queue entries, this function will successfully do nothing.
 *
 * @param peripheral_args_t* peripheral_args
 *          - necessary arguments to distinguish between multiple instances of this peripheral
 * @return none
 */
void wlan_axi_eth_intr_attach_free_rx_bd(peripheral_args_t* peripheral_args) {
    int status;
    int iter;
    u32 bd_count;
    u32 bd_queue_pairs_to_process;
    u32 bd_queue_pairs_processed;

    XAxiDma* eth_dma_instance_ptr;
    XAxiDma_BdRing* rx_ring_ptr;
    XAxiDma_Bd* first_bd_ptr;
    XAxiDma_Bd* cur_bd_ptr;

    dl_list checkout;
    dl_entry* queue_entry;

    interrupt_state_t prev_interrupt_state = wlan_platform_intc_stop();

    eth_dma_instance_ptr = (XAxiDma*)(peripheral_args->driver_instance);

    // Get the Rx ring pointer and the number of free Rx buffer descriptors
    rx_ring_ptr = XAxiDma_GetRxRing(eth_dma_instance_ptr);
    bd_count = XAxiDma_BdRingGetFreeCnt(rx_ring_ptr);

    // If there are no BDs, then we are done
    if (bd_count == 0) {
        wlan_platform_intc_set_state(prev_interrupt_state);
        return;
    }

    // Initialize the list to checkout Tx queue entries
    dl_list_init(&checkout);

    // Attempt to checkout Tx queue entries for all free buffer descriptors
    queue_checkout_list(&checkout, bd_count);

    // If there were not enough Tx queue entries available, the length of the
    // checkout list will be the number of free Tx queue entries that were
    // found.  Only process buffer descriptors that have a corresponding Tx
    // queue entry.
    bd_queue_pairs_to_process = WLAN_MIN(bd_count, checkout.length);

    if (bd_queue_pairs_to_process > 0) {

        // Initialize the number of buffer descriptors processed
        bd_queue_pairs_processed = 0;

        // Allocate the correct number of Rx buffer descriptors that have
        // been freed and have Tx queue entries available.
        status = XAxiDma_BdRingAlloc(rx_ring_ptr, bd_queue_pairs_to_process, &first_bd_ptr);
        if(status != XST_SUCCESS) {xil_printf("WLAN_AXI_ETHERNET_INTR: Error in XAxiDma_BdRingAlloc()! Err = %d\n", status);
            wlan_platform_intc_set_state(prev_interrupt_state);
            return;
        }

        // Initialize loop variables
        iter             = checkout.length;
        queue_entry      = checkout.first;
        cur_bd_ptr       = first_bd_ptr;

        while ((queue_entry != NULL) && (iter-- > 0)) {

            // Initialize the Rx buffer descriptor
            status = _init_rx_bd(cur_bd_ptr, queue_entry, WLAN_AXI_ETH_RX_INTR_BUF_SIZE, rx_ring_ptr->MaxTransferLen);

            if (status != XST_SUCCESS) {
                // Clean up buffer descriptors and Tx queues
                //     NOTE:  Regardless of where we are in the update, we will check
                //         back in everything so the function can start fresh next invocation
                status = XAxiDma_BdRingUnAlloc(rx_ring_ptr, bd_queue_pairs_to_process, first_bd_ptr);
                if(status != XST_SUCCESS) {xil_printf("WLAN_AXI_ETHERNET_INTR: Error in XAxiDma_BdRingUnAlloc()! Err = %d\n", status);}

                queue_checkin_list(&checkout);
                wlan_platform_intc_set_state(prev_interrupt_state);
                return;
            }

            // Update the BD and queue entry pointers to the next list elements
            //     NOTE: This loop traverses both lists simultaneously
            cur_bd_ptr     = XAxiDma_BdRingNext(rx_ring_ptr, cur_bd_ptr);
            queue_entry = dl_entry_next(queue_entry);
            bd_queue_pairs_processed++;

        }

        if (bd_queue_pairs_processed == bd_queue_pairs_to_process) {
            // Push the Rx BD ring to hardware and start receiving
            status = XAxiDma_BdRingToHw(rx_ring_ptr, bd_queue_pairs_to_process, first_bd_ptr);
            if(status != XST_SUCCESS) {xil_printf("WLAN_AXI_ETHERNET_INTR: XAxiDma_BdRingToHw failed! Err = %d\n", status);}
        } else {
            // Clean up buffer descriptors and Tx queues
            xil_printf("WLAN_AXI_ETHERNET_INTR: Error processing BD-queue pairs\n");

            status = XAxiDma_BdRingUnAlloc(rx_ring_ptr, bd_queue_pairs_to_process, first_bd_ptr);
            if(status != XST_SUCCESS) {xil_printf("WLAN_AXI_ETHERNET_INTR: Error in XAxiDma_BdRingUnAlloc()! Err = %d\n", status);}

            queue_checkin_list(&checkout);
        }
    }
    wlan_platform_intc_set_state(prev_interrupt_state);
}

int wlan_axi_eth_intr_get_mtu(){
    return 9000;
}

// Local Helper Functions

/*****************************************************************************/
/**
 * @brief Initializes an Rx buffer descriptor to use the given Tx queue entry
 *
 * @param XAxiDma_Bd * bd_ptr
 *  - Pointer to buffer descriptor to be initialized
 * @param dl_entry * qe_ptr
 *  - Pointer to Tx queue element
 * @param u32 max_transfer_len
 *  - Max transfer length for Rx BD
 * @param u32 LengthMask
 *  - Mask for length in Rx BD
 *
 * @return WLAN_SUCCESS or WLAN_FAILURE
 */
static int _init_rx_bd(XAxiDma_Bd* bd_ptr, dl_entry* qe_ptr, u32 max_transfer_len, u32 LengthMask) {
    int status;
    u32 buf_addr;

    if ((bd_ptr == NULL) || (qe_ptr == NULL)) { return WLAN_FAILURE; }

    // Set the memory address for this BD's buffer to the corresponding Tx queue entry buffer
    //     NOTE:  This pointer is offset by the size of a MAC header and LLC header, which results
    //         in the Ethernet payload being copied to its post-encapsulated location. This
    //         speeds up the encapsulation process by skipping any re-copying of Ethernet payloads
    buf_addr = (u32)((void*)((eth_rx_queue_buffer_t*)(qe_ptr->data))->pkt);

    status   = XAxiDma_BdSetBufAddr(bd_ptr, buf_addr);
    if (status != XST_SUCCESS) { xil_printf("WLAN_AXI_ETHERNET_INTR: XAxiDma_BdSetBufAddr failed (addr 0x08x)! Err = %d\n", buf_addr, status); return WLAN_FAILURE; }

    // Set every Rx BD to max length (this assures 1 BD per Rx pkt)
    //     NOTE:  Jumbo Ethernet frames are not supported by the Ethernet device (ie the XAE_JUMBO_OPTION is cleared),
    //         so the WLAN_ETH_PKT_BUF_SIZE must be at least large enough to support standard MTUs (ie greater than
    //         1522 bytes) so the assumption of 1 BD = 1 Rx pkt is met.
    status = XAxiDma_BdSetLength(bd_ptr, max_transfer_len, LengthMask);
    if (status != XST_SUCCESS) { xil_printf("WLAN_AXI_ETHERNET_INTR: XAxiDma_BdSetLength failed (addr 0x08x)! Err = %d\n", buf_addr, status); return WLAN_FAILURE; }

    // Rx BD's don't need control flags before use; DMA populates these post-Rx
    XAxiDma_BdSetCtrl(bd_ptr, 0);

    return WLAN_SUCCESS;
}

static u32 _wlan_axi_eth_intr_calc_num_bd(u32 mem_size){
    return (mem_size/XAXIDMA_BD_MINIMUM_ALIGNMENT);
}

static void _eth_tx_interrupt_handler(void *callback_arg){
    XAxiDma_BdRing* tx_ring_ptr;
    u32 irq_status;
    XAxiDma* eth_dma_instance_ptr;

    peripheral_args_t* peripheral_args = (peripheral_args_t*)callback_arg;
    eth_dma_instance_ptr = (XAxiDma*)(peripheral_args->driver_instance);

    tx_ring_ptr = XAxiDma_GetTxRing(eth_dma_instance_ptr);

    XAxiDma_BdRingIntDisable(tx_ring_ptr, XAXIDMA_IRQ_ALL_MASK);
    irq_status = XAxiDma_BdRingGetIrq(tx_ring_ptr);

    XAxiDma_BdRingAckIrq(tx_ring_ptr, irq_status);

    if (irq_status & XAXIDMA_IRQ_ERROR_MASK) {
        xil_printf("WLAN_AXI_ETHERNET_INTR: %s: error interrupt asserted\n", __FUNCTION__);
        XAxiDma_Reset(eth_dma_instance_ptr);

        return;
    }

    if (irq_status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)) {
        _wlan_axi_eth_intr_free_tx_bd(peripheral_args);
    }

    XAxiDma_BdRingIntEnable(tx_ring_ptr, XAXIDMA_IRQ_ALL_MASK);


}

static void _eth_rx_interrupt_handler(void *callback_arg){
    XAxiDma_BdRing* rx_ring_ptr;
    u32 irq_status;
    XAxiDma_Bd* bd_set_to_process_ptr;
    u32 eth_rx_len;
    u32 eth_rx_buf;
    u32 bd_set_count;
    u32 status;
    eth_rx_queue_buffer_t* eth_rx_queue_buffer;
    XAxiDma* eth_dma_instance_ptr;


    // FIXME: In the case of >WLAN_AXI_ETH_RX_INTR_BUF_SIZE receptions,
    //  packet won't be dropped but rather split across multiple BDs. We
    //  should only pass a received Ethernet frame to the framework for
    //  further processing if it is both a Start of Frame and End of Frame.

    peripheral_args_t* peripheral_args = (peripheral_args_t*)callback_arg;
    eth_dma_instance_ptr = (XAxiDma*)(peripheral_args->driver_instance);

    rx_ring_ptr = XAxiDma_GetRxRing(eth_dma_instance_ptr);
    irq_status = XAxiDma_BdRingGetIrq(rx_ring_ptr);

    if (!(irq_status & XAXIDMA_IRQ_ERROR_MASK)) {
        // At least one reception is completed

        // Disable the interrupt and then acknowledge the interrupt
        XAxiDma_BdRingIntDisable(rx_ring_ptr, irq_status);
        XAxiDma_BdRingAckIrq(rx_ring_ptr, irq_status);

        // Get all the BDs that are available
        //     NOTE:  Use global variable so it is easy to process a sub-set of
        //         packets at a time.
        bd_set_count = XAxiDma_BdRingFromHw(rx_ring_ptr, XAXIDMA_ALL_BDS, &bd_set_to_process_ptr);

        if(bd_set_count > 0) {
            while (bd_set_count > 0) {
                // Lookup length and data pointers from the DMA metadata
                eth_rx_len = XAxiDma_BdGetActualLength(bd_set_to_process_ptr, rx_ring_ptr->MaxTransferLen);
                eth_rx_buf = XAxiDma_BdGetBufAddr(bd_set_to_process_ptr);

                // Get the Rx Eth queue entry pointer. This is located further back in the queue_buffer_t struct.
                //
                eth_rx_queue_buffer = (eth_rx_queue_buffer_t*)( (u8*)eth_rx_buf - offsetof(eth_rx_queue_buffer_t, pkt));
                eth_rx_queue_buffer->length = eth_rx_len;

                // Check and make sure this is both the start and end of a frame.
                //  A large MTU reception could be split among multiple BDs. We do
                //  not currently support jumbo receptions.
                // FIXME: we need similar code in the emac ps peripheral.
                if ( ((XAxiDma_BdGetSts(bd_set_to_process_ptr) & XAXIDMA_BD_STS_RXSOF_MASK) == 0) ||
                     ((XAxiDma_BdGetSts(bd_set_to_process_ptr) & XAXIDMA_BD_STS_RXEOF_MASK) == 0) ){
                    queue_checkin(eth_rx_queue_buffer->pyld_queue_hdr.dle);
                } else {
                    // Add the Rx Eth queue entry to the list of packets to be processed by the High Framework
                    if( peripheral_args->callback0(eth_rx_queue_buffer) == 0 ){
                        queue_checkin(eth_rx_queue_buffer->pyld_queue_hdr.dle);
                    }
                }

                // Free the ETH DMA buffer descriptor
                status = XAxiDma_BdRingFree(rx_ring_ptr, 1, bd_set_to_process_ptr);
                if(status != XST_SUCCESS) {
                        xil_printf("WLAN_AXI_ETHERNET_INTR: Error in XAxiDma_BdRingFree of Rx BD! Err = %d\n", status);
                }

                bd_set_count--;

                // Update to the next BD in the chain for the next iteration
                bd_set_to_process_ptr = XAxiDma_BdRingNext(rx_ring_ptr, bd_set_to_process_ptr);
            }

            // At this point, we heave dealt with every BD in the ring

            // Attach any newly free BDs
            wlan_axi_eth_intr_attach_free_rx_bd(peripheral_args);
        }

        // Finished all available Eth Rx - re-enable interrupt
        XAxiDma_BdRingIntEnable(rx_ring_ptr, irq_status);

    } else {
        // Acknowledge the error interrupt
        XAxiDma_BdRingAckIrq(rx_ring_ptr, XAXIDMA_IRQ_ERROR_MASK);
        // TODO:  Clean up from error condition !!!
    }

    return;
}

/**
 * @brief Free any complete Tx BDs
 *
 * @param peripheral_args_t* peripheral_args
 *          - necessary arguments to distinguish between multiple instances of this peripheral
 * @return none
 */
inline void _wlan_axi_eth_intr_free_tx_bd(peripheral_args_t* peripheral_args) {
       int i;
       int status;

       XAxiDma* eth_dma_instance_ptr;
       eth_tx_queue_buffer_t* eth_tx_queue_buffer;
       XAxiDma_BdRing* eth_tx_ring_ptr;
       u32 eth_tx_buf;

       int processed_bd_count;

       XAxiDma_Bd* bd_set_ptr = NULL;
       XAxiDma_Bd* bd_ptr = NULL;

       eth_dma_instance_ptr = (XAxiDma*)(peripheral_args->driver_instance);
       eth_tx_ring_ptr = XAxiDma_GetTxRing(eth_dma_instance_ptr);

       // Check how many buffer descriptors have been processed
       processed_bd_count = XAxiDma_BdRingFromHw(eth_tx_ring_ptr, XAXIDMA_ALL_BDS, &bd_set_ptr);

       // Initialize the working descriptor pointer
       bd_ptr = bd_set_ptr;

       for (i = 0; i < processed_bd_count; i++) {

           // Get the status of the descriptor
           status = XAxiDma_BdGetSts(bd_ptr);

           // Check the status
           if ((status & XAXIDMA_BD_STS_ALL_ERR_MASK) || (!(status & XAXIDMA_BD_STS_COMPLETE_MASK))) {
               xil_printf("WLAN_AXI_ETHERNET_INTR: Error in _wlan_axi_eth_poll_free_tx_bd(): Tx BD contained error status\n");
           }

           if(XAxiDma_BdGetCtrl(bd_ptr) & XAXIDMA_BD_CTRL_TXSOF_MASK){
               // This is the start of a frame, i.e. it is seg0 of a queue buffer.

               // Call the platform's Tx Done callback so it can clean up
               eth_tx_buf = XAxiDma_BdGetBufAddr(bd_ptr);

               // Get the Rx Eth queue entry pointer. This is located further back in the queue_buffer_t struct
               eth_tx_queue_buffer = (eth_tx_queue_buffer_t*)( (u8*)eth_tx_buf - offsetof(eth_tx_queue_buffer_t, seg0));

               // Per the documentation for XAxiDMA_BdRingFromHw, "If hardware has partially
               //  completed a packet spanning multiple BDs, then none of the BDs for that
               //  packet will be included in the results." So, if we see the BD marked as a
               //  start of frame, we know the entire frame must be complete. So, we can call
               //  the _done_callback() function even if we have not finished looping through
               //  every BD.
               peripheral_args->callback1(eth_tx_queue_buffer);
           }

           // Get next descriptor
           bd_ptr = (XAxiDma_Bd*)XAxiDma_BdRingNext(eth_tx_ring_ptr, bd_ptr);
        }


        // Free all processed RX BDs for future transmission
        status = XAxiDma_BdRingFree(eth_tx_ring_ptr, processed_bd_count, bd_set_ptr);

        if (status != XST_SUCCESS) {
            xil_printf("WLAN_AXI_ETHERNET_INTR: Error in _wlan_axi_eth_poll_free_tx_bd(): Unable to free Tx ring");
            return;
        }
        return;
}