source: ReferenceDesigns/w3_802.11/c/wlan_w3_high/include/w3_high.h

#ifndef W3_PLATFORM_HIGH_H_
#define W3_PLATFORM_HIGH_H_

/*********************************************************************
 * Mapping macros from xparameters.h
 *
 * The BSP generates xparameters.h to define macros for hardware-specific
 * parameters, including peripheral memory addresses, peripheral IDs,
 * interrupt IDs, etc.
 *
 * The macros below map the BSP-generated macros ("XPAR_...") to the
 * hardware-agnostic names used by the 802.11 Ref Design C code. Each
 * platform must implement this mapping in wlan_platform_common.h.
 *
 **********************************************************************/

// On-chip Aux BRAM
#define AUX_BRAM_BASEADDR       XPAR_MB_HIGH_AUX_BRAM_CTRL_S_AXI_BASEADDR
#define AUX_BRAM_HIGHADDR       XPAR_MB_HIGH_AUX_BRAM_CTRL_S_AXI_HIGHADDR
#define AUX_BRAM_SIZE           CALC_MEM_SIZE(AUX_BRAM_BASEADDR, AUX_BRAM_HIGHADDR)

// Aux BRAM set aside for w3 platform usage
#define AUX_BRAM_ETH_BD_MEM_SIZE    (240 * 64)

/********************************************************************
 * Portal Ethernet Aux. Space
 *
 * Space is set aside for the use of wlan_platform's Ethernet
 * implementation
 ********************************************************************/
#define PORTAL_ETH_BD_MEM_BASEADDR         (AUX_BRAM_HIGHADDR - AUX_BRAM_ETH_BD_MEM_SIZE + 1)
#define PORTAL_ETH_BD_MEM_SIZE          AUX_BRAM_ETH_BD_MEM_SIZE

// Off-chip DRAM
#define DRAM_BASEADDR           XPAR_DDR3_SODIMM_S_AXI_BASEADDR
#define DRAM_HIGHADDR           XPAR_DDR3_SODIMM_S_AXI_HIGHADDR
#define DRAM_SIZE               CALC_MEM_SIZE(DRAM_BASEADDR,DRAM_HIGHADDR)

// DRAM set aside for w3 platform usage
#define DRAM_ETH_BD_MEM_SIZE    (15 * 64)

/********************************************************************
 * wlan_exp Ethernet DRAM Space
 *
 * Space is set aside for the use of wlan_platform's Ethernet
 * implementation
 ********************************************************************/
// There is a bug deep within Xil_DCacheFlushRange that prevents us from using
//  the 0xFFFFFFFF address in an Ethernet buffer descriptor. Instead, we will
//  reserve platform usage of DRAM at the base address of DRAM
#define WLAN_EXP_ETH_BD_MEM_BASEADDR    DRAM_BASEADDR
#define WLAN_EXP_ETH_BD_MEM_SIZE        DRAM_ETH_BD_MEM_SIZE
#define WLAN_EXP_ETH_BD_MEM_HIGHADDR    CALC_MEM_HIGH_ADDR(WLAN_EXP_ETH_BD_MEM_BASEADDR, WLAN_EXP_ETH_BD_MEM_SIZE)

//---------------------------------------
// Peripherals accessible by CPU High
//  Each core has a device ID (used by Xilinx drivers to initialize config structs)
//  Cores that generate interrupts have interrupt IDs (identifies interrupt source for connecting ISRs)

// Interrupt controller
#define PLATFORM_DEV_ID_INTC                 XPAR_INTC_0_DEVICE_ID              ///< XParameters rename of interrupt controller device ID

// GPIO for user I/O inputs
#define PLATFORM_DEV_ID_USRIO_GPIO           XPAR_MB_HIGH_SW_GPIO_DEVICE_ID     ///< XParameters rename of device ID of GPIO
#define PLATFORM_INT_ID_USRIO_GPIO           XPAR_INTC_0_GPIO_0_VEC_ID          ///< XParameters rename of GPIO interrupt ID

// Timer
#define PLATFORM_DEV_ID_TIMER                XPAR_TMRCTR_0_DEVICE_ID
#define TIMER_FREQ_HZ                        XPAR_TMRCTR_0_CLOCK_FREQ_HZ
#define PLATFORM_INT_ID_TIMER                XPAR_INTC_0_TMRCTR_0_VEC_ID        ///< XParameters rename of timer interrupt ID

// Central DMA (CMDA)
#define PLATFORM_DEV_ID_CDMA                 XPAR_AXI_CDMA_0_DEVICE_ID

// Mailbox Interrupt
#define PLATFORM_INT_ID_MAILBOX              XPAR_INTC_0_MBOX_0_VEC_ID

// wlan_exp Ethernet ID
#define WLAN_EXP_ETH_MAC_ID                  ETH_B_MAC_DEVICE_ID
#define WLAN_EXP_ETH_DMA_ID                  ETH_B_DMA_DEVICE_ID

// Timer
#define TIMER_DUR_US                    64

#endif /* W3_PLATFORM_HIGH_H_ */