#include "wlan_mac_high_sw_config.h" #include "xil_cache.h" #include "wlan_platform_high.h" #include "w3_high.h" #include "w3_eth.h" #include "w3_uart.h" #include "w3_high_userio.h" #include "w3_userio_util.h" #include "w3_iic_eeprom.h" #include "w3_sw_intr.h" #include "w3_common.h" #include "wlan_platform_timer.h" #include "wlan_common_types.h" #include "wlan_platform_common.h" #include "wlan_mac_high.h" #include "wlan_mac_schedule.h" #include "wlan_exp_common.h" #include "wlan_exp_node.h" #include "wlan_exp_transport.h" #include "wlan_mac_queue.h" static const platform_high_dev_info_t w3_platform_high_dev_info = { .aux_bram_baseaddr = AUX_BRAM_BASEADDR, .aux_bram_size = AUX_BRAM_SIZE - PORTAL_ETH_BD_MEM_SIZE, .dram_baseaddr = WLAN_EXP_ETH_BD_MEM_HIGHADDR + 1, .dram_size = DRAM_SIZE - WLAN_EXP_ETH_BD_MEM_SIZE, .cdma_dev_id = PLATFORM_DEV_ID_CDMA, .mailbox_int_id = PLATFORM_INT_ID_MAILBOX, .timer_dur_us = TIMER_DUR_US, }; typedef struct _w3_node_info_t{ u64 fpga_dna; // FPGA DNA value, unique ID per chip s8 wlan_max_tx_power_dbm; // RF interface maximum transmit power s8 wlan_min_tx_power_dbm; // RF interface minimum transmit power } __attribute__((__packed__)) _w3_node_info_t; static _w3_node_info_t w3_node_info; ASSERT_TYPE_SIZE(_w3_node_info_t, 10); int _init_wlan_exp_node_info(); void wlan_platform_cpu_high_init() { Xil_AssertSetCallback((Xil_AssertCallback)wlan_assert_print); // Disable I and D cache Xil_DCacheDisable(); Xil_ICacheDisable(); // Enable exceptions - exceptions *must* be enabled on MicroBlaze // to handle unaligned memory accesses microblaze_enable_exceptions(); // Initialize HW platform wlan_platform_common_init(); // Fill in node info struct _init_wlan_exp_node_info(); return; } platform_high_dev_info_t wlan_platform_high_get_dev_info(){ return w3_platform_high_dev_info; } void wlan_platform_high_poll(){ } int wlan_platform_high_init() { int status; status = wlan_platform_intc_init(PLATFORM_DEV_ID_INTC); status |= wlan_timer_init(PLATFORM_DEV_ID_TIMER, TIMER_DUR_US*(TIMER_FREQ_HZ/1000000)); // 64 usec status |= wlan_timer_setup_interrupt(PLATFORM_INT_ID_TIMER, wlan_mac_schedule_poll); status |= w3_uart_init(); status |= w3_uart_setup_interrupt(); status |= w3_high_userio_init(); status |= w3_high_userio_setup_interrupt(); status |= w3_sw_intr_init(); // Initialize Ethernet in wlan_platform status |= w3_wlan_platform_ethernet_init(); // Set stack protection addresses // Set stack protection addresses // Linker sets these variables at build time extern int _stack_end; ///< Start of the stack (stack counts backwards) extern int __stack; ///< End of the stack mtshr(&__stack); mtslr(&_stack_end); return status; } void wlan_platform_free_queue_entry_notify(){ #if WLAN_SW_CONFIG_ENABLE_ETH_BRIDGE w3_wlan_platform_ethernet_free_queue_entry_notify(); #endif } void wlan_platform_high_userio_disp_status(userio_disp_high_status_t status, int status_param){ static application_role_t application_role = APPLICATION_ROLE_UNKNOWN; switch(status){ case USERIO_DISP_STATUS_IDENTIFY: { blink_hex_display(25, 200000); } break; case USERIO_DISP_STATUS_APPLICATION_ROLE: { application_role = (application_role_t)status_param; if(application_role == APPLICATION_ROLE_AP){ // Set Periodic blinking of hex display (period of 500 with min of 2 and max of 400) set_hex_pwm_period(500); set_hex_pwm_min_max(2, 400); enable_hex_pwm(); } } break; case USERIO_DISP_STATUS_MEMBER_LIST_UPDATE: { if(application_role == APPLICATION_ROLE_AP){ write_hex_display_with_pwm((u8)status_param); } else { write_hex_display((u8)status_param); } } break; case USERIO_DISP_STATUS_WLAN_EXP_CONFIGURE: { if( status_param ){ set_hex_display_right_dp(1); } else { set_hex_display_right_dp(0); } } break; case USERIO_DISP_STATUS_CPU_ERROR: { u32 error_code = (u32)status_param; if (status_param != WLAN_ERROR_CPU_STOP) { // Print error message xil_printf("\n\nERROR: CPU is halting with error code: E%X\n\n", (error_code & 0xF)); // Set the error code on the hex display set_hex_display_error_status(error_code & 0xF); // Enter infinite loop blinking the hex display blink_hex_display(0, 250000); } else { // Stop execution while (1) {}; } } break; default: break; } return; } #if WLAN_SW_CONFIG_ENABLE_WLAN_EXP int wlan_platform_wlan_exp_process_node_cmd(cmd_resp_hdr_t* cmd_hdr, eth_tx_queue_buffer_t* eth_tx_queue_buffer, u8* cmd_processed){ // // IMPORTANT ENDIAN NOTES: // - command // - header - Already endian swapped by the framework (safe to access directly) // - args - Must be endian swapped as necessary by code (framework does not know the contents of the command) // - response // - header - Will be endian swapped by the framework (safe to write directly) // - args - Must be endian swapped as necessary by code (framework does not know the contents of the response) // u32 resp_sent = NO_RESP_SENT; u32 cmd_id = CMD_TO_CMDID(cmd_hdr->cmd); // Segment 0 length includes a fully formed command response header // because one was created with default values suitable for a responseless // acknowledgment. cmd_resp_hdr_t* resp_hdr = (cmd_resp_hdr_t*)(eth_tx_queue_buffer->seg0 + eth_tx_queue_buffer->seg0_len - sizeof(cmd_resp_hdr_t)); u32* cmd_args_32 = (u32*)((u8*)cmd_hdr + sizeof(cmd_resp_hdr_t)); u32* resp_args_32 = (u32*)((u8*)resp_hdr + sizeof(cmd_resp_hdr_t)); u32 resp_index = 0; // NOTE: Response header cmd, length, and num_args fields have already been initialized. // *cmd_processed = 1; switch(cmd_id){ default: *cmd_processed = 0; break; //--------------------------------------------------------------------- case CMDID_DEV_EEPROM: { // Read / Write values from / to EEPROM // // Write Message format: // cmd_args_32[0] Command == CMD_PARAM_WRITE_VAL // cmd_args_32[1] EEPROM (0 = ON_BOARD / 1 = FMC) // cmd_args_32[2] Address // cmd_args_32[3] Length (Number of u8 bytes to write) // cmd_args_32[4:] Values to write (Length u32 values each containing a single byte to write) // Response format: // resp_args_32[0] Status // // Read Message format: // cmd_args_32[0] Command == CMD_PARAM_READ_VAL // cmd_args_32[1] EEPROM Device (1 = ON_BOARD / 0 = FMC) // cmd_args_32[2] Address // cmd_args_32[3] Length (number of u8 bytes to read) // Response format: // resp_args_32[0] Status // resp_args_32[1] Length (Number of u8 bytes read) // resp_args_32[2:] EEPROM values (Length u32 values each containing a single byte read) // #define EEPROM_BASEADDR XPAR_W3_IIC_EEPROM_ONBOARD_BASEADDR #define FMC_EEPROM_BASEADDR XPAR_W3_IIC_EEPROM_FMC_BASEADDR u32 eeprom_idx; int eeprom_status; u8 byte_to_write; u32 status = CMD_PARAM_SUCCESS; u32 msg_cmd = Xil_Ntohl(cmd_args_32[0]); u32 eeprom_device = Xil_Ntohl(cmd_args_32[1]); u32 eeprom_addr = (Xil_Ntohl(cmd_args_32[2]) & 0xFFFF); u32 eeprom_length = Xil_Ntohl(cmd_args_32[3]); u32 use_default_resp = WLAN_EXP_TRUE; u32 eeprom_ba = EEPROM_BASEADDR; u32 max_resp_len = wlan_exp_transport_get_max_pkt_words(); // Select EEPROM device if (eeprom_device) { eeprom_ba = EEPROM_BASEADDR; } else { #if FMC_EEPROM_BASEADDR eeprom_ba = FMC_EEPROM_BASEADDR; #else wlan_exp_printf(WLAN_EXP_PRINT_ERROR, print_type_node, "FMC EEPROM not supported\n"); msg_cmd = CMD_PARAM_RSVD; #endif } switch (msg_cmd) { case CMD_PARAM_WRITE_VAL: wlan_exp_printf(WLAN_EXP_PRINT_INFO, print_type_node, "Write EEPROM:\n"); wlan_exp_printf(WLAN_EXP_PRINT_INFO, print_type_node, " Addr: 0x%08x\n", eeprom_addr); wlan_exp_printf(WLAN_EXP_PRINT_INFO, print_type_node, " Len: %d\n", eeprom_length); // Don't bother if length is clearly bogus if(eeprom_length < max_resp_len) { for (eeprom_idx = 0; eeprom_idx < eeprom_length; eeprom_idx++) { // Endian swap payload and extract the byte to write byte_to_write = (Xil_Ntohl(cmd_args_32[eeprom_idx + 4]) & 0xFF); // Write the byte and break if there was an EEPROM failure eeprom_status = iic_eeprom_write_byte(eeprom_ba, (eeprom_addr + eeprom_idx), byte_to_write, XPAR_CPU_ID); if (eeprom_status == IIC_EEPROM_FAILURE) { wlan_exp_printf(WLAN_EXP_PRINT_ERROR, print_type_node, "CMDID_DEV_EEPROM write failed at byte %d\n", eeprom_idx); status = CMD_PARAM_ERROR; break; } } } else { wlan_exp_printf(WLAN_EXP_PRINT_ERROR, print_type_node, "CMDID_DEV_EEPROM write longer than %d bytes\n", max_resp_len); status = CMD_PARAM_ERROR; } break; case CMD_PARAM_READ_VAL: // There's a chicken and egg problem in this command trying to use the // wlan_exp_add_u32_resp_arg() utility. The first word, status, might // become CMD_PARAM_ERROR as we are well into reading bytes from the // EEPROM. To use the wlan_exp_add_u32_resp_arg() function, we need to // know the final value of the first word before writing any other words // to the response. We will simply leave the "old" resp_index method of // writing a response. wlan_exp_printf(WLAN_EXP_PRINT_INFO, print_type_node, "Read EEPROM:\n"); wlan_exp_printf(WLAN_EXP_PRINT_INFO, print_type_node, " Addr: 0x%08x\n", eeprom_addr); wlan_exp_printf(WLAN_EXP_PRINT_INFO, print_type_node, " Len: %d\n", eeprom_length); if (eeprom_length < max_resp_len) { // Don't set the default response use_default_resp = WLAN_EXP_FALSE; for (eeprom_idx = 0; eeprom_idx < eeprom_length; eeprom_idx++) { // Read the byte and break if there was an EEPROM failure eeprom_status = iic_eeprom_read_byte(eeprom_ba, (eeprom_addr + eeprom_idx), XPAR_CPU_ID); if (eeprom_status == IIC_EEPROM_FAILURE) { wlan_exp_printf(WLAN_EXP_PRINT_ERROR, print_type_node, "CMDID_DEV_EEPROM write failed at byte %d\n", eeprom_idx); status = CMD_PARAM_ERROR; break; } // Add the byte read and Endian swap the payload // - This modified the output Ethernet packet but does not update the resp_index variable resp_args_32[resp_index + eeprom_idx + 2] = Xil_Htonl(eeprom_status & 0xFF); } // Add length argument to response resp_args_32[resp_index++] = Xil_Htonl(status); resp_args_32[resp_index++] = Xil_Htonl(eeprom_idx); resp_index += eeprom_idx; // Update response index for all EEPROM bytes resp_hdr->length += (resp_index * sizeof(resp_args_32)); eth_tx_queue_buffer->seg0_len += (resp_index * sizeof(u32)); resp_hdr->num_u32_args = resp_index; } else { wlan_exp_printf(WLAN_EXP_PRINT_ERROR, print_type_node, "CMDID_DEV_EEPROM read longer than %d bytes\n", max_resp_len); status = CMD_PARAM_ERROR; } break; case CMD_PARAM_RSVD: status = CMD_PARAM_ERROR; break; default: wlan_exp_printf(WLAN_EXP_PRINT_ERROR, print_type_node, "Unknown command for 0x%6x: %d\n", cmd_id, msg_cmd); status = CMD_PARAM_ERROR; break; } if (use_default_resp) { // Send default response wlan_exp_add_u32_resp_arg(eth_tx_queue_buffer, resp_hdr, status); } } break; } return resp_sent; } #endif int wlan_platform_high_copy_info(u8* dest){ memcpy(dest, &w3_node_info, sizeof(_w3_node_info_t)); return sizeof(_w3_node_info_t); } int _init_wlan_exp_node_info(){ wlan_mac_hw_info_t hw_info = wlan_platform_get_hw_info(); xil_printf("Initializing node Serial Number : %s-%05d\n", hw_info.serial_number_prefix, hw_info.serial_number); //FIXME: Did I get the endianness right on this? w3_node_info.fpga_dna = (((u64)w3_eeprom_read_fpga_dna(EEPROM_BASEADDR, 1)) << 32) + (u64)w3_eeprom_read_fpga_dna(EEPROM_BASEADDR, 0); w3_node_info.wlan_max_tx_power_dbm = TX_POWER_MAX_DBM; w3_node_info.wlan_min_tx_power_dbm = TX_POWER_MIN_DBM; return WLAN_SUCCESS; }