source: ReferenceDesigns/w3_802.11/c/wlan_w3_low/include/w3_phy_util.h

Last change on this file was 6319, checked in by chunter, 5 years ago

1.8.0 release wlan-mac-se
File size: 15.1 KB
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1/** @file wlan_phy_util.h
2 *  @brief Physical Layer Utility
3 *
4 *  This contains code for configuring low-level parameters in the PHY and hardware.
5 *
6 *  @copyright Copyright 2013-2019, Mango Communications. All rights reserved.
7 *          Distributed under the Mango Communications Reference Design License
8 *                See LICENSE.txt included in the design archive or
9 *                at http://mangocomm.com/802.11/license
10 *
11 *  This file is part of the Mango 802.11 Reference Design (https://mangocomm.com/802.11)
12 */
13
14/*************************** Constant Definitions ****************************/
15#ifndef W3_PHY_UTIL_H_
16#define W3_PHY_UTIL_H_
17
18#include "xil_types.h"
19
20//Forward declarations
21enum phy_samp_rate_t;
22
23// ****************************************************************************
24// Define standard macros for base addresses and device IDs
25//     XPAR_ names will change with instance names in hardware
26//
27#define CLK_BASEADDR         XPAR_W3_CLOCK_CONTROLLER_BASEADDR
28#define DRAM_BASEADDR        XPAR_DDR3_2GB_SODIMM_MPMC_BASEADDR
29#define RC_BASEADDR          XPAR_RADIO_CONTROLLER_BASEADDR
30#define AD_BASEADDR          XPAR_W3_AD_CONTROLLER_BASEADDR
31
32// ****************************************************************************
33// RX PHY-level constants
34#define PHY_RX_RSSI_SUM_LEN       4
35#define PHY_RX_RSSI_SUM_LEN_BITS  2 // LOG2(PHY_RX_RSSI_SUM_LEN)
36
37// ****************************************************************************
38// RATE field values for SIGNAL/L-SIG in PHY preamble (IEEE 802.11-2012 18.3.4.2)
39//  DSSS 1M rate code is non-standard, used by our code to indicate DSSS Rx
40#define WLAN_PHY_RATE_DSSS_1M  0x1
41
42// ****************************************************************************
43// Data bytes per OFDM symbol
44//     NOTE:  Values from Table 17-3 of 2007 IEEE 802.11
45//
46#define N_DBPS_R6    24
47#define N_DBPS_R9    36
48#define N_DBPS_R12   48
49#define N_DBPS_R18   72
50#define N_DBPS_R24   96
51#define N_DBPS_R36  144
52#define N_DBPS_R48  192
53#define N_DBPS_R54  216
54
55
56// ****************************************************************************
57// Currently active antenna defines
58//
59#define RX_ACTIVE_ANTA  0x0
60#define RX_ACTIVE_ANTB  0x1
61#define RX_ACTIVE_ANTC  0x2
62#define RX_ACTIVE_ANTD  0x3
63
64// ****************************************************************************
65// PHY Register definitions
66//
67
68
69
70
71
72/**************************** Macro Definitions ******************************/
73
74#define REG_CLEAR_BITS(addr, mask) Xil_Out32(addr, (Xil_In32(addr) & ~(mask)))
75#define REG_SET_BITS(addr, mask)   Xil_Out32(addr, (Xil_In32(addr) | (mask)))
76
77//-----------------------------------------------
78// PHY Macros
79//
80#define wlan_phy_select_rx_antenna(d) Xil_Out32(WLAN_RX_REG_CFG, ((Xil_In32(WLAN_RX_REG_CFG) & ~WLAN_RX_REG_CFG_ANT_SEL_MASK) | (((d) & 0x3) << 15)))
81
82#define wlan_phy_enable_req_both_pkt_det()  Xil_Out32(WLAN_RX_REG_CFG, (Xil_In32(WLAN_RX_REG_CFG) | (WLAN_RX_REG_CFG_REQ_BOTH_PKT_DET_OFDM | WLAN_RX_REG_CFG_REQ_BOTH_PKT_DET_DSSS)))
83#define wlan_phy_disable_req_both_pkt_det() Xil_Out32(WLAN_RX_REG_CFG, (Xil_In32(WLAN_RX_REG_CFG) & ~(WLAN_RX_REG_CFG_REQ_BOTH_PKT_DET_OFDM | WLAN_RX_REG_CFG_REQ_BOTH_PKT_DET_DSSS)))
84
85#define wlan_phy_rx_set_max_pkt_len_kB(d) Xil_Out32(WLAN_RX_REG_CFG, (Xil_In32(WLAN_RX_REG_CFG) & ~WLAN_RX_REG_CFG_MAX_PKT_LEN_MASK) | (((d) << 17) & WLAN_RX_REG_CFG_MAX_PKT_LEN_MASK))
86#define wlan_phy_tx_set_max_pkt_len_kB(d) Xil_Out32(WLAN_TX_REG_CFG, (Xil_In32(WLAN_TX_REG_CFG) & ~WLAN_TX_REG_CFG_MAX_PKT_LEN_MASK) | (((d) << 8) & WLAN_TX_REG_CFG_MAX_PKT_LEN_MASK))
87
88#define wlan_phy_rx_set_max_pktbuf_addr(a) Xil_Out32(WLAN_RX_PKT_BUF_MAXADDR, (a))
89
90// The PHY header offsets deal in units of u64 words, so the << 13 is like a << 16 and >> 3 to convert u8 words to u64 words
91#define wlan_phy_rx_pkt_buf_phy_hdr_offset(d) Xil_Out32(WLAN_RX_PKT_BUF_SEL, ((Xil_In32(WLAN_RX_PKT_BUF_SEL) & (~0x00FF0000)) | (((d) << 13) & 0x00FF0000)))
92#define wlan_phy_tx_pkt_buf_phy_hdr_offset(d) Xil_Out32(WLAN_TX_REG_PKT_BUF_SEL, ((Xil_In32(WLAN_TX_REG_PKT_BUF_SEL) & (~0x00FF0000)) | (((d) << 13) & 0x00FF0000)))
93
94// Chan est offset is specified in units of u64 words; this macros converts a byte offset to u64 offset (hence the implicit >> 3, ie the 21 is (24 - 3))
95#define wlan_phy_rx_pkt_buf_h_est_offset(d) Xil_Out32(WLAN_RX_PKT_BUF_SEL, ((Xil_In32(WLAN_RX_PKT_BUF_SEL) & (~0xFF000000)) | (((d) << 21) & 0xFF000000)))
96
97#define wlan_phy_tx_set_scaling(pre, pay) Xil_Out32(WLAN_TX_REG_SCALING, (((pre) & 0xFFFF) | (((pay) & 0xFFFF) << 16)))
98
99#define wlan_phy_rx_pkt_buf_dsss(d) Xil_Out32(WLAN_RX_PKT_BUF_SEL, ((Xil_In32(WLAN_RX_PKT_BUF_SEL) & (~0x00000F00)) | (((d) << 8) & 0x00000F00)))
100#define wlan_phy_rx_pkt_buf_ofdm(d) Xil_Out32(WLAN_RX_PKT_BUF_SEL, ((Xil_In32(WLAN_RX_PKT_BUF_SEL) & (~0x0000000F)) | ((d) & 0x0000000F)))
101
102#define wlan_phy_tx_pkt_buf(d) Xil_Out32(WLAN_TX_REG_PKT_BUF_SEL, ((Xil_In32(WLAN_TX_REG_PKT_BUF_SEL) & (~0x0000000F)) | ((d) & 0x0000000F)))
103
104#define wlan_phy_rx_get_active_rx_ant() ((Xil_In32(WLAN_RX_STATUS) & WLAN_RX_REG_STATUS_ACTIVE_ANT_MASK) >> 2)
105
106#define wlan_phy_rx_get_pkt_det_status() ((Xil_In32(WLAN_RX_STATUS) & WLAN_RX_REG_STATUS_PKT_DET_STATUS_MASK) >> 4)
107
108#define wlan_phy_rx_set_fec_scaling(sc_bpsk, sc_qpsk, sc_16qam, sc_64qam) Xil_Out32(WLAN_RX_FEC_CFG, \
109         ((sc_bpsk) & 0x1F) | \
110        (((sc_qpsk) & 0x1F) << 5) | \
111        (((sc_16qam) & 0x1F) << 10) | \
112        (((sc_64qam) & 0x1F) << 15))
113
114// WLAN_RX_FFT_CFG register fields:
115//     [ 7: 0] - Number of subcarriers (MUST BE 64 - OTHER VALUES UNTESTED)
116//     [15: 8] - Cyclic prefix length (MUST BE 16 - OTHER VALUES UNTESTED)
117//     [23:16] - FFT window offset - number of samples of CP to use on average (must be in [0,CP_LENGTH))
118//     [31:24] - FFT scaling - UFix6_0 value; see Xilinx FFT datasheet for scaling details
119//
120#define wlan_phy_rx_set_fft_window_offset(d)   Xil_Out32(WLAN_RX_FFT_CFG, ((Xil_In32(WLAN_RX_FFT_CFG) & 0xFF00FFFF) | (((d) & 0xFF) << 16)))
121#define wlan_phy_rx_set_fft_scaling(d)         Xil_Out32(WLAN_RX_FFT_CFG, ((Xil_In32(WLAN_RX_FFT_CFG) & 0x00FFFFFF) | (((d) & 0xFF) << 24)))
122#define wlan_phy_rx_config_fft(num_sc, cp_len) Xil_Out32(WLAN_RX_FFT_CFG, ((Xil_In32(WLAN_RX_FFT_CFG) & 0xFFFF0000) | ( (((num_sc) & 0xFF) << 0))) | (((cp_len) & 0xFF) << 8))
123
124#define wlan_phy_tx_config_fft(scaling, num_sc, cp_len) Xil_Out32(WLAN_TX_REG_FFT_CFG, \
125        (((scaling) & 0x3F) << 24) | \
126        (((cp_len) & 0xFF)  <<  8) | \
127        ((num_sc) & 0xFF))
128
129#ifdef WLAN_RX_PKT_RSSI_AB
130// RSSI register files:
131//     WLAN_RX_PKT_RSSI_AB:
132//         [15: 0] - RFA
133//         [31:16] - RFB
134//     WLAN_RX_PKT_RSSI_CD:
135//         [15: 0] - RFC
136//         [31:16] - RFD
137//
138// NOTE: The final << 1 accounts for the fact that this register actually returns the summed RSSI divided by 2
139//
140#define wlan_phy_rx_get_pkt_rssi(ant) ((((ant) == 0) ?  (Xil_In32(WLAN_RX_PKT_RSSI_AB)        & 0xFFFF) : \
141                                        ((ant) == 1) ? ((Xil_In32(WLAN_RX_PKT_RSSI_AB) >> 16) & 0xFFFF) : \
142                                        ((ant) == 2) ?  (Xil_In32(WLAN_RX_PKT_RSSI_CD)        & 0xFFFF) : \
143                                       ((Xil_In32(WLAN_RX_PKT_RSSI_CD) >> 16) & 0xFFFF)) << 1)
144
145// AGC gains register fields:
146//     [ 4: 0] - RF A BBG
147//     [ 6: 5] - RF A RFG
148//         [7] - 0
149//     [12: 8] - RF B BBG
150//     [14:13] - RF B RFG
151//        [15] - 0
152//     [20:16] - RF C BBG
153//     [22:21] - RF C RFG
154//        [23] - 0
155//     [28:24] - RF D BBG
156//     [30:29] - RF D RFG
157//        [31] - 0
158//
159#define wlan_phy_rx_get_agc_RFG(ant) ((((ant) == 0) ? (Xil_In32(WLAN_RX_PKT_AGC_GAINS) >>  5) : \
160                                       ((ant) == 1) ? (Xil_In32(WLAN_RX_PKT_AGC_GAINS) >> 13) : \
161                                       ((ant) == 2) ? (Xil_In32(WLAN_RX_PKT_AGC_GAINS) >> 21) : \
162                                       (Xil_In32(WLAN_RX_PKT_AGC_GAINS) >> 29)) & 0x3)
163
164#define wlan_phy_rx_get_agc_BBG(ant) ((((ant) == 0) ? (Xil_In32(WLAN_RX_PKT_AGC_GAINS) >>  0) : \
165                                       ((ant) == 1) ? (Xil_In32(WLAN_RX_PKT_AGC_GAINS) >>  8) : \
166                                       ((ant) == 2) ? (Xil_In32(WLAN_RX_PKT_AGC_GAINS) >> 16) : \
167                                       (Xil_In32(WLAN_RX_PKT_AGC_GAINS) >> 24)) & 0x1F)
168#else
169int wlan_phy_rx_get_pkt_rssi(u8 ant);
170int wlan_phy_rx_get_agc_BBG(u8 ant);
171
172//#define wlan_phy_rx_get_pkt_rssi(ant) (0)
173//#define wlan_phy_rx_get_agc_BBG(ant)  (0)
174#define wlan_phy_rx_get_agc_RFG(ant)  (0)
175#endif
176
177#define wlan_phy_DSSS_rx_enable()  Xil_Out32(WLAN_RX_REG_CFG, Xil_In32(WLAN_RX_REG_CFG) | WLAN_RX_REG_CFG_DSSS_RX_EN)
178#define wlan_phy_DSSS_rx_disable() Xil_Out32(WLAN_RX_REG_CFG, Xil_In32(WLAN_RX_REG_CFG) & ~WLAN_RX_REG_CFG_DSSS_RX_EN)
179
180// Rx PHY captures time-domain CFO est
181// Fix20_21 value, sign extended to Fix32_31 in this register
182#define wlan_phy_rx_get_cfo_est() Xil_In32(WLAN_RX_CFO_EST_TIME_DOMAIN)
183
184#define wlan_phy_rx_pktDet_RSSI_cfg(sum_len, sum_thresh, min_dur) \
185    Xil_Out32(WLAN_RX_PKTDET_RSSI_CFG, (((sum_len) & 0x1F) | (((sum_thresh) & 0x7FFF) << 5) | (((min_dur) & 0x1F) << 20)))
186
187// WLAN_RX_DSSS_CFG register fields:
188//     [ 7: 0] - UFix8_0 SYNC matching score thresh
189//     [15: 8] - UFix8_0 SYNC matching timeout (samples, multiplied by 32x in hw)
190//     [23:16] - UFix8_0 SFD matching timeout (samples, multiplied by 32x in hw)
191//     [31:24] - UFix8_0 SYNC search time (samples)
192#define wlan_phy_DSSS_rx_config(thresh, sync_timeout, sfd_timeout, search_time) \
193    Xil_Out32(WLAN_RX_DSSS_CFG, (((thresh) & 0xFF) | (((sync_timeout) & 0xFF) << 8) | (((sfd_timeout) & 0xFF) << 16) | (((search_time) & 0xFF) << 24)))
194
195// WLAN_RX_PKT_DET_DSSS_CFG register fields:
196//     [ 7: 0] - Correlation threshold as UFix8_7
197//     [21: 8] - Energy threshold as UFix14_3
198//
199#define wlan_phy_rx_pktDet_autoCorr_dsss_cfg(corr_thresh, energy_thresh) \
200    Xil_Out32(WLAN_RX_PKT_DET_DSSS_CFG, (((corr_thresh) & 0xFF) | (((energy_thresh) & 0x3FFF) << 8)))
201
202// WLAN_RX_PKT_DET_OFDM_CFG register fields:
203//     [ 7: 0] - Correlation threshold as UFix8_8
204//     [21: 8] - Energy threshold as UFix14_3
205//     [25:22] - Minimum duration
206//     [31:26] - Post detection reset block
207//
208#define wlan_phy_rx_pktDet_autoCorr_ofdm_cfg(corr_thresh, energy_thresh, min_dur, post_wait) \
209    Xil_Out32(WLAN_RX_PKT_DET_OFDM_CFG, (((corr_thresh) & 0xFF) | \
210                                         (((energy_thresh) & 0x3FFF) << 8) | \
211                                         (((min_dur) & 0xF) << 22) | \
212                                         (((post_wait) & 0x3F) << 26)))
213
214#define wlan_phy_rx_lts_corr_thresholds(corr_thresh_low_snr, corr_thresh_high_snr) \
215    Xil_Out32(WLAN_RX_LTS_THRESH, ((corr_thresh_low_snr) & 0xFFFF) | (((corr_thresh_high_snr) & 0xFFFF) << 16))
216
217
218#define wlan_phy_rx_lts_corr_peaktype_thresholds(thresh_low_snr, thresh_high_snr) \
219    Xil_Out32(WLAN_RX_LTS_PEAKTYPE_THRESH, ((thresh_low_snr) & 0xFFFF) | (((thresh_high_snr) & 0xFFFF) << 16))
220
221#define wlan_phy_rx_lts_corr_config(snr_thresh, corr_timeout, dly_mask) Xil_Out32(WLAN_RX_LTS_CFG, ((((dly_mask) & 0x7) << 24) | ((corr_timeout) & 0xFF) | (((snr_thresh) & 0xFFFF) << 8)))
222
223#define wlan_phy_rx_chan_est_smoothing(coef_a, coef_b) \
224    Xil_Out32(WLAN_RX_CHAN_EST_SMOOTHING, ((Xil_In32(WLAN_RX_CHAN_EST_SMOOTHING) & 0xFF000000) | \
225            (((coef_b) & 0xFFF) << 12) | ((coef_a) & 0xFFF)))
226
227#define wlan_phy_rx_phy_mode_det_thresh(thresh) \
228        Xil_Out32(WLAN_RX_CHAN_EST_SMOOTHING, ((Xil_In32(WLAN_RX_CHAN_EST_SMOOTHING) & 0xC0FFFFFF) | \
229            (((thresh) & 0x3F) << 24)))
230
231//Tx PHY TIMING register:
232// [ 9: 0] Tx extension (time from last sample to TX_DONE)
233// [19:10] TxEn extension (time from last sample to de-assertion of radio TXEN)
234// [29:20] Rx invalid extension (time from last sample to de-assertion of RX_SIG_INVALID output)
235#define wlan_phy_tx_set_extension(d)            Xil_Out32(WLAN_TX_REG_TIMING, ( (Xil_In32(WLAN_TX_REG_TIMING) & 0xFFFFFC00) | ((d) & 0x3FF)))
236#define wlan_phy_tx_set_txen_extension(d)       Xil_Out32(WLAN_TX_REG_TIMING, ( (Xil_In32(WLAN_TX_REG_TIMING) & 0xFFF003FF) | (((d) & 0x3FF) << 10)))
237#define wlan_phy_tx_set_rx_invalid_extension(d) Xil_Out32(WLAN_TX_REG_TIMING, ( (Xil_In32(WLAN_TX_REG_TIMING) & 0xC00FFFFF) | (((d) & 0x3FF) << 20)))
238
239#define wlan_phy_rx_set_cca_thresh(d) Xil_Out32(WLAN_RX_PHY_CCA_CFG, ((Xil_In32(WLAN_RX_PHY_CCA_CFG) & 0xFFFF0000) | ((d) & 0xFFFF)))
240#define wlan_phy_rx_set_extension(d)  Xil_Out32(WLAN_RX_PHY_CCA_CFG, ((Xil_In32(WLAN_RX_PHY_CCA_CFG) & 0xFF00FFFF) | (((d) << 16) & 0xFF0000)))
241
242//Software-set packet buffer index only used for Tx events triggered via register writes
243// Normal operation uses hardware-triggered Tx via the wlan_mac_hw core
244#define wlan_tx_buffer_sel(n)  Xil_Out32(WLAN_TX_REG_PKT_BUF_SEL, ((Xil_In32(WLAN_TX_REG_PKT_BUF_SEL) & ~0xF) | ((n) & 0xF)) )
245
246//Check if PHY Tx core is active - debug only, use wlan_mac_hw status register to ensure consistent MAC/PHY state
247#define wlan_tx_isrunning() (Xil_In32(WLAN_TX_REG_STATUS) & WLAN_TX_REG_STATUS_TX_RUNNING))
248
249//-----------------------------------------------
250// AGC Macros
251//
252#define wlan_agc_set_AGC_timing(capt_rssi_1, capt_rssi_2, capt_v_db, agc_done) \
253    Xil_Out32(WLAN_AGC_REG_TIMING_AGC, (((capt_rssi_1) & 0xFF) | ( ((capt_rssi_2) & 0xFF) << 8) | \
254                                        (((capt_v_db) & 0xFF) << 16) | ( ((agc_done) & 0xFF) << 24)))
255
256#define wlan_agc_set_DCO_timing(start_dco, en_iir_filt) Xil_Out32(WLAN_AGC_REG_TIMING_DCO, ((start_dco) & 0xFF) | ( ((en_iir_filt) & 0xFF)<<8))
257
258#define wlan_agc_set_target(target_pwr) Xil_Out32(WLAN_AGC_REG_TARGET, ((target_pwr) & 0x3F))
259
260#define wlan_agc_set_config(thresh32, thresh21, avg_len, v_db_adj, init_g_bb) \
261         Xil_Out32(WLAN_AGC_REG_CONFIG, (Xil_In32(WLAN_AGC_REG_CONFIG) & 0xE0000000) | \
262                                    (((thresh32)  & 0xFF) <<  0) | \
263                                    (((thresh21)  & 0xFF) <<  8) | \
264                                    (((avg_len)   & 0x03) << 16) | \
265                                    (((v_db_adj)  & 0x3F) << 18) | \
266                                    (((init_g_bb) & 0x1F) << 24))
267
268#define wlan_agc_set_rxhp_mode(m) Xil_Out32(WLAN_AGC_REG_CONFIG, (Xil_In32(WLAN_AGC_REG_CONFIG) & ~WLAN_AGC_CONFIG_MASK_RXHP_MODE) | ((m) ? WLAN_AGC_CONFIG_MASK_RXHP_MODE : 0))
269
270#define wlan_agc_set_RSSI_pwr_calib(g3, g2, g1) Xil_Out32(WLAN_AGC_REG_RSSI_PWR_CALIB, (((g3) & 0xFF) | (((g2) & 0xFF) << 8) | (((g1) & 0xFF) << 16)))
271
272#define wlan_agc_set_reset_timing(rxhp,g_rf, g_bb) Xil_Out32(WLAN_AGC_TIMING_RESET, (((rxhp) & 0xFF) | (((g_rf) & 0xFF) << 8) | (((g_bb) & 0xFF) << 16)))
273
274
275
276/*************************** Function Prototypes *****************************/
277
278// Initialization commands
279int  w3_node_init();
280void wlan_phy_init();
281void wlan_radio_init();
282
283// Configuration commands
284void wlan_rx_config_ant_mode(u32 ant_mode);
285
286// PHY commands
287void write_phy_preamble(u8 pkt_buf, u8 phy_mode, u8 mcs, u16 length);
288
289// TX debug commands
290void wlan_tx_start();
291
292// Calculate transmit times
293u16 wlan_ofdm_calc_txtime(u16 length, u8 mcs, u8 phy_mode, enum phy_samp_rate_t phy_samp_rate);
294u16 wlan_ofdm_calc_num_payload_syms(u16 length, u8 mcs, u8 phy_mode);
295
296#endif /* W3_PHY_UTIL_H_ */
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