1 | <?xml version="1.0" encoding="UTF-8"?> |
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2 | <Project NoOfControllers="1" > |
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3 | <ModuleName>DDR3_SODIMM</ModuleName> |
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4 | <dci_inouts_inputs>1</dci_inouts_inputs> |
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5 | <dci_outputs>0</dci_outputs> |
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6 | <Debug_En>OFF</Debug_En> |
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7 | <TargetFPGA>xc6vlx240t-ff1156/-2</TargetFPGA> |
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8 | <Version>3.92</Version> |
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9 | <SystemClock>Differential</SystemClock> |
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10 | <PinSelectionFlag>TRUE</PinSelectionFlag> |
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11 | <IODelayHighPerformanceMode>HIGH</IODelayHighPerformanceMode> |
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12 | <InternalVref>1</InternalVref> |
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13 | <IdelayGroupName>IODELAY_MIG</IdelayGroupName> |
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14 | <Controller number="0" > |
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15 | <MemoryDevice>DDR3_SDRAM/SODIMMs/MT8JSF25664HZ-1G4</MemoryDevice> |
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16 | <TimePeriod>3125</TimePeriod> |
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17 | <DataWidth>64</DataWidth> |
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18 | <DeepMemory>1</DeepMemory> |
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19 | <DataMask>1</DataMask> |
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20 | <CustomPart>FALSE</CustomPart> |
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21 | <NewPartName></NewPartName> |
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22 | <RowAddress>15</RowAddress> |
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23 | <ColAddress>10</ColAddress> |
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24 | <BankAddress>3</BankAddress> |
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25 | <MasterBanks>23</MasterBanks> |
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26 | <TimingParameters> |
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27 | <Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="30" trtp="7.5" trfc="160" trp="13.125" tras="36" trcd="13.125" /> |
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28 | </TimingParameters> |
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29 | <ECC>Disabled</ECC> |
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30 | <DiscreteBankSelections>1</DiscreteBankSelections> |
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31 | <CaptureClock>32</CaptureClock> |
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32 | <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap> |
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33 | <Ordering>Normal</Ordering> |
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34 | <PinSelection> |
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35 | <Pin SignalName="BUFIO:0" PINNumber="AH23" SignalGroup="Data" Bank="23" /> |
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36 | <Pin SignalName="BUFIO:1" PINNumber="AK27" SignalGroup="Data" Bank="23" /> |
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37 | <Pin SignalName="BUFIO:2" PINNumber="AN27" SignalGroup="Data" Bank="23" /> |
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38 | <Pin SignalName="BUFIO:3" PINNumber="AF19" SignalGroup="Data" Bank="22" /> |
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39 | <Pin SignalName="BUFIO:4" PINNumber="AF20" SignalGroup="Data" Bank="22" /> |
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40 | <Pin SignalName="BUFIO:5" PINNumber="AC13" SignalGroup="Data" Bank="33" /> |
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41 | <Pin SignalName="BUFIO:6" PINNumber="AD12" SignalGroup="Data" Bank="33" /> |
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42 | <Pin SignalName="BUFIO:7" PINNumber="AP11" SignalGroup="Data" Bank="33" /> |
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43 | <Pin SignalName="BUFR:0" PINNumber="AP20" SignalGroup="Data" Bank="22" /> |
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44 | <Pin SignalName="BUFR:1" PINNumber="AH17" SignalGroup="Data" Bank="32" /> |
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45 | <Pin SignalName="ddr3_addr[0]" PINNumber="AM17" SignalGroup="Address" Bank="32" /> |
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46 | <Pin SignalName="ddr3_addr[10]" PINNumber="AH15" SignalGroup="Address" Bank="32" /> |
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47 | <Pin SignalName="ddr3_addr[11]" PINNumber="AH18" SignalGroup="Address" Bank="32" /> |
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48 | <Pin SignalName="ddr3_addr[12]" PINNumber="AE17" SignalGroup="Address" Bank="32" /> |
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49 | <Pin SignalName="ddr3_addr[13]" PINNumber="AJ16" SignalGroup="Address" Bank="32" /> |
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50 | <Pin SignalName="ddr3_addr[14]" PINNumber="AK18" SignalGroup="Address" Bank="32" /> |
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51 | <Pin SignalName="ddr3_addr[1]" PINNumber="AF16" SignalGroup="Address" Bank="32" /> |
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52 | <Pin SignalName="ddr3_addr[2]" PINNumber="AN17" SignalGroup="Address" Bank="32" /> |
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53 | <Pin SignalName="ddr3_addr[3]" PINNumber="AG17" SignalGroup="Address" Bank="32" /> |
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54 | <Pin SignalName="ddr3_addr[4]" PINNumber="AK16" SignalGroup="Address" Bank="32" /> |
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55 | <Pin SignalName="ddr3_addr[5]" PINNumber="AG16" SignalGroup="Address" Bank="32" /> |
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56 | <Pin SignalName="ddr3_addr[6]" PINNumber="AK17" SignalGroup="Address" Bank="32" /> |
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57 | <Pin SignalName="ddr3_addr[7]" PINNumber="AG18" SignalGroup="Address" Bank="32" /> |
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58 | <Pin SignalName="ddr3_addr[8]" PINNumber="AE16" SignalGroup="Address" Bank="32" /> |
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59 | <Pin SignalName="ddr3_addr[9]" PINNumber="AD16" SignalGroup="Address" Bank="32" /> |
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60 | <Pin SignalName="ddr3_ba[0]" PINNumber="AG15" SignalGroup="Address" Bank="32" /> |
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61 | <Pin SignalName="ddr3_ba[1]" PINNumber="AP16" SignalGroup="Address" Bank="32" /> |
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62 | <Pin SignalName="ddr3_ba[2]" PINNumber="AD17" SignalGroup="Address" Bank="32" /> |
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63 | <Pin SignalName="ddr3_cas#" PINNumber="AJ17" SignalGroup="Address" Bank="32" /> |
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64 | <Pin SignalName="ddr3_ck#[0]" PINNumber="AD15" SignalGroup="Address" Bank="32" /> |
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65 | <Pin SignalName="ddr3_ck#[1]" PINNumber="AM15" SignalGroup="Address" Bank="32" /> |
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66 | <Pin SignalName="ddr3_ck_p[0]" PINNumber="AC15" SignalGroup="Address" Bank="32" /> |
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67 | <Pin SignalName="ddr3_ck_p[1]" PINNumber="AN15" SignalGroup="Address" Bank="32" /> |
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68 | <Pin SignalName="ddr3_cke[0]" PINNumber="AF18" SignalGroup="Address" Bank="32" /> |
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69 | <Pin SignalName="ddr3_cs#[0]" PINNumber="AL16" SignalGroup="Address" Bank="32" /> |
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70 | <Pin SignalName="ddr3_dm[0]" PINNumber="AM30" SignalGroup="Data" Bank="23" /> |
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71 | <Pin SignalName="ddr3_dm[1]" PINNumber="AL26" SignalGroup="Data" Bank="23" /> |
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72 | <Pin SignalName="ddr3_dm[2]" PINNumber="AP26" SignalGroup="Data" Bank="23" /> |
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73 | <Pin SignalName="ddr3_dm[3]" PINNumber="AJ22" SignalGroup="Data" Bank="22" /> |
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74 | <Pin SignalName="ddr3_dm[4]" PINNumber="AN20" SignalGroup="Data" Bank="22" /> |
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75 | <Pin SignalName="ddr3_dm[5]" PINNumber="AH14" SignalGroup="Data" Bank="33" /> |
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76 | <Pin SignalName="ddr3_dm[6]" PINNumber="AM10" SignalGroup="Data" Bank="33" /> |
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77 | <Pin SignalName="ddr3_dm[7]" PINNumber="AG11" SignalGroup="Data" Bank="33" /> |
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78 | <Pin SignalName="ddr3_dq[0]" PINNumber="AK29" SignalGroup="Data" Bank="23" /> |
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79 | <Pin SignalName="ddr3_dq[10]" PINNumber="AJ27" SignalGroup="Data" Bank="23" /> |
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80 | <Pin SignalName="ddr3_dq[11]" PINNumber="AH25" SignalGroup="Data" Bank="23" /> |
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81 | <Pin SignalName="ddr3_dq[12]" PINNumber="AP29" SignalGroup="Data" Bank="23" /> |
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82 | <Pin SignalName="ddr3_dq[13]" PINNumber="AM27" SignalGroup="Data" Bank="23" /> |
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83 | <Pin SignalName="ddr3_dq[14]" PINNumber="AJ25" SignalGroup="Data" Bank="23" /> |
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84 | <Pin SignalName="ddr3_dq[15]" PINNumber="AH24" SignalGroup="Data" Bank="23" /> |
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85 | <Pin SignalName="ddr3_dq[16]" PINNumber="AJ24" SignalGroup="Data" Bank="23" /> |
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86 | <Pin SignalName="ddr3_dq[17]" PINNumber="AK24" SignalGroup="Data" Bank="23" /> |
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87 | <Pin SignalName="ddr3_dq[18]" PINNumber="AL24" SignalGroup="Data" Bank="23" /> |
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88 | <Pin SignalName="ddr3_dq[19]" PINNumber="AK23" SignalGroup="Data" Bank="23" /> |
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89 | <Pin SignalName="ddr3_dq[1]" PINNumber="AN30" SignalGroup="Data" Bank="23" /> |
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90 | <Pin SignalName="ddr3_dq[20]" PINNumber="AP27" SignalGroup="Data" Bank="23" /> |
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91 | <Pin SignalName="ddr3_dq[21]" PINNumber="AM26" SignalGroup="Data" Bank="23" /> |
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92 | <Pin SignalName="ddr3_dq[22]" PINNumber="AN25" SignalGroup="Data" Bank="23" /> |
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93 | <Pin SignalName="ddr3_dq[23]" PINNumber="AN24" SignalGroup="Data" Bank="23" /> |
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94 | <Pin SignalName="ddr3_dq[24]" PINNumber="AD21" SignalGroup="Data" Bank="22" /> |
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95 | <Pin SignalName="ddr3_dq[25]" PINNumber="AE21" SignalGroup="Data" Bank="22" /> |
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96 | <Pin SignalName="ddr3_dq[26]" PINNumber="AK22" SignalGroup="Data" Bank="22" /> |
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97 | <Pin SignalName="ddr3_dq[27]" PINNumber="AL18" SignalGroup="Data" Bank="22" /> |
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98 | <Pin SignalName="ddr3_dq[28]" PINNumber="AN19" SignalGroup="Data" Bank="22" /> |
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99 | <Pin SignalName="ddr3_dq[29]" PINNumber="AP19" SignalGroup="Data" Bank="22" /> |
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100 | <Pin SignalName="ddr3_dq[2]" PINNumber="AL29" SignalGroup="Data" Bank="23" /> |
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101 | <Pin SignalName="ddr3_dq[30]" PINNumber="AM18" SignalGroup="Data" Bank="22" /> |
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102 | <Pin SignalName="ddr3_dq[31]" PINNumber="AN18" SignalGroup="Data" Bank="22" /> |
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103 | <Pin SignalName="ddr3_dq[32]" PINNumber="AF21" SignalGroup="Data" Bank="22" /> |
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104 | <Pin SignalName="ddr3_dq[33]" PINNumber="AC20" SignalGroup="Data" Bank="22" /> |
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105 | <Pin SignalName="ddr3_dq[34]" PINNumber="AD20" SignalGroup="Data" Bank="22" /> |
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106 | <Pin SignalName="ddr3_dq[35]" PINNumber="AE19" SignalGroup="Data" Bank="22" /> |
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107 | <Pin SignalName="ddr3_dq[36]" PINNumber="AP21" SignalGroup="Data" Bank="22" /> |
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108 | <Pin SignalName="ddr3_dq[37]" PINNumber="AJ20" SignalGroup="Data" Bank="22" /> |
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109 | <Pin SignalName="ddr3_dq[38]" PINNumber="AL19" SignalGroup="Data" Bank="22" /> |
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110 | <Pin SignalName="ddr3_dq[39]" PINNumber="AK19" SignalGroup="Data" Bank="22" /> |
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111 | <Pin SignalName="ddr3_dq[3]" PINNumber="AN29" SignalGroup="Data" Bank="23" /> |
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112 | <Pin SignalName="ddr3_dq[40]" PINNumber="AF14" SignalGroup="Data" Bank="33" /> |
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113 | <Pin SignalName="ddr3_dq[41]" PINNumber="AG12" SignalGroup="Data" Bank="33" /> |
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114 | <Pin SignalName="ddr3_dq[42]" PINNumber="AK13" SignalGroup="Data" Bank="33" /> |
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115 | <Pin SignalName="ddr3_dq[43]" PINNumber="AH12" SignalGroup="Data" Bank="33" /> |
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116 | <Pin SignalName="ddr3_dq[44]" PINNumber="AN14" SignalGroup="Data" Bank="33" /> |
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117 | <Pin SignalName="ddr3_dq[45]" PINNumber="AP14" SignalGroup="Data" Bank="33" /> |
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118 | <Pin SignalName="ddr3_dq[46]" PINNumber="AL13" SignalGroup="Data" Bank="33" /> |
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119 | <Pin SignalName="ddr3_dq[47]" PINNumber="AN12" SignalGroup="Data" Bank="33" /> |
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120 | <Pin SignalName="ddr3_dq[48]" PINNumber="AF11" SignalGroup="Data" Bank="33" /> |
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121 | <Pin SignalName="ddr3_dq[49]" PINNumber="AE11" SignalGroup="Data" Bank="33" /> |
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122 | <Pin SignalName="ddr3_dq[4]" PINNumber="AP31" SignalGroup="Data" Bank="23" /> |
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123 | <Pin SignalName="ddr3_dq[50]" PINNumber="AE13" SignalGroup="Data" Bank="33" /> |
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124 | <Pin SignalName="ddr3_dq[51]" PINNumber="AE12" SignalGroup="Data" Bank="33" /> |
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125 | <Pin SignalName="ddr3_dq[52]" PINNumber="AK12" SignalGroup="Data" Bank="33" /> |
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126 | <Pin SignalName="ddr3_dq[53]" PINNumber="AJ12" SignalGroup="Data" Bank="33" /> |
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127 | <Pin SignalName="ddr3_dq[54]" PINNumber="AK11" SignalGroup="Data" Bank="33" /> |
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128 | <Pin SignalName="ddr3_dq[55]" PINNumber="AJ11" SignalGroup="Data" Bank="33" /> |
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129 | <Pin SignalName="ddr3_dq[56]" PINNumber="AC12" SignalGroup="Data" Bank="33" /> |
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130 | <Pin SignalName="ddr3_dq[57]" PINNumber="AH10" SignalGroup="Data" Bank="33" /> |
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131 | <Pin SignalName="ddr3_dq[58]" PINNumber="AD11" SignalGroup="Data" Bank="33" /> |
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132 | <Pin SignalName="ddr3_dq[59]" PINNumber="AG10" SignalGroup="Data" Bank="33" /> |
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133 | <Pin SignalName="ddr3_dq[5]" PINNumber="AP30" SignalGroup="Data" Bank="23" /> |
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134 | <Pin SignalName="ddr3_dq[60]" PINNumber="AP12" SignalGroup="Data" Bank="33" /> |
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135 | <Pin SignalName="ddr3_dq[61]" PINNumber="AM12" SignalGroup="Data" Bank="33" /> |
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136 | <Pin SignalName="ddr3_dq[62]" PINNumber="AL10" SignalGroup="Data" Bank="33" /> |
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137 | <Pin SignalName="ddr3_dq[63]" PINNumber="AJ10" SignalGroup="Data" Bank="33" /> |
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138 | <Pin SignalName="ddr3_dq[6]" PINNumber="AH28" SignalGroup="Data" Bank="23" /> |
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139 | <Pin SignalName="ddr3_dq[7]" PINNumber="AH27" SignalGroup="Data" Bank="23" /> |
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140 | <Pin SignalName="ddr3_dq[8]" PINNumber="AK28" SignalGroup="Data" Bank="23" /> |
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141 | <Pin SignalName="ddr3_dq[9]" PINNumber="AL28" SignalGroup="Data" Bank="23" /> |
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142 | <Pin SignalName="ddr3_dqs#[0]" PINNumber="AG26" SignalGroup="Data" Bank="23" /> |
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143 | <Pin SignalName="ddr3_dqs#[1]" PINNumber="AM28" SignalGroup="Data" Bank="23" /> |
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144 | <Pin SignalName="ddr3_dqs#[2]" PINNumber="AL25" SignalGroup="Data" Bank="23" /> |
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145 | <Pin SignalName="ddr3_dqs#[3]" PINNumber="AH22" SignalGroup="Data" Bank="22" /> |
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146 | <Pin SignalName="ddr3_dqs#[4]" PINNumber="AL20" SignalGroup="Data" Bank="22" /> |
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147 | <Pin SignalName="ddr3_dqs#[5]" PINNumber="AM13" SignalGroup="Data" Bank="33" /> |
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148 | <Pin SignalName="ddr3_dqs#[6]" PINNumber="AC14" SignalGroup="Data" Bank="33" /> |
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149 | <Pin SignalName="ddr3_dqs#[7]" PINNumber="AM11" SignalGroup="Data" Bank="33" /> |
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150 | <Pin SignalName="ddr3_dqs_p[0]" PINNumber="AG25" SignalGroup="Data" Bank="23" /> |
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151 | <Pin SignalName="ddr3_dqs_p[1]" PINNumber="AN28" SignalGroup="Data" Bank="23" /> |
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152 | <Pin SignalName="ddr3_dqs_p[2]" PINNumber="AM25" SignalGroup="Data" Bank="23" /> |
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153 | <Pin SignalName="ddr3_dqs_p[3]" PINNumber="AG22" SignalGroup="Data" Bank="22" /> |
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154 | <Pin SignalName="ddr3_dqs_p[4]" PINNumber="AM20" SignalGroup="Data" Bank="22" /> |
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155 | <Pin SignalName="ddr3_dqs_p[5]" PINNumber="AN13" SignalGroup="Data" Bank="33" /> |
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156 | <Pin SignalName="ddr3_dqs_p[6]" PINNumber="AD14" SignalGroup="Data" Bank="33" /> |
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157 | <Pin SignalName="ddr3_dqs_p[7]" PINNumber="AL11" SignalGroup="Data" Bank="33" /> |
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158 | <Pin SignalName="ddr3_odt[0]" PINNumber="AP15" SignalGroup="Address" Bank="32" /> |
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159 | <Pin SignalName="ddr3_ras#" PINNumber="AM16" SignalGroup="Address" Bank="32" /> |
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160 | <Pin SignalName="ddr3_reset#" PINNumber="AP17" SignalGroup="Address" Bank="32" /> |
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161 | <Pin SignalName="ddr3_we#" PINNumber="AF15" SignalGroup="Address" Bank="32" /> |
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162 | </PinSelection> |
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163 | <BankSelection> |
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164 | <Bank SysClk="0" Data="1" name="22" Address="0" wasso="40" /> |
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165 | <Bank SysClk="0" Data="1" name="23" Address="0" wasso="40" /> |
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166 | <Bank SysClk="0" Data="0" name="32" Address="1" wasso="40" /> |
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167 | <Bank SysClk="0" Data="1" name="33" Address="0" wasso="40" /> |
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168 | </BankSelection> |
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169 | <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength> |
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170 | <mrBurstType name="Read Burst Type" >Sequential</mrBurstType> |
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171 | <mrCasLatency name="CAS Latency" >5</mrCasLatency> |
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172 | <mrMode name="Mode" >Normal</mrMode> |
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173 | <mrDllReset name="DLL Reset" >No</mrDllReset> |
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174 | <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode> |
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175 | <emrDllEnable name="DLL Enable" >Enable</emrDllEnable> |
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176 | <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength> |
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177 | <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT> |
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178 | <emrPosted name="Additive Latency (AL)" >0</emrPosted> |
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179 | <emrOCD name="Write Leveling Enable" >Disabled</emrOCD> |
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180 | <emrDQS name="TDQS enable" >Enabled</emrDQS> |
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181 | <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS> |
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182 | <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh> |
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183 | <mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency> |
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184 | <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh> |
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185 | <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange> |
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186 | <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR> |
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187 | <PortInterface>AXI</PortInterface> |
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188 | <AXIParameters> |
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189 | <C_INTERCONNECT_S_AXI_AR_REGISTER>BYPASS</C_INTERCONNECT_S_AXI_AR_REGISTER> |
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190 | <C_INTERCONNECT_S_AXI_AW_REGISTER>BYPASS</C_INTERCONNECT_S_AXI_AW_REGISTER> |
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191 | <C_INTERCONNECT_S_AXI_B_REGISTER>BYPASS</C_INTERCONNECT_S_AXI_B_REGISTER> |
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192 | <C_INTERCONNECT_S_AXI_READ_ACCEPTANCE>4</C_INTERCONNECT_S_AXI_READ_ACCEPTANCE> |
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193 | <C_INTERCONNECT_S_AXI_READ_FIFO_DEPTH>0</C_INTERCONNECT_S_AXI_READ_FIFO_DEPTH> |
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194 | <C_INTERCONNECT_S_AXI_R_REGISTER>BYPASS</C_INTERCONNECT_S_AXI_R_REGISTER> |
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195 | <C_INTERCONNECT_S_AXI_SECURE>0</C_INTERCONNECT_S_AXI_SECURE> |
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196 | <C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE>4</C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE> |
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197 | <C_INTERCONNECT_S_AXI_WRITE_FIFO_DEPTH>0</C_INTERCONNECT_S_AXI_WRITE_FIFO_DEPTH> |
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198 | <C_INTERCONNECT_S_AXI_W_REGISTER>BYPASS</C_INTERCONNECT_S_AXI_W_REGISTER> |
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199 | <C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C_RD_WR_ARB_ALGORITHM> |
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200 | <C_S_AXI_ADDR_WIDTH>32</C_S_AXI_ADDR_WIDTH> |
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201 | <C_S_AXI_BASEADDR>0xc0000000</C_S_AXI_BASEADDR> |
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202 | <C_S_AXI_DATA_WIDTH>64</C_S_AXI_DATA_WIDTH> |
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203 | <C_S_AXI_HIGHADDR>0xffffffff</C_S_AXI_HIGHADDR> |
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204 | <C_S_AXI_SUPPORTS_NARROW_BURST>Auto</C_S_AXI_SUPPORTS_NARROW_BURST> |
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205 | </AXIParameters> |
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206 | </Controller> |
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207 | </Project> |
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