1 | ### NOTE: DDR3 SO-DIMM contraints are not specified here!
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2 | ### These are pulled automatically from the MIG project during implementation
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3 | NET ddr_parity LOC = "H29" | IOSTANDARD = "LVCMOS25" | TIG; #stray PAD MIG insists on including, mapped to NC pin on FPGA
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4 |
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5 | NET "dbg_hdr<0>" LOC = "AG27" | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 0
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6 | NET "dbg_hdr<1>" LOC = "AE26" | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 1
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7 | NET "dbg_hdr<2>" LOC = "AF26" | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 2 |
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8 | NET "dbg_hdr<3>" LOC = "AD25" | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 3 |
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9 |
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10 | NET "dbg_hdr<4>" LOC = "V24" | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 4 |
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11 | NET "dbg_hdr<5>" LOC = "AA23" | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 5 |
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12 | NET "dbg_hdr<6>" LOC = "AH30" | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 6 |
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13 | NET "dbg_hdr<7>" LOC = "AK31" | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 7
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14 |
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15 | NET "dbg_hdr<8>" LOC = "AG28" | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 8
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16 | NET "dbg_hdr<9>" LOC = "AE27" | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 9
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17 | NET "dbg_hdr<10>" LOC = "AF28" | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 10
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18 | NET "dbg_hdr<11>" LOC = "AJ29" | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 11
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19 |
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20 | NET "dbg_hdr<12>" LOC = "AH29" | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 12
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21 | NET "dbg_hdr<13>" LOC = "AL30" | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 13
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22 | NET "dbg_hdr<14>" LOC = "AM31" | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 14
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23 | NET "dbg_hdr<15>" LOC = "AP32" | IOSTANDARD = "LVCMOS25" | PULLDOWN; #pin 15
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24 |
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25 | #System clock (80MHz, from sampling clock buffer)
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26 | NET samp_clk_n LOC = V23 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
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27 | NET samp_clk_p LOC = U23 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
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28 | Net samp_clk_p TNM_NET = samp_clk;
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29 | TIMESPEC TS_samp_clk = PERIOD samp_clk 80000 kHz;
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30 |
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31 | Net clk_160MHz TNM_NET = TNM_clk_160MHz;
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32 |
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33 | #System clock (200MHz, from LVDS oscillator)
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34 | Net osc200_p LOC = A10 | IOSTANDARD=LVDS_25 | DIFF_TERM = TRUE;
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35 | Net osc200_n LOC = B10 | IOSTANDARD=LVDS_25 | DIFF_TERM = TRUE;
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36 | Net osc200_p TNM_NET = osc200_p;
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37 | TIMESPEC TS_osc200_p = PERIOD osc200_p 200000 kHz;
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38 |
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39 | #FPGA CC pins connected to clock module header
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40 | # CM-PLL drives these with copy of selected PLL reference clock
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41 | # Constrained to 200MHz (overkill, but easy to meet given the simple logic)
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42 | Net pll_refclk_p LOC = AD24 | IOSTANDARD=LVDS_25 | DIFF_TERM = TRUE;
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43 | Net pll_refclk_n LOC = AE24 | IOSTANDARD=LVDS_25 | DIFF_TERM = TRUE;
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44 | Net pll_refclk_p TNM_NET = pll_refclk;
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45 | TIMESPEC TS_pll_refclk = PERIOD pll_refclk 200000 kHz;
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46 |
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47 | NET userio_dipsw<0> LOC = "AM22" | IOSTANDARD = "LVCMOS15";
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48 | NET userio_dipsw<1> LOC = "AL23" | IOSTANDARD = "LVCMOS15";
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49 | NET userio_dipsw<2> LOC = "AM23" | IOSTANDARD = "LVCMOS15";
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50 | NET userio_dipsw<3> LOC = "AN23" | IOSTANDARD = "LVCMOS15";
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51 |
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52 | Net userio_leds_red<0> LOC=AN34 | IOSTANDARD = LVCMOS25; |
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53 | Net userio_leds_red<1> LOC=AM33 | IOSTANDARD = LVCMOS25; |
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54 | Net userio_leds_red<2> LOC=AN33 | IOSTANDARD = LVCMOS25; |
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55 | Net userio_leds_red<3> LOC=AP33 | IOSTANDARD = LVCMOS25; |
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56 |
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57 | Net userio_leds_green<0> LOC=AD22 | IOSTANDARD = LVCMOS25; |
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58 | Net userio_leds_green<1> LOC=AE22 | IOSTANDARD = LVCMOS25; |
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59 | Net userio_leds_green<2> LOC=AM32 | IOSTANDARD = LVCMOS25; |
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60 | Net userio_leds_green<3> LOC=AN32 | IOSTANDARD = LVCMOS25; |
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61 | |
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62 | Net userio_pb_u LOC=AM21 | IOSTANDARD = LVCMOS15; |
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63 | Net userio_pb_m LOC=AN22 | IOSTANDARD = LVCMOS15; |
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64 | Net userio_pb_d LOC=AP22 | IOSTANDARD = LVCMOS15; |
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65 |
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66 | Net userio_hexdisp_left<0> LOC=AL33 | IOSTANDARD = LVCMOS25; |
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67 | Net userio_hexdisp_left<1> LOC=AK33 | IOSTANDARD = LVCMOS25; |
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68 | Net userio_hexdisp_left<2> LOC=AH32 | IOSTANDARD = LVCMOS25; |
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69 | Net userio_hexdisp_left<3> LOC=AF29 | IOSTANDARD = LVCMOS25; |
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70 | Net userio_hexdisp_left<4> LOC=AE29 | IOSTANDARD = LVCMOS25; |
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71 | Net userio_hexdisp_left<5> LOC=AK32 | IOSTANDARD = LVCMOS25; |
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72 | Net userio_hexdisp_left<6> LOC=AF30 | IOSTANDARD = LVCMOS25; |
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73 |
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74 | Net userio_hexdisp_right<0> LOC=AE28 | IOSTANDARD = LVCMOS25; |
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75 | Net userio_hexdisp_right<1> LOC=AD26 | IOSTANDARD = LVCMOS25; |
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76 | Net userio_hexdisp_right<2> LOC=AC24 | IOSTANDARD = LVCMOS25; |
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77 | Net userio_hexdisp_right<3> LOC=AE23 | IOSTANDARD = LVCMOS25; |
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78 | Net userio_hexdisp_right<4> LOC=AC22 | IOSTANDARD = LVCMOS25; |
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79 | Net userio_hexdisp_right<5> LOC=AD27 | IOSTANDARD = LVCMOS25; |
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80 | Net userio_hexdisp_right<6> LOC=AB23 | IOSTANDARD = LVCMOS25; |
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81 |
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82 | Net userio_hexdisp_left_dp LOC=AG30 | IOSTANDARD = LVCMOS25; |
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83 | Net userio_hexdisp_right_dp LOC=AC23 | IOSTANDARD = LVCMOS25; |
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84 |
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85 | Net userio_rfa_led_red LOC=AL34 | IOSTANDARD = LVCMOS25; |
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86 | Net userio_rfa_led_green LOC=AK34 | IOSTANDARD = LVCMOS25; |
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87 | Net userio_rfb_led_red LOC=AJ34 | IOSTANDARD = LVCMOS25; |
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88 | Net userio_rfb_led_green LOC=AH34 | IOSTANDARD = LVCMOS25;
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89 |
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90 | NET usb_uart_rx LOC = "J9" | IOSTANDARD = "LVCMOS25";
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91 | NET usb_uart_tx LOC = "H9" | IOSTANDARD = "LVCMOS25";
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92 |
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93 | #SIP switch on CM-MMCX / DIP switch on the CM-PLL
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94 | NET "cm_switch<0>" LOC = V30 | IOSTANDARD = LVCMOS25 | PULLUP; #CLKHDR_CTRL12 in schematics
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95 | NET "cm_switch<1>" LOC = R34 | IOSTANDARD = LVCMOS25 | PULLUP; #CLKHDR_CTRL13 in schematics
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96 | NET "cm_switch<2>" LOC = W26 | IOSTANDARD = LVCMOS25 | PULLUP; #CLKHDR_CTRL13 in schematics
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97 |
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98 | NET cm_spi_sclk LOC = "Y34" | IOSTANDARD = LVCMOS25; #CM hdr p25 CTRL8
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99 | NET cm_spi_mosi LOC = "Y31" | IOSTANDARD = LVCMOS25; #CM hdr p29 CTRL10
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100 | NET cm_spi_miso LOC = "Y33" | IOSTANDARD = LVCMOS25; #CM hdr p27 CTRL9
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101 | NET cm_spi_cs_n LOC = "Y32" | IOSTANDARD = LVCMOS25; #CM hdr p31 CTRL11
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102 | NET cm_pll_status LOC = "V29" | IOSTANDARD = LVCMOS25 | PULLUP; #CM hdr p14 CTRL15
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103 |
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104 | NET clk_rfref_spi_sclk LOC = V25 | IOSTANDARD = LVCMOS25;#
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105 | NET clk_rfref_spi_mosi LOC = W25 | IOSTANDARD = LVCMOS25;#
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106 | NET clk_rfref_spi_cs_n LOC = W27 | IOSTANDARD = LVCMOS25;#
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107 | NET clk_rfref_spi_miso LOC = Y27 | IOSTANDARD = LVCMOS25;#
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108 | NET clk_rfref_func LOC = L26 | IOSTANDARD = LVCMOS25;
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109 |
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110 | NET clk_samp_spi_sclk LOC = W32 | IOSTANDARD = LVCMOS25;#
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111 | NET clk_samp_spi_mosi LOC = Y29 | IOSTANDARD = LVCMOS25;#
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112 | NET clk_samp_spi_cs_n LOC = W31 | IOSTANDARD = LVCMOS25;#
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113 | NET clk_samp_spi_miso LOC = Y28 | IOSTANDARD = LVCMOS25;#
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114 | NET clk_samp_func LOC = R33 | IOSTANDARD = LVCMOS25;#
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115 |
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116 | #IIC EEPROM on-board
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117 | Net iic_eeprom_onboard_sda LOC = AG23 | IOSTANDARD=LVCMOS25;
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118 | Net iic_eeprom_onboard_scl LOC = AF23 | IOSTANDARD=LVCMOS25;
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119 |
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120 | #ETH_A pins (88e1121R P1)
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121 | Net ETH_A_PHY_RST_N LOC=L9 | IOSTANDARD = "LVCMOS25" | TIG;
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122 | Net ETH_A_RGMII_TXD<0> LOC=AF9 | IOSTANDARD = "LVCMOS25";
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123 | Net ETH_A_RGMII_TXD<1> LOC=AF10 | IOSTANDARD = "LVCMOS25";
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124 | Net ETH_A_RGMII_TXD<2> LOC=AD9 | IOSTANDARD = "LVCMOS25";
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125 | Net ETH_A_RGMII_TXD<3> LOC=AD10 | IOSTANDARD = "LVCMOS25";
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126 | Net ETH_A_RGMII_TX_CTL LOC=AG8 | IOSTANDARD = "LVCMOS25";
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127 | Net ETH_A_RGMII_TXC LOC=AE9 | IOSTANDARD = "LVCMOS25";
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128 | Net ETH_A_RGMII_RXD<0> LOC=AK9 | IOSTANDARD = "LVCMOS25";
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129 | Net ETH_A_RGMII_RXD<1> LOC=AJ9 | IOSTANDARD = "LVCMOS25";
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130 | Net ETH_A_RGMII_RXD<2> LOC=AH8 | IOSTANDARD = "LVCMOS25";
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131 | Net ETH_A_RGMII_RXD<3> LOC=AH9 | IOSTANDARD = "LVCMOS25";
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132 | Net ETH_A_RGMII_RX_CTL LOC=AL9 | IOSTANDARD = "LVCMOS25";
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133 | Net ETH_A_RGMII_RXC LOC=AC10 | IOSTANDARD = "LVCMOS25";
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134 | Net ETH_A_MDIO LOC=AP9 | IOSTANDARD = "LVCMOS25" | PULLUP;
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135 | Net ETH_A_MDC LOC=AK8 | IOSTANDARD = "LVCMOS25";
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136 | NET ETH_A_PD LOC = K9 | IOSTANDARD = "LVCMOS25" | TIG;
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137 |
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138 | #ETH B
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139 | Net ETH_B_RGMII_TXD<0> LOC=M10 | IOSTANDARD = LVCMOS25;
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140 | Net ETH_B_RGMII_TXD<1> LOC=B8 | IOSTANDARD = LVCMOS25;
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141 | Net ETH_B_RGMII_TXD<2> LOC=AC9 | IOSTANDARD = LVCMOS25;
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142 | Net ETH_B_RGMII_TXD<3> LOC=E9 | IOSTANDARD = LVCMOS25;
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143 | Net ETH_B_RGMII_TX_CTL LOC=D10 | IOSTANDARD = LVCMOS25;
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144 | Net ETH_B_RGMII_TXC LOC=AB10 | IOSTANDARD = LVCMOS25;
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145 | Net ETH_B_RGMII_RXD<0> LOC=A9 | IOSTANDARD = LVCMOS25;
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146 | Net ETH_B_RGMII_RXD<1> LOC=D9 | IOSTANDARD = LVCMOS25;
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147 | Net ETH_B_RGMII_RXD<2> LOC=C9 | IOSTANDARD = LVCMOS25;
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148 | Net ETH_B_RGMII_RXD<3> LOC=F10 | IOSTANDARD = LVCMOS25;
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149 | Net ETH_B_RGMII_RX_CTL LOC=A8 | IOSTANDARD = LVCMOS25;
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150 | Net ETH_B_RGMII_RXC LOC=L10 | IOSTANDARD = LVCMOS25;
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151 | Net ETH_B_MDC LOC=AN9 | IOSTANDARD = LVCMOS25;
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152 | Net ETH_B_MDIO LOC=AL8 | IOSTANDARD = LVCMOS25 | PULLUP;
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153 | NET ETH_B_PD LOC = E8 | IOSTANDARD = "LVCMOS25" | TIG;
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154 |
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155 | NET ETH_COMA LOC = C8 | IOSTANDARD = "LVCMOS25" | TIG;
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156 |
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157 | NET reset_pb LOC = "AH13" | IOSTANDARD = "LVCMOS15" | TIG;
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158 |
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159 | #NET "*fpga_dna*" TIG;
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160 |
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161 | ###############
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162 | # ETH_A Timing
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163 | INST "*ETH_A*gmii_interface*rxdata_bus[0].delay_rgmii_rxd" IDELAY_VALUE = 13;
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164 | INST "*ETH_A*gmii_interface*rxdata_bus[1].delay_rgmii_rxd" IDELAY_VALUE = 13;
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165 | INST "*ETH_A*gmii_interface*rxdata_bus[2].delay_rgmii_rxd" IDELAY_VALUE = 13;
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166 | INST "*ETH_A*gmii_interface*rxdata_bus[3].delay_rgmii_rxd" IDELAY_VALUE = 13;
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167 |
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168 | INST "*ETH_A*gmii_interface*delay_rgmii_rx_ctl" IDELAY_VALUE = 13;
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169 |
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170 | INST "*ETH_A*gmii_interface*delay_rgmii_tx_clk" ODELAY_VALUE = 6;
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171 | INST "*ETH_A*gmii_interface*delay_rgmii_tx_clk" SIGNAL_PATTERN = CLOCK;
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172 |
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173 | # Group all IODELAY-related blocks to use a single IDELAYCTRL
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174 | INST "*ETH_A*dlyctrl" IODELAY_GROUP = ETH_rgmii_iodelay;
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175 | INST "*ETH_A*gmii_interface*delay_rgmii_rx_ctl" IODELAY_GROUP = ETH_rgmii_iodelay;
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176 | INST "*ETH_A*gmii_interface*rxdata_bus[?].delay_rgmii_rxd" IODELAY_GROUP = ETH_rgmii_iodelay;
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177 | INST "*ETH_A*gmii_interface*delay_rgmii_tx_clk" IODELAY_GROUP = ETH_rgmii_iodelay;
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178 |
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179 | # Spec: 1.2ns setup time, 1.2ns hold time
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180 | # The internal PHY delays were not used to derive the OFFSET constraints
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181 | # Changed NET Name
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182 | # This signal trace is longer than the clock trace, and arrives at the FPGA pin 64 ps after the clock
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183 | # Therefore the offset in constraint must have less setup time than nominal
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184 | NET "ETH_A_RGMII_RXD[0]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" RISING;
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185 | NET "ETH_A_RGMII_RXD[0]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" FALLING;
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186 |
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187 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 376 ps before the clock
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188 | # Therefore the offset in constraint must have more setup time than nominal
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189 | NET "ETH_A_RGMII_RXD[1]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" RISING;
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190 | NET "ETH_A_RGMII_RXD[1]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" FALLING;
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191 |
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192 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 372 ps before the clock
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193 | # Therefore the offset in constraint must have more setup time than nominal
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194 | NET "ETH_A_RGMII_RXD[2]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" RISING;
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195 | NET "ETH_A_RGMII_RXD[2]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" FALLING;
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196 |
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197 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 115 ps before the clock
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198 | # Therefore the offset in constraint must have more setup time than nominal
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199 | NET "ETH_A_RGMII_RXD[3]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" RISING;
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200 | NET "ETH_A_RGMII_RXD[3]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" FALLING;
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201 |
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202 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 292 ps before the clock
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203 | # Therefore the offset in constraint must have more setup time than nominal
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204 | NET "ETH_A_RGMII_RX_CTL" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" RISING;
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205 | NET "ETH_A_RGMII_RX_CTL" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" FALLING;
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206 |
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207 | ###############
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208 | # ETH_B Timing
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209 | INST "*ETH_B*gmii_interface*rxdata_bus[0].delay_rgmii_rxd" IDELAY_VALUE = 13;
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210 | INST "*ETH_B*gmii_interface*rxdata_bus[1].delay_rgmii_rxd" IDELAY_VALUE = 13;
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211 | INST "*ETH_B*gmii_interface*rxdata_bus[2].delay_rgmii_rxd" IDELAY_VALUE = 13;
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212 | INST "*ETH_B*gmii_interface*rxdata_bus[3].delay_rgmii_rxd" IDELAY_VALUE = 13;
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213 |
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214 | INST "*ETH_B*gmii_interface*delay_rgmii_rx_ctl" IDELAY_VALUE = 13;
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215 |
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216 | INST "*ETH_B*gmii_interface*delay_rgmii_tx_clk" ODELAY_VALUE = 6;
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217 | INST "*ETH_B*gmii_interface*delay_rgmii_tx_clk" SIGNAL_PATTERN = CLOCK;
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218 |
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219 | # Group all IODELAY-related blocks to use a single IDELAYCTRL
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220 | #INST "ETH_B*dlyctrl" IODELAY_GROUP = ETH_rgmii_iodelay;
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221 | INST "*ETH_B*gmii_interface*delay_rgmii_rx_ctl" IODELAY_GROUP = ETH_rgmii_iodelay;
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222 | INST "*ETH_B*gmii_interface*rxdata_bus[?].delay_rgmii_rxd" IODELAY_GROUP = ETH_rgmii_iodelay;
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223 | INST "*ETH_B*gmii_interface*delay_rgmii_tx_clk" IODELAY_GROUP = ETH_rgmii_iodelay;
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224 |
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225 | # Spec: 1.2ns setup time, 1.2ns hold time
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226 | # The internal PHY delays were not used to derive the OFFSET constraints
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227 | # Changed NET Name
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228 | # This signal trace is longer than the clock trace, and arrives at the FPGA pin 64 ps after the clock
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229 | # Therefore the offset in constraint must have less setup time than nominal
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230 | NET "ETH_B_RGMII_RXD[0]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" RISING;
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231 | NET "ETH_B_RGMII_RXD[0]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" FALLING;
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232 |
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233 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 376 ps before the clock
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234 | # Therefore the offset in constraint must have more setup time than nominal
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235 | NET "ETH_B_RGMII_RXD[1]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" RISING;
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236 | NET "ETH_B_RGMII_RXD[1]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" FALLING;
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237 |
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238 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 372 ps before the clock
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239 | # Therefore the offset in constraint must have more setup time than nominal
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240 | NET "ETH_B_RGMII_RXD[2]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" RISING;
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241 | NET "ETH_B_RGMII_RXD[2]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" FALLING;
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242 |
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243 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 115 ps before the clock
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244 | # Therefore the offset in constraint must have more setup time than nominal
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245 | NET "ETH_B_RGMII_RXD[3]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" RISING;
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246 | NET "ETH_B_RGMII_RXD[3]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" FALLING;
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247 |
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248 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 292 ps before the clock
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249 | # Therefore the offset in constraint must have more setup time than nominal
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250 | NET "ETH_B_RGMII_RX_CTL" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" RISING;
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251 | NET "ETH_B_RGMII_RX_CTL" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" FALLING;
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252 |
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253 | ############
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254 | NET RFA_AD_spi_sclk LOC = AB33 | IOSTANDARD = LVCMOS25;
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255 | NET RFA_AD_spi_sdio LOC = AC30 | IOSTANDARD = LVCMOS25;
|
---|
256 | NET RFA_AD_spi_cs_n LOC = AB31 | IOSTANDARD = LVCMOS25;
|
---|
257 | NET RFA_AD_reset_n LOC = AA34 | IOSTANDARD = LVCMOS25;
|
---|
258 |
|
---|
259 | NET RFB_AD_spi_sclk LOC = P32 | IOSTANDARD = LVCMOS25;
|
---|
260 | NET RFB_AD_spi_sdio LOC = P34 | IOSTANDARD = LVCMOS25;
|
---|
261 | NET RFB_AD_spi_cs_n LOC = N32 | IOSTANDARD = LVCMOS25;
|
---|
262 | NET RFB_AD_reset_n LOC = N34 | IOSTANDARD = LVCMOS25;
|
---|
263 |
|
---|
264 | #RFA AD9963
|
---|
265 | NET RFA_AD_TRXD<0> LOC = AC25 | IOSTANDARD = LVCMOS25;
|
---|
266 | NET RFA_AD_TRXD<1> LOC = AB25 | IOSTANDARD = LVCMOS25;
|
---|
267 | NET RFA_AD_TRXD<2> LOC = AB32 | IOSTANDARD = LVCMOS25;
|
---|
268 | NET RFA_AD_TRXD<3> LOC = AC29 | IOSTANDARD = LVCMOS25;
|
---|
269 | NET RFA_AD_TRXD<4> LOC = AD29 | IOSTANDARD = LVCMOS25;
|
---|
270 | NET RFA_AD_TRXD<5> LOC = AC33 | IOSTANDARD = LVCMOS25;
|
---|
271 | NET RFA_AD_TRXD<6> LOC = AD34 | IOSTANDARD = LVCMOS25;
|
---|
272 | NET RFA_AD_TRXD<7> LOC = AC32 | IOSTANDARD = LVCMOS25;
|
---|
273 | NET RFA_AD_TRXD<8> LOC = AD31 | IOSTANDARD = LVCMOS25;
|
---|
274 | NET RFA_AD_TRXD<9> LOC = AD32 | IOSTANDARD = LVCMOS25;
|
---|
275 | NET RFA_AD_TRXD<10> LOC = AE31 | IOSTANDARD = LVCMOS25;
|
---|
276 | NET RFA_AD_TRXD<11> LOC = AE32 | IOSTANDARD = LVCMOS25;
|
---|
277 |
|
---|
278 | NET RFA_AD_TRXCLK LOC = AD30 | IOSTANDARD = LVCMOS25;
|
---|
279 | NET RFA_AD_TRXIQ LOC = AC34 | IOSTANDARD = LVCMOS25;
|
---|
280 |
|
---|
281 | NET RFA_AD_TXCLK LOC = AA31 | IOSTANDARD = LVCMOS25;
|
---|
282 | NET RFA_AD_TXIQ LOC = AA33 | IOSTANDARD = LVCMOS25;
|
---|
283 |
|
---|
284 | NET RFA_AD_TXD<0> LOC = AA25 | IOSTANDARD = LVCMOS25;
|
---|
285 | NET RFA_AD_TXD<1> LOC = AB26 | IOSTANDARD = LVCMOS25;
|
---|
286 | NET RFA_AD_TXD<2> LOC = Y26 | IOSTANDARD = LVCMOS25;
|
---|
287 | NET RFA_AD_TXD<3> LOC = AA26 | IOSTANDARD = LVCMOS25;
|
---|
288 | NET RFA_AD_TXD<4> LOC = AA28 | IOSTANDARD = LVCMOS25;
|
---|
289 | NET RFA_AD_TXD<5> LOC = AA29 | IOSTANDARD = LVCMOS25;
|
---|
290 | NET RFA_AD_TXD<6> LOC = AA30 | IOSTANDARD = LVCMOS25;
|
---|
291 | NET RFA_AD_TXD<7> LOC = AB30 | IOSTANDARD = LVCMOS25;
|
---|
292 | NET RFA_AD_TXD<8> LOC = AB28 | IOSTANDARD = LVCMOS25;
|
---|
293 | NET RFA_AD_TXD<9> LOC = AB27 | IOSTANDARD = LVCMOS25;
|
---|
294 | NET RFA_AD_TXD<10> LOC = AC28 | IOSTANDARD = LVCMOS25;
|
---|
295 | NET RFA_AD_TXD<11> LOC = AC27 | IOSTANDARD = LVCMOS25;
|
---|
296 |
|
---|
297 | #RFB
|
---|
298 | NET RFB_AD_TRXD<0> LOC = N25 | IOSTANDARD = LVCMOS25;
|
---|
299 | NET RFB_AD_TRXD<1> LOC = M25 | IOSTANDARD = LVCMOS25;
|
---|
300 | NET RFB_AD_TRXD<2> LOC = N28 | IOSTANDARD = LVCMOS25;
|
---|
301 | NET RFB_AD_TRXD<3> LOC = N27 | IOSTANDARD = LVCMOS25;
|
---|
302 | NET RFB_AD_TRXD<4> LOC = P29 | IOSTANDARD = LVCMOS25;
|
---|
303 | NET RFB_AD_TRXD<5> LOC = M30 | IOSTANDARD = LVCMOS25;
|
---|
304 | NET RFB_AD_TRXD<6> LOC = N30 | IOSTANDARD = LVCMOS25;
|
---|
305 | NET RFB_AD_TRXD<7> LOC = N29 | IOSTANDARD = LVCMOS25;
|
---|
306 | NET RFB_AD_TRXD<8> LOC = P26 | IOSTANDARD = LVCMOS25;
|
---|
307 | NET RFB_AD_TRXD<9> LOC = P31 | IOSTANDARD = LVCMOS25;
|
---|
308 | NET RFB_AD_TRXD<10> LOC = P25 | IOSTANDARD = LVCMOS25;
|
---|
309 | NET RFB_AD_TRXD<11> LOC = P30 | IOSTANDARD = LVCMOS25;
|
---|
310 |
|
---|
311 | NET RFB_AD_TRXCLK LOC = N33 | IOSTANDARD = LVCMOS25;
|
---|
312 | NET RFB_AD_TRXIQ LOC = M33 | IOSTANDARD = LVCMOS25;
|
---|
313 |
|
---|
314 | NET RFB_AD_TXCLK LOC = L28 | IOSTANDARD = LVCMOS25;
|
---|
315 | NET RFB_AD_TXIQ LOC = L29 | IOSTANDARD = LVCMOS25;
|
---|
316 |
|
---|
317 | NET RFB_AD_TXD<0> LOC = K32 | IOSTANDARD = LVCMOS25;
|
---|
318 | NET RFB_AD_TXD<1> LOC = M26 | IOSTANDARD = LVCMOS25;
|
---|
319 | NET RFB_AD_TXD<2> LOC = M32 | IOSTANDARD = LVCMOS25;
|
---|
320 | NET RFB_AD_TXD<3> LOC = K34 | IOSTANDARD = LVCMOS25;
|
---|
321 | NET RFB_AD_TXD<4> LOC = M31 | IOSTANDARD = LVCMOS25;
|
---|
322 | NET RFB_AD_TXD<5> LOC = L30 | IOSTANDARD = LVCMOS25;
|
---|
323 | NET RFB_AD_TXD<6> LOC = L33 | IOSTANDARD = LVCMOS25;
|
---|
324 | NET RFB_AD_TXD<7> LOC = L31 | IOSTANDARD = LVCMOS25;
|
---|
325 | NET RFB_AD_TXD<8> LOC = M28 | IOSTANDARD = LVCMOS25;
|
---|
326 | NET RFB_AD_TXD<9> LOC = L34 | IOSTANDARD = LVCMOS25;
|
---|
327 | NET RFB_AD_TXD<10> LOC = M27 | IOSTANDARD = LVCMOS25;
|
---|
328 | NET RFB_AD_TXD<11> LOC = K31 | IOSTANDARD = LVCMOS25;
|
---|
329 |
|
---|
330 | NET RF_RSSI_CLK LOC = B32 | IOSTANDARD = LVCMOS25;
|
---|
331 | NET RF_RSSI_PD LOC = B34 | IOSTANDARD = LVCMOS25;
|
---|
332 | NET RFB_RSSI_D<0> LOC = A33 | IOSTANDARD = LVCMOS25;
|
---|
333 | NET RFB_RSSI_D<1> LOC = B33 | IOSTANDARD = LVCMOS25;
|
---|
334 | NET RFB_RSSI_D<2> LOC = C33 | IOSTANDARD = LVCMOS25;
|
---|
335 | NET RFB_RSSI_D<3> LOC = C34 | IOSTANDARD = LVCMOS25;
|
---|
336 | NET RFB_RSSI_D<4> LOC = C32 | IOSTANDARD = LVCMOS25;
|
---|
337 | NET RFB_RSSI_D<5> LOC = D31 | IOSTANDARD = LVCMOS25;
|
---|
338 | NET RFB_RSSI_D<6> LOC = G30 | IOSTANDARD = LVCMOS25;
|
---|
339 | NET RFB_RSSI_D<7> LOC = E31 | IOSTANDARD = LVCMOS25;
|
---|
340 | NET RFB_RSSI_D<8> LOC = D32 | IOSTANDARD = LVCMOS25;
|
---|
341 | NET RFB_RSSI_D<9> LOC = D34 | IOSTANDARD = LVCMOS25;
|
---|
342 | NET RFA_RSSI_D<0> LOC = E32 | IOSTANDARD = LVCMOS25;
|
---|
343 | NET RFA_RSSI_D<1> LOC = E33 | IOSTANDARD = LVCMOS25;
|
---|
344 | NET RFA_RSSI_D<2> LOC = E34 | IOSTANDARD = LVCMOS25;
|
---|
345 | NET RFA_RSSI_D<3> LOC = F30 | IOSTANDARD = LVCMOS25;
|
---|
346 | NET RFA_RSSI_D<4> LOC = F31 | IOSTANDARD = LVCMOS25;
|
---|
347 | NET RFA_RSSI_D<5> LOC = F34 | IOSTANDARD = LVCMOS25;
|
---|
348 | NET RFA_RSSI_D<6> LOC = F33 | IOSTANDARD = LVCMOS25;
|
---|
349 | NET RFA_RSSI_D<7> LOC = G31 | IOSTANDARD = LVCMOS25;
|
---|
350 | NET RFA_RSSI_D<8> LOC = G33 | IOSTANDARD = LVCMOS25;
|
---|
351 | NET RFA_RSSI_D<9> LOC = G32 | IOSTANDARD = LVCMOS25;
|
---|
352 |
|
---|
353 | #######################################
|
---|
354 | #MAX2829 transceivers and RF front end
|
---|
355 | NET RFA_SPI_SCLK LOC=T34 | IOSTANDARD=LVCMOS25;
|
---|
356 | NET RFA_SPI_MOSI LOC=T33 | IOSTANDARD=LVCMOS25;
|
---|
357 | NET RFA_SPI_CSn LOC=U32 | IOSTANDARD=LVCMOS25;
|
---|
358 | NET RFA_SHDN LOC=U27 | IOSTANDARD=LVCMOS25;
|
---|
359 | NET RFA_TxEn LOC=T31 | IOSTANDARD=LVCMOS25;
|
---|
360 | NET RFA_RxEn LOC=U33 | IOSTANDARD=LVCMOS25;
|
---|
361 | NET RFA_RxHP LOC=AG32 | IOSTANDARD=LVCMOS25;
|
---|
362 | NET RFA_PAEn_24 LOC=U25 | IOSTANDARD=LVCMOS25;
|
---|
363 | NET RFA_PAEn_5 LOC=U28 | IOSTANDARD=LVCMOS25;
|
---|
364 | NET RFA_ANTSW<0> LOC=U31 | IOSTANDARD=LVCMOS25;
|
---|
365 | NET RFA_ANTSW<1> LOC=U30 | IOSTANDARD=LVCMOS25;
|
---|
366 | NET RFA_LD LOC=U26 | IOSTANDARD=LVCMOS25;
|
---|
367 | NET RFA_B<0> LOC=AG33 | IOSTANDARD=LVCMOS25;
|
---|
368 | NET RFA_B<1> LOC=AF31 | IOSTANDARD=LVCMOS25;
|
---|
369 | NET RFA_B<2> LOC=AF33 | IOSTANDARD=LVCMOS25;
|
---|
370 | NET RFA_B<3> LOC=AG31 | IOSTANDARD=LVCMOS25;
|
---|
371 | NET RFA_B<4> LOC=AF34 | IOSTANDARD=LVCMOS25;
|
---|
372 | NET RFA_B<5> LOC=AE33 | IOSTANDARD=LVCMOS25;
|
---|
373 | NET RFA_B<6> LOC=AE34 | IOSTANDARD=LVCMOS25;
|
---|
374 |
|
---|
375 | NET RFB_SPI_SCLK LOC=H34 | IOSTANDARD=LVCMOS25;
|
---|
376 | NET RFB_SPI_MOSI LOC=H33 | IOSTANDARD=LVCMOS25;
|
---|
377 | NET RFB_SPI_CSn LOC=J32 | IOSTANDARD=LVCMOS25;
|
---|
378 | NET RFB_SHDN LOC=J34 | IOSTANDARD=LVCMOS25;
|
---|
379 | NET RFB_TxEn LOC=H32 | IOSTANDARD=LVCMOS25;
|
---|
380 | NET RFB_RxEn LOC=J31 | IOSTANDARD=LVCMOS25;
|
---|
381 | NET RFB_RxHP LOC=R28 | IOSTANDARD=LVCMOS25;
|
---|
382 | NET RFB_PAEn_24 LOC=T25 | IOSTANDARD=LVCMOS25;
|
---|
383 | NET RFB_PAEn_5 LOC=T28 | IOSTANDARD=LVCMOS25;
|
---|
384 | NET RFB_ANTSW<0> LOC=T30 | IOSTANDARD=LVCMOS25;
|
---|
385 | NET RFB_ANTSW<1> LOC=T29 | IOSTANDARD=LVCMOS25;
|
---|
386 | NET RFB_LD LOC=K33 | IOSTANDARD=LVCMOS25;
|
---|
387 | NET RFB_B<0> LOC=P27 | IOSTANDARD=LVCMOS25;
|
---|
388 | NET RFB_B<1> LOC=R27 | IOSTANDARD=LVCMOS25;
|
---|
389 | NET RFB_B<2> LOC=R29 | IOSTANDARD=LVCMOS25;
|
---|
390 | NET RFB_B<3> LOC=R26 | IOSTANDARD=LVCMOS25;
|
---|
391 | NET RFB_B<4> LOC=R32 | IOSTANDARD=LVCMOS25;
|
---|
392 | NET RFB_B<5> LOC=T26 | IOSTANDARD=LVCMOS25;
|
---|
393 | NET RFB_B<6> LOC=R31 | IOSTANDARD=LVCMOS25;
|
---|
394 |
|
---|
395 | #AD9963 data interface clock constraints
|
---|
396 | Net RFA_AD_TRXCLK TNM_NET = TNM_RFA_AD_TRXCLK;
|
---|
397 | Net RFB_AD_TRXCLK TNM_NET = TNM_RFB_AD_TRXCLK;
|
---|
398 |
|
---|
399 | #TRXCLK runs up to 40MHz (no decimation in AD9963s)
|
---|
400 | TIMESPEC TS_RFA_AD_TRXCLK = PERIOD TNM_RFA_AD_TRXCLK TS_samp_clk*2;
|
---|
401 | TIMESPEC TS_RFB_AD_TRXCLK = PERIOD TNM_RFB_AD_TRXCLK TS_samp_clk*2;
|
---|
402 |
|
---|
403 | #Define relationship of TRXD and TRXCLK, based on AD9963 specs
|
---|
404 | # Using worst-case output delay from AD9963 datasheet table 23
|
---|
405 | # TRXCLK leads TRXD transition by t_OD2; ad_bridge uses IDELAY to shift this to mid valid window
|
---|
406 | # VALID window below assumes DDR interleaved I/Q at 20MSps rate (25nsec / half sample)
|
---|
407 | INST "RFA_AD_TRXD<*>" TNM = RFA_AD_TRXD_group;
|
---|
408 | NET "RFA_AD_TRXCLK" TNM_NET = RFA_AD_TRXCLK;
|
---|
409 | TIMEGRP "RFA_AD_TRXD_group" OFFSET = IN 0.7 ns VALID 22 ns BEFORE "RFA_AD_TRXCLK" RISING;
|
---|
410 | TIMEGRP "RFA_AD_TRXD_group" OFFSET = IN 0.7 ns VALID 22 ns BEFORE "RFA_AD_TRXCLK" FALLING;
|
---|
411 |
|
---|
412 | INST "RFB_AD_TRXD<*>" TNM = RFB_AD_TRXD_group;
|
---|
413 | NET "RFB_AD_TRXCLK" TNM_NET = RFB_AD_TRXCLK;
|
---|
414 | TIMEGRP "RFB_AD_TRXD_group" OFFSET = IN 0.7 ns VALID 22 ns BEFORE "RFB_AD_TRXCLK" RISING;
|
---|
415 | TIMEGRP "RFB_AD_TRXD_group" OFFSET = IN 0.7 ns VALID 22 ns BEFORE "RFB_AD_TRXCLK" FALLING;
|
---|
416 |
|
---|
417 | #Relaxed constraints for T=8 paths through Rx PHY (mostly in DSSS Rx)
|
---|
418 | NET "*wlan_phy_rx*ce_8_sg_x*" TNM_NET = "TNM_rx_phy_CE8";
|
---|
419 | TIMESPEC TS_rx_phy_T8 = FROM "TNM_rx_phy_CE8" TO "TNM_rx_phy_CE8" 20 MHz;
|
---|
420 |
|
---|
421 | # Basic floorplanning
|
---|
422 | INST "wlan_phy_tx" AREA_GROUP = "WLAN_PHY_Tx";
|
---|
423 | AREA_GROUP "WLAN_PHY_Tx" RANGE=SLICE_X10Y81:SLICE_X65Y139;
|
---|
424 | AREA_GROUP "WLAN_PHY_Tx" RANGE=DSP48_X0Y34:DSP48_X3Y55;
|
---|
425 | AREA_GROUP "WLAN_PHY_Tx" RANGE=RAMB18_X1Y34:RAMB18_X3Y55;
|
---|
426 | AREA_GROUP "WLAN_PHY_Tx" RANGE=RAMB36_X1Y17:RAMB36_X3Y27;
|
---|
427 |
|
---|
428 | INST "DDR3_SODIMM" AREA_GROUP = "DDR3_SODIMM";
|
---|
429 | AREA_GROUP "DDR3_SODIMM" RANGE=SLICE_X56Y60:SLICE_X99Y79, SLICE_X12Y0:SLICE_X123Y59;
|
---|
430 | AREA_GROUP "DDR3_SODIMM" RANGE=DSP48_X0Y0:DSP48_X5Y23;
|
---|
431 | AREA_GROUP "DDR3_SODIMM" RANGE=RAMB18_X1Y0:RAMB18_X5Y23;
|
---|
432 | AREA_GROUP "DDR3_SODIMM" RANGE=RAMB36_X1Y0:RAMB36_X5Y11;
|
---|
433 |
|
---|
434 | INST "wlan_phy_rx" AREA_GROUP = "WLAN_PHY_Rx";
|
---|
435 | AREA_GROUP "WLAN_PHY_Rx" RANGE=SLICE_X0Y140:SLICE_X161Y239;
|
---|
436 | AREA_GROUP "WLAN_PHY_Rx" RANGE=DSP48_X0Y56:DSP48_X7Y95;
|
---|
437 | AREA_GROUP "WLAN_PHY_Rx" RANGE=RAMB18_X0Y56:RAMB18_X8Y95;
|
---|
438 | AREA_GROUP "WLAN_PHY_Rx" RANGE=RAMB36_X0Y28:RAMB36_X8Y47;
|
---|
439 |
|
---|
440 | INST "wlan_agc" AREA_GROUP = "WLAN_AGC";
|
---|
441 | AREA_GROUP "WLAN_AGC" RANGE=SLICE_X0Y40:SLICE_X13Y140;
|
---|
442 | AREA_GROUP "WLAN_AGC" RANGE=DSP48_X0Y16:DSP48_X0Y55;
|
---|
443 | AREA_GROUP "WLAN_AGC" RANGE=RAMB18_X0Y16:RAMB18_X0Y55;
|
---|
444 | AREA_GROUP "WLAN_AGC" RANGE=RAMB36_X0Y8:RAMB36_X0Y27;
|
---|
445 |
|
---|
446 | INST "ad_bridge_onBoard" AREA_GROUP = "AD_Bridge_OnBoard";
|
---|
447 | AREA_GROUP "AD_Bridge_OnBoard" RANGE=SLICE_X0Y41:SLICE_X1Y159;
|
---|
448 |
|
---|
449 | INST "mb_high" AREA_GROUP = "MB_High_Subsystem";
|
---|
450 | INST "mb_high_dlmb" AREA_GROUP = "MB_High_Subsystem";
|
---|
451 | INST "mb_high_ilmb" AREA_GROUP = "MB_High_Subsystem";
|
---|
452 | INST "mb_high_dlmb_bram_cntlr_0" AREA_GROUP = "MB_High_Subsystem";
|
---|
453 | INST "mb_high_ilmb_bram_cntlr_0" AREA_GROUP = "MB_High_Subsystem";
|
---|
454 | INST "mb_high_dlmb_bram_cntlr_1" AREA_GROUP = "MB_High_Subsystem";
|
---|
455 | INST "mb_high_ilmb_bram_cntlr_1" AREA_GROUP = "MB_High_Subsystem";
|
---|
456 | INST "mb_high_lmb_bram_0" AREA_GROUP = "MB_High_Subsystem";
|
---|
457 | INST "mb_high_lmb_bram_1" AREA_GROUP = "MB_High_Subsystem";
|
---|
458 | AREA_GROUP "MB_High_Subsystem" RANGE=SLICE_X100Y0:SLICE_X161Y79;
|
---|
459 | AREA_GROUP "MB_High_Subsystem" RANGE=DSP48_X4Y0:DSP48_X7Y31;
|
---|
460 | AREA_GROUP "MB_High_Subsystem" RANGE=RAMB18_X4Y0:RAMB18_X8Y31;
|
---|
461 | AREA_GROUP "MB_High_Subsystem" RANGE=RAMB36_X4Y0:RAMB36_X8Y15;
|
---|