source:
ReferenceDesigns/w3_802.11/sysgen/wlan_phy_tx_pmd/blackboxes
Name | Size | Rev | Age | Author | Last Change |
---|---|---|---|---|---|
../ | |||||
dp_ram_wr_1b_rd_8b_512b.ngc | 12.7 KB | 5110 | 8 years | murphpo | Updating interleaver RAM black box |
dp_ram_wr_1b_rd_8b_512b.xco | 3.2 KB | 5119 | 8 years | murphpo | adding coregen xco file for interleaver RAM core |
interleaver_ram.m | 3.6 KB | 5112 | 8 years | murphpo | Fixed blackbox issue (verilog ports must be vectors if VHDL wrapper … |
interleaver_ram.v | 5.4 KB | 5118 | 8 years | murphpo | Better comments in black box wrapper |
Note: See TracBrowser
for help on using the repository browser.