@echo off
REM Copyright 2012 Xilinx, Inc. All rights reserved.

echo.
echo Synthesizing netlists...
echo.
xflow.exe -p xc4vfx100ff1517-11 -synth xst_verilog.opt fec_decoder_top.prj

mv fec_decoder_top.ngc fec_decoder_simOnly.ngc

echo.
echo Generating simulation model...
echo.
netgen -sim -ofmt verilog -tm fec_decoder_simOnly fec_decoder_simOnly.ngc