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Last change
on this file was
1733,
checked in by murphpo, 12 years ago
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Updated PHY model with two fec_decoder black boxes and sim mux to select between them for sim/implementation. Also added script for generating simulation-only verilog for fec_decoder. All this is workaround for MATLAB crashing during simulation due to a bug in isim/Sysgen 13.4 that's under investigation by Xilinx.
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File size:
65 bytes
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| 1 | verilog work fec_decoder_rest.v |
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| 2 | verilog work fec_decoder_top.v |
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