| 1 | FLOWTYPE = FPGA_SYNTHESIS; |
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| 2 | ######################################################### |
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| 3 | ## Filename: xst_verilog.opt |
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| 4 | ## |
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| 5 | ## Verilog Option File for XST targeted for speed |
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| 6 | ## This works for FPGA devices. |
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| 7 | ## |
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| 8 | ## Version: 13.1 |
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| 9 | ## $Header: /devl/xcs/repo/env/Jobs/Xflow/data/optionfiles/fpga_xst_verilog_speed.opt,v 1.16 2011/01/07 21:14:39 rvklair Exp $ |
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| 10 | ######################################################### |
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| 11 | # |
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| 12 | # Options for XST |
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| 13 | # |
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| 14 | # |
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| 15 | Program xst |
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| 16 | -ifn <design>_xst.scr; # input XST script file |
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| 17 | -ofn <design>_xst.log; # output XST log file |
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| 18 | -intstyle xflow; # Message Reporting Style: ise, xflow, or silent |
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| 19 | # |
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| 20 | # The options listed under ParamFile are the XST Properties that can be set by the |
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| 21 | # user. To turn on an option, uncomment by removing the '#' in front of the switch. |
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| 22 | # |
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| 23 | ParamFile: <design>_xst.scr |
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| 24 | "run"; |
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| 25 | # |
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| 26 | # Global Synthesis Options |
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| 27 | # |
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| 28 | "-top fec_decoder_top"; |
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| 29 | "-ifn <synthdesign>"; # Input/Project File Name |
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| 30 | "-ifmt Mixed"; # Input Format |
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| 31 | "-ofn <design>"; # Output File Name |
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| 32 | "-ofmt ngc"; # Output File Format |
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| 33 | "-p <partname>"; # Target Device |
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| 34 | "-verilog2001 YES"; # Enables the use of Verilog 2001 Constructs |
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| 35 | # YES, NO |
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| 36 | #"-opt_mode SPEED"; # Optimization Criteria |
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| 37 | # AREA or SPEED |
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| 38 | #"-uc <design>.xcf"; # Constraint File name |
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| 39 | #"-case maintain"; # Specifies how to handle source name case |
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| 40 | # upper, lower, maintain |
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| 41 | #"-keep_hierarchy NO"; # Prevents optimization across module boundaries |
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| 42 | # CPLD default YES, FPGA default NO |
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| 43 | #"-write_timing_constraints NO"; # Write Timing Constraints |
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| 44 | # YES, NO |
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| 45 | #"-cross_clock_analysis NO"; # Cross Clock Option |
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| 46 | # YES, NO |
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| 47 | #"-iobuf YES"; # Add I/O Buffers to top level ports |
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| 48 | # YES, NO |
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| 49 | # |
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| 50 | # The following are HDL Options |
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| 51 | # |
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| 52 | # The following are Xilinx FPGA specific options for Virtex, VirtexE, Virtex-II and Spartan2 |
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| 53 | # |
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| 54 | #"-register_balancing NO"; # Register Balancing |
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| 55 | # YES, NO, Forward, Backward |
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| 56 | #"-move_first_stage YES"; # Move First Flip-Flop Stage |
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| 57 | # YES, NO |
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| 58 | #"-move_last_stage YES"; # Move Last Flip-Flop Stage |
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| 59 | # YES, NO |
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| 60 | End ParamFile |
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| 61 | End Program xst |
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| 62 | # |
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| 63 | # See XST USER Guide Chapter 8 (Command Line Mode) for all XST options |
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| 64 | # |
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| 65 | |
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| 66 | |
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