1 | |
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2 | function fec_encoder_config(this_block) |
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3 | |
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4 | % Revision History: |
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5 | % |
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6 | % 11-Oct-2010 (22:47 hours): |
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7 | % Original code was machine generated by Xilinx's System Generator after parsing |
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8 | % E:\My Dropbox\Project\WARP\Sysgen\Rev4\fec_encoder.v |
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9 | % |
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10 | % |
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11 | |
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12 | this_block.setTopLevelLanguage('Verilog'); |
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13 | |
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14 | this_block.setEntityName('fec_encoder'); |
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15 | |
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16 | % System Generator has to assume that your entity has a combinational feed through; |
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17 | % if it doesn't, then comment out the following line: |
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18 | this_block.tagAsCombinational; |
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19 | |
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20 | this_block.addSimulinkInport('nrst'); |
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21 | this_block.addSimulinkInport('start'); |
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22 | this_block.addSimulinkInport('coding_en'); |
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23 | this_block.addSimulinkInport('pkt_done'); |
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24 | this_block.addSimulinkInport('fec_rd'); |
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25 | this_block.addSimulinkInport('info_data'); |
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26 | this_block.addSimulinkInport('info_scram'); |
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27 | this_block.addSimulinkInport('info_len'); |
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28 | |
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29 | this_block.addSimulinkOutport('codeword_len'); |
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30 | this_block.addSimulinkOutport('info_rd'); |
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31 | this_block.addSimulinkOutport('info_raddr'); |
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32 | this_block.addSimulinkOutport('fec_data'); |
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33 | |
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34 | codeword_len_port = this_block.port('codeword_len'); |
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35 | codeword_len_port.setType('UFix_16_0'); |
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36 | info_rd_port = this_block.port('info_rd'); |
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37 | info_rd_port.setType('Bool'); |
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38 | info_rd_port.useHDLVector(false); |
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39 | info_raddr_port = this_block.port('info_raddr'); |
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40 | info_raddr_port.setType('UFix_14_0'); |
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41 | fec_data_port = this_block.port('fec_data'); |
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42 | fec_data_port.setType('UFix_8_0'); |
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43 | |
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44 | % ----------------------------- |
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45 | if (this_block.inputTypesKnown) |
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46 | % do input type checking, dynamic output type and generic setup in this code block. |
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47 | |
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48 | if (this_block.port('nrst').width ~= 1); |
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49 | this_block.setError('Input data type for port "nrst" must have width=1.'); |
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50 | end |
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51 | |
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52 | this_block.port('nrst').useHDLVector(false); |
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53 | |
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54 | if (this_block.port('start').width ~= 1); |
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55 | this_block.setError('Input data type for port "start" must have width=1.'); |
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56 | end |
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57 | |
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58 | this_block.port('start').useHDLVector(false); |
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59 | |
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60 | if (this_block.port('coding_en').width ~= 1); |
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61 | this_block.setError('Input data type for port "coding_en" must have width=1.'); |
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62 | end |
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63 | |
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64 | this_block.port('coding_en').useHDLVector(false); |
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65 | |
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66 | if (this_block.port('pkt_done').width ~= 1); |
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67 | this_block.setError('Input data type for port "pkt_done" must have width=1.'); |
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68 | end |
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69 | |
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70 | this_block.port('pkt_done').useHDLVector(false); |
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71 | |
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72 | if (this_block.port('fec_rd').width ~= 1); |
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73 | this_block.setError('Input data type for port "fec_rd" must have width=1.'); |
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74 | end |
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75 | |
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76 | this_block.port('fec_rd').useHDLVector(false); |
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77 | |
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78 | if (this_block.port('info_data').width ~= 8); |
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79 | this_block.setError('Input data type for port "info_data" must have width=8.'); |
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80 | end |
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81 | |
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82 | if (this_block.port('info_scram').width ~= 8); |
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83 | this_block.setError('Input data type for port "info_scram" must have width=8.'); |
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84 | end |
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85 | |
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86 | if (this_block.port('info_len').width ~= 16); |
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87 | this_block.setError('Input data type for port "info_len" must have width=16.'); |
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88 | end |
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89 | |
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90 | end % if(inputTypesKnown) |
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91 | % ----------------------------- |
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92 | |
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93 | % ----------------------------- |
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94 | if (this_block.inputRatesKnown) |
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95 | setup_as_single_rate(this_block,'clk','ce') |
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96 | end % if(inputRatesKnown) |
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97 | % ----------------------------- |
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98 | |
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99 | % (!) Set the inout port rate to be the same as the first input |
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100 | % rate. Change the following code if this is untrue. |
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101 | uniqueInputRates = unique(this_block.getInputRates); |
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102 | |
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103 | |
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104 | % Add addtional source files as needed. |
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105 | % |------------- |
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106 | % | Add files in the order in which they should be compiled. |
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107 | % | If two files "a.vhd" and "b.vhd" contain the entities |
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108 | % | entity_a and entity_b, and entity_a contains a |
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109 | % | component of type entity_b, the correct sequence of |
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110 | % | addFile() calls would be: |
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111 | % | this_block.addFile('b.vhd'); |
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112 | % | this_block.addFile('a.vhd'); |
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113 | % |------------- |
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114 | |
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115 | % this_block.addFile(''); |
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116 | % this_block.addFile(''); |
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117 | this_block.addFile('fec_encoder.v'); |
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118 | |
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119 | return; |
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120 | |
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121 | |
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122 | % ------------------------------------------------------------ |
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123 | |
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124 | function setup_as_single_rate(block,clkname,cename) |
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125 | inputRates = block.inputRates; |
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126 | uniqueInputRates = unique(inputRates); |
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127 | if (length(uniqueInputRates)==1 & uniqueInputRates(1)==Inf) |
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128 | block.addError('The inputs to this block cannot all be constant.'); |
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129 | return; |
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130 | end |
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131 | if (uniqueInputRates(end) == Inf) |
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132 | hasConstantInput = true; |
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133 | uniqueInputRates = uniqueInputRates(1:end-1); |
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134 | end |
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135 | if (length(uniqueInputRates) ~= 1) |
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136 | block.addError('The inputs to this block must run at a single rate.'); |
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137 | return; |
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138 | end |
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139 | theInputRate = uniqueInputRates(1); |
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140 | for i = 1:block.numSimulinkOutports |
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141 | block.outport(i).setRate(theInputRate); |
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142 | end |
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143 | block.addClkCEPair(clkname,cename,theInputRate); |
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144 | return; |
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145 | |
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146 | % ------------------------------------------------------------ |
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147 | |
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