| 1 | /** @file wl_baseband.h |
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| 2 | * @brief WARPLab Framework (Baseband) |
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| 3 | * |
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| 4 | * This contains the code for WARPLab Framework. |
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| 5 | * |
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| 6 | * @copyright Copyright 2013, Mango Communications. All rights reserved. |
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| 7 | * Distributed under the WARP license (http://warpproject.org/license) |
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| 8 | * |
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| 9 | * @author Chris Hunter (chunter [at] mangocomm.com) |
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| 10 | * @author Patrick Murphy (murphpo [at] mangocomm.com) |
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| 11 | * @author Erik Welsh (welsh [at] mangocomm.com) |
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| 12 | */ |
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| 13 | |
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| 14 | /**********************************************************************************************************************/ |
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| 15 | /** |
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| 16 | * @brief Common Functions (WARP v2 and WARP v3) |
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| 17 | * |
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| 18 | **********************************************************************************************************************/ |
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| 19 | |
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| 20 | /***************************** Include Files *********************************/ |
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| 21 | |
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| 22 | // Xilinx / Standard library includes |
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| 23 | #include <xparameters.h> |
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| 24 | |
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| 25 | // WARPLab includes |
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| 26 | #include "wl_common.h" |
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| 27 | |
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| 28 | |
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| 29 | /*************************** Constant Definitions ****************************/ |
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| 30 | #ifndef WL_BASEBAND_H_ |
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| 31 | #define WL_BASEBAND_H_ |
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| 32 | |
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| 33 | // ********************************************************************** |
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| 34 | // Command IDs (must match the CMD_ properties in wl_baseband_buffers.m) |
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| 35 | // |
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| 36 | #define CMDID_BASEBAND_TX_DELAY 0x000001 |
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| 37 | #define CMDID_BASEBAND_TX_LENGTH 0x000002 |
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| 38 | #define CMDID_BASEBAND_TX_MODE 0x000003 |
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| 39 | #define CMDID_BASEBAND_TX_BUFF_EN 0x000004 |
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| 40 | #define CMDID_BASEBAND_RX_BUFF_EN 0x000005 |
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| 41 | #define CMDID_BASEBAND_TXRX_BUFF_DIS 0x000006 |
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| 42 | #define CMDID_BASEBAND_TXRX_BUFF_STATE 0x000007 |
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| 43 | #define CMDID_BASEBAND_WRITE_IQ 0x000008 |
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| 44 | #define CMDID_BASEBAND_READ_IQ 0x000009 |
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| 45 | #define CMDID_BASEBAND_READ_RSSI 0x00000A |
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| 46 | #define CMDID_BASEBAND_RX_LENGTH 0x00000B |
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| 47 | #define CMDID_BASEBAND_WRITE_IQ_CHECKSUM 0x00000C |
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| 48 | #define CMDID_BASEBAND_MAX_NUM_SAMPLES 0x00000D |
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| 49 | |
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| 50 | #define CMDID_BASEBAND_TXRX_COUNT_RESET 0x000010 |
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| 51 | #define CMDID_BASEBAND_TXRX_COUNT_GET 0x000011 |
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| 52 | |
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| 53 | #define CMDID_BASEBAND_AGC_STATE 0x000100 |
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| 54 | #define CMDID_BASEBAND_AGC_DONE_ADDR 0x000101 |
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| 55 | #define CMDID_BASEBAND_AGC_RESET 0x000102 |
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| 56 | #define CMDID_BASEBAND_AGC_RESET_MODE 0x000103 |
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| 57 | |
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| 58 | #define CMDID_BASEBAND_AGC_TARGET 0x000110 |
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| 59 | #define CMDID_BASEBAND_AGC_DCO_EN_DIS 0x000111 |
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| 60 | |
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| 61 | #define CMDID_BASEBAND_AGC_CONFIG 0x000120 |
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| 62 | #define CMDID_BASEBAND_AGC_IIR_HPF 0x000121 |
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| 63 | #define CMDID_BASEBAND_AGC_RF_GAIN_THRESHOLD 0x000122 |
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| 64 | #define CMDID_BASEBAND_AGC_TIMING 0x000123 |
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| 65 | #define CMDID_BASEBAND_AGC_DCO_TIMING 0x000124 |
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| 66 | |
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| 67 | |
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| 68 | |
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| 69 | // #define CMDID_BASEBAND_DEBUG_TX_OUTPUT_CONFIGURE 0x000080 |
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| 70 | |
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| 71 | |
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| 72 | // ********************************************************************** |
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| 73 | // WARPLab Buffers core debug parameters |
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| 74 | // |
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| 75 | #define USE_GENERATED_RX_DATA 0 |
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| 76 | #define USE_TX_RX_LOOPBACK 0 |
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| 77 | |
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| 78 | |
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| 79 | // ********************************************************************** |
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| 80 | // Samples Constants |
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| 81 | // |
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| 82 | #define BYTES_PER_SAMP 4 |
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| 83 | |
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| 84 | |
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| 85 | |
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| 86 | // ********************************************************************** |
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| 87 | // Misc Constants |
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| 88 | // |
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| 89 | #define INIT_TX_DELAY 0 |
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| 90 | #define WL_BUF_DEBUG_4RF_ON_2RF 0 |
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| 91 | |
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| 92 | |
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| 93 | |
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| 94 | // ********************************************************************** |
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| 95 | // Command Parameter Constants |
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| 96 | // |
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| 97 | #define CMD_PARAM_BASEBAND_TXRX_COUNT_GET_TX 0 |
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| 98 | #define CMD_PARAM_BASEBAND_TXRX_COUNT_GET_RX 1 |
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| 99 | |
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| 100 | #define CMD_PARAM_BASEBAND_TXRX_COUNT_GET_COUNT_RSVD 0xFFFFFFFF |
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| 101 | |
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| 102 | |
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| 103 | |
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| 104 | |
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| 105 | // ********************************************************************** |
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| 106 | // Common memory defines for BRAM sample buffers |
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| 107 | // - ASSUME: all BRAM memories are the same size |
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| 108 | // |
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| 109 | #define WARPLAB_IQ_RX_BUF_SIZE WARPLAB_IQ_RX_BUF_A_SIZE |
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| 110 | #define WARPLAB_IQ_TX_BUF_SIZE WARPLAB_IQ_TX_BUF_A_SIZE |
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| 111 | #define WARPLAB_RSSI_BUF_SIZE WARPLAB_RSSI_BUF_A_SIZE |
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| 112 | |
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| 113 | #define WL_BUF_DEFAULT_RX_NUM_SAMPLES ((WARPLAB_IQ_RX_BUF_A_SIZE >> 2) - 1) |
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| 114 | #define WL_BUF_DEFAULT_TX_NUM_SAMPLES ((WARPLAB_IQ_TX_BUF_A_SIZE >> 2) - 1) |
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| 115 | |
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| 116 | |
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| 117 | |
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| 118 | // ********************************************************************** |
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| 119 | // Defines for WARPLab Buffers Core |
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| 120 | // - Renamed from XPAR* here for easier maintenance |
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| 121 | // |
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| 122 | |
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| 123 | // Buffers Register definitions |
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| 124 | #define WL_BUF_REG_DESIGN_VER XPAR_WARPLAB_BUFFERS_MEMMAP_DESIGN_VER |
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| 125 | #define WL_BUF_REG_BUF_SIZES XPAR_WARPLAB_BUFFERS_MEMMAP_BUFF_SIZES |
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| 126 | #define WL_BUF_REG_CONFIG XPAR_WARPLAB_BUFFERS_MEMMAP_CONFIG |
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| 127 | #define WL_BUF_REG_STATUS XPAR_WARPLAB_BUFFERS_MEMMAP_STATUS |
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| 128 | |
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| 129 | #define WL_BUF_REG_TX_DELAY XPAR_WARPLAB_BUFFERS_MEMMAP_TX_DELAY |
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| 130 | #define WL_BUF_REG_RX_LENGTH XPAR_WARPLAB_BUFFERS_MEMMAP_RX_LENGTH |
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| 131 | #define WL_BUF_REG_TX_LENGTH XPAR_WARPLAB_BUFFERS_MEMMAP_TX_LENGTH |
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| 132 | |
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| 133 | #define WL_BUF_REG_RF_BUFFER_SEL XPAR_WARPLAB_BUFFERS_MEMMAP_RF_BUFFER_SEL |
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| 134 | #define WL_BUF_REG_RX_BUF_EN XPAR_WARPLAB_BUFFERS_MEMMAP_RX_BUF_EN |
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| 135 | #define WL_BUF_REG_TX_BUF_EN XPAR_WARPLAB_BUFFERS_MEMMAP_TX_BUF_EN |
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| 136 | |
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| 137 | #define WL_BUF_REG_AGC_DONE_ADDR XPAR_WARPLAB_BUFFERS_MEMMAP_AGC_DONE_ADDR |
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| 138 | #define WL_BUF_REG_RF_AB_AGC_DONE_RSSI XPAR_WARPLAB_BUFFERS_MEMMAP_RFAB_AGC_DONE_RSSI |
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| 139 | #define WL_BUF_REG_RF_CD_AGC_DONE_RSSI XPAR_WARPLAB_BUFFERS_MEMMAP_RFCD_AGC_DONE_RSSI |
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| 140 | |
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| 141 | #define WL_BUF_REG_RF_RX_IQ_BUF_RD_BYTE_OFFSET XPAR_WARPLAB_BUFFERS_MEMMAP_RF_RX_IQ_BUF_RD_BYTE_OFFSET |
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| 142 | #define WL_BUF_REG_RF_RX_IQ_BUF_WR_BYTE_OFFSET XPAR_WARPLAB_BUFFERS_MEMMAP_RF_RX_IQ_BUF_WR_BYTE_OFFSET |
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| 143 | #define WL_BUF_REG_RF_RX_IQ_BUF_WR_BYTE_OFFSET_UPDATE XPAR_WARPLAB_BUFFERS_MEMMAP_RF_RX_IQ_BUF_WR_BYTE_OFFSET_UPDATE |
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| 144 | #define WL_BUF_REG_RF_RX_IQ_THRESHOLD XPAR_WARPLAB_BUFFERS_MEMMAP_RF_RX_IQ_THRESHOLD |
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| 145 | #define WL_BUF_REG_RF_RX_IQ_BUF_OCCUPANCY XPAR_WARPLAB_BUFFERS_MEMMAP_RF_RX_IQ_BUF_OCCUPANCY |
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| 146 | |
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| 147 | #define WL_BUF_REG_RF_TX_IQ_BUF_RD_BYTE_OFFSET XPAR_WARPLAB_BUFFERS_MEMMAP_RF_TX_IQ_BUF_RD_BYTE_OFFSET |
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| 148 | #define WL_BUF_REG_RF_TX_IQ_BUF_WR_BYTE_OFFSET XPAR_WARPLAB_BUFFERS_MEMMAP_RF_TX_IQ_BUF_WR_BYTE_OFFSET |
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| 149 | #define WL_BUF_REG_RF_TX_IQ_THRESHOLD XPAR_WARPLAB_BUFFERS_MEMMAP_RF_TX_IQ_THRESHOLD |
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| 150 | #define WL_BUF_REG_RF_TX_IQ_BUF_OCCUPANCY XPAR_WARPLAB_BUFFERS_MEMMAP_RF_TX_IQ_BUF_OCCUPANCY |
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| 151 | #define WL_BUF_REG_RF_TX_IQ_STATUS XPAR_WARPLAB_BUFFERS_MEMMAP_RF_TX_IQ_STATUS |
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| 152 | |
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| 153 | #define WL_BUF_REG_RF_ERROR_CLR XPAR_WARPLAB_BUFFERS_MEMMAP_RF_ERROR_CLR |
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| 154 | #define WL_BUF_REG_INT_STATUS XPAR_WARPLAB_BUFFERS_MEMMAP_INT_STATUS |
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| 155 | |
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| 156 | #define WL_BUF_REG_TXRX_COUNTER_RESET XPAR_WARPLAB_BUFFERS_MEMMAP_TXRX_COUNTER_RESET |
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| 157 | |
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| 158 | #define WL_BUF_REG_RFA_TX_COUNTER XPAR_WARPLAB_BUFFERS_MEMMAP_RFA_TX_COUNTER |
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| 159 | #define WL_BUF_REG_RFB_TX_COUNTER XPAR_WARPLAB_BUFFERS_MEMMAP_RFB_TX_COUNTER |
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| 160 | #define WL_BUF_REG_RFC_TX_COUNTER XPAR_WARPLAB_BUFFERS_MEMMAP_RFC_TX_COUNTER |
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| 161 | #define WL_BUF_REG_RFD_TX_COUNTER XPAR_WARPLAB_BUFFERS_MEMMAP_RFD_TX_COUNTER |
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| 162 | #define WL_BUF_REG_RFA_RX_COUNTER XPAR_WARPLAB_BUFFERS_MEMMAP_RFA_RX_COUNTER |
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| 163 | #define WL_BUF_REG_RFB_RX_COUNTER XPAR_WARPLAB_BUFFERS_MEMMAP_RFB_RX_COUNTER |
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| 164 | #define WL_BUF_REG_RFC_RX_COUNTER XPAR_WARPLAB_BUFFERS_MEMMAP_RFC_RX_COUNTER |
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| 165 | #define WL_BUF_REG_RFD_RX_COUNTER XPAR_WARPLAB_BUFFERS_MEMMAP_RFD_RX_COUNTER |
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| 166 | |
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| 167 | #define WL_LOAD_TIMER_64_LSB XPAR_WARPLAB_BUFFERS_MEMMAP_LOAD_TIMER_64_LSB |
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| 168 | #define WL_LOAD_TIMER_64_MSB XPAR_WARPLAB_BUFFERS_MEMMAP_LOAD_TIMER_64_MSB |
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| 169 | #define WL_TIMER_64_LSB XPAR_WARPLAB_BUFFERS_MEMMAP_TIMER_64_LSB |
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| 170 | #define WL_TIMER_64_MSB XPAR_WARPLAB_BUFFERS_MEMMAP_TIMER_64_MSB |
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| 171 | |
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| 172 | |
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| 173 | // Masks for CONFIG register |
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| 174 | #define WL_BUF_REG_CONFIG_CONT_TX 0x00000001 |
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| 175 | #define WL_BUF_REG_CONFIG_STOP_TX 0x00000002 |
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| 176 | #define WL_BUF_REG_CONFIG_PROC_ALL_TRIGGERS 0x00000004 |
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| 177 | #define WL_BUF_REG_CONFIG_AGC_IQ_SEL_RFA 0x00000010 |
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| 178 | #define WL_BUF_REG_CONFIG_AGC_IQ_SEL_RFB 0x00000020 |
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| 179 | #define WL_BUF_REG_CONFIG_AGC_IQ_SEL_RFC 0x00000040 |
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| 180 | #define WL_BUF_REG_CONFIG_AGC_IQ_SEL_RFD 0x00000080 |
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| 181 | #define WL_BUF_REG_CONFIG_RSSI_CLK_SEL 0x00000300 |
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| 182 | #define WL_BUF_REG_CONFIG_LOAD_TIMER_64 0x00001000 |
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| 183 | #define WL_BUF_REG_CONFIG_RX_WORD_ORDER 0x00010000 |
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| 184 | #define WL_BUF_REG_CONFIG_RX_BYTE_ORDER 0x00020000 |
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| 185 | #define WL_BUF_REG_CONFIG_TX_WORD_ORDER 0x00040000 |
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| 186 | #define WL_BUF_REG_CONFIG_TX_BYTE_ORDER 0x00080000 |
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| 187 | #define WL_BUF_REG_CONFIG_COUNTER_DATA_SEL 0x00100000 |
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| 188 | #define WL_BUF_REG_CONFIG_TX_RX_LOOPBACK_SEL 0x00200000 |
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| 189 | #define WL_BUF_REG_CONFIG_DEBUG_TX_OUTPUT_SEL 0x10000000 |
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| 190 | #define WL_BUF_REG_CONFIG_DEBUG_TX_BUF_SEL 0xE0000000 |
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| 191 | |
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| 192 | |
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| 193 | #define WL_BUF_REG_CONFIG_AGC_IQ_SEL_RF_ALL 0x000000F0 |
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| 194 | |
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| 195 | |
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| 196 | // Masks for Status register |
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| 197 | #define WL_BUF_REG_STATUS_TX_RUNNING 0x0000000F |
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| 198 | #define WL_BUF_REG_STATUS_TX_RUNNING_RF_A 0x00000001 |
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| 199 | #define WL_BUF_REG_STATUS_TX_RUNNING_RF_B 0x00000002 |
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| 200 | #define WL_BUF_REG_STATUS_TX_RUNNING_RF_C 0x00000004 |
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| 201 | #define WL_BUF_REG_STATUS_TX_RUNNING_RF_D 0x00000008 |
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| 202 | #define WL_BUF_REG_STATUS_RX_RUNNING 0x00000F00 |
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| 203 | #define WL_BUF_REG_STATUS_RX_RUNNING_RF_A 0x00000100 |
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| 204 | #define WL_BUF_REG_STATUS_RX_RUNNING_RF_B 0x00000200 |
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| 205 | #define WL_BUF_REG_STATUS_RX_RUNNING_RF_C 0x00000400 |
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| 206 | #define WL_BUF_REG_STATUS_RX_RUNNING_RF_D 0x00000800 |
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| 207 | #define WL_BUF_REG_STATUS_DRAM_INIT_DONE 0x00010000 |
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| 208 | |
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| 209 | |
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| 210 | // Mask for RF output selection register |
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| 211 | // NOTE: The defines for ANT_* in wl_interface.h should be used as values for the antenna arguments |
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| 212 | #define RFA_BUF_SEL 0x00000003 |
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| 213 | #define RFB_BUF_SEL 0x00000300 |
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| 214 | #define RFC_BUF_SEL 0x00030000 |
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| 215 | #define RFD_BUF_SEL 0x03000000 |
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| 216 | |
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| 217 | |
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| 218 | // Masks for RF enable registers |
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| 219 | #define RF_SEL_A 0x00000001 |
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| 220 | #define RF_SEL_B 0x00000002 |
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| 221 | #define RF_SEL_C 0x00000004 |
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| 222 | #define RF_SEL_D 0x00000008 |
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| 223 | |
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| 224 | #if WARPLAB_CONFIG_4RF |
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| 225 | #define NUM_RF_INF 4 |
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| 226 | #define RF_SEL_ALL 0x0000000F |
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| 227 | |
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| 228 | #else |
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| 229 | #define NUM_RF_INF 2 |
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| 230 | #define RF_SEL_ALL 0x00000003 |
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| 231 | #endif |
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| 232 | |
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| 233 | // Buffer state variables |
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| 234 | #define BUF_STATE_STANDBY 0 |
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| 235 | #define BUF_STATE_RX 1 |
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| 236 | #define BUF_STATE_TX 2 |
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| 237 | |
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| 238 | // Masks for interrupt status register |
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| 239 | #define WL_BUF_INT_ALL 0x00000003 |
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| 240 | #define RF_RX_IQ_RSSI_ERROR 0x01000000 |
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| 241 | #define RF_TX_IQ_ERROR 0x01000000 |
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| 242 | |
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| 243 | #define RF_RX_IQ_RSSI_ERROR_CLR 0x00000001 |
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| 244 | #define RF_TX_IQ_ERROR_CLR 0x00000100 |
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| 245 | |
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| 246 | |
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| 247 | // Masks for transfer calculations |
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| 248 | // Currently, these are defined as the BRAM size / 2 (ie we have a "ping" and "pong" buffer for storage) |
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| 249 | // |
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| 250 | // NOTE: We looked at |
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| 251 | // |
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| 252 | // |
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| 253 | #define WL_BUF_RX_TRANSFER_THRESHOLD_SAMPLES 0x00004000 |
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| 254 | #define WL_BUF_RX_TRANSFER_THRESHOLD_BYTES 0x00010000 |
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| 255 | #define WL_BUF_RX_TRANSFER_BYTE_ALIGNMENT_MASK 0xFFFF0000 |
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| 256 | |
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| 257 | #define WL_BUF_TX_TRANSFER_THRESHOLD_SAMPLES 0x00004000 |
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| 258 | #define WL_BUF_TX_TRANSFER_THRESHOLD_BYTES 0x00010000 |
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| 259 | #define WL_BUF_TX_TRANSFER_BYTE_ALIGNMENT_MASK 0xFFFF0000 |
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| 260 | |
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| 261 | |
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| 262 | // Masks for RX / TX sample length calculations |
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| 263 | // NOTE: This is based on the TX/RX_TRANSFER_THRESHOLD |
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| 264 | // |
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| 265 | #define WL_BUF_RX_SAMPLE_ALIGNMENT_MASK 0xFFFFC000 |
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| 266 | #define WL_BUF_TX_SAMPLE_ALIGNMENT_MASK 0xFFFFC000 |
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| 267 | |
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| 268 | |
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| 269 | // Defines for TX IQ status register |
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| 270 | #define WL_BUF_TX_IQ_STATUS_WR_DONE 0x00000001 |
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| 271 | |
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| 272 | // Defines for TX/RX counter reset |
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| 273 | #define WL_BUF_TXRX_COUNTER_RESET_TX_RFA 0x00000001 |
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| 274 | #define WL_BUF_TXRX_COUNTER_RESET_TX_RFB 0x00000002 |
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| 275 | #define WL_BUF_TXRX_COUNTER_RESET_TX_RFC 0x00000004 |
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| 276 | #define WL_BUF_TXRX_COUNTER_RESET_TX_RFD 0x00000008 |
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| 277 | #define WL_BUF_TXRX_COUNTER_RESET_RX_RFA 0x00000100 |
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| 278 | #define WL_BUF_TXRX_COUNTER_RESET_RX_RFB 0x00000200 |
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| 279 | #define WL_BUF_TXRX_COUNTER_RESET_RX_RFC 0x00000400 |
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| 280 | #define WL_BUF_TXRX_COUNTER_RESET_RX_RFD 0x00000800 |
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| 281 | |
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| 282 | #define WL_BUF_TXRX_COUNTER_RESET_TXRX_ALL 0x00000F0F |
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| 283 | |
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| 284 | |
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| 285 | |
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| 286 | // Baseband Macros |
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| 287 | #define wl_get_design_ver() XIo_In32(WL_BUF_REG_DESIGN_VER) |
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| 288 | |
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| 289 | #define wl_bb_get_buffer_sizes() XIo_In32(WL_BUF_REG_BUF_SIZES) |
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| 290 | #define wl_bb_get_rx_buffer_size() (XIo_In32(WL_BUF_REG_BUF_SIZES) & 0x0000FFFF) |
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| 291 | #define wl_bb_get_tx_buffer_size() ((XIo_In32(WL_BUF_REG_BUF_SIZES) & 0xFFFF0000) >> 16) |
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| 292 | |
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| 293 | #define wl_bb_get_raw_status() (XIo_In32(WL_BUF_REG_STATUS)) |
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| 294 | #define wl_bb_get_tx_status() (XIo_In32(WL_BUF_REG_STATUS) & WL_BUF_REG_STATUS_TX_RUNNING) |
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| 295 | #define wl_bb_get_rx_status() ((XIo_In32(WL_BUF_REG_STATUS) & WL_BUF_REG_STATUS_RX_RUNNING) >> 8) |
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| 296 | |
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| 297 | #define wl_bb_get_config() XIo_In32(WL_BUF_REG_CONFIG) |
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| 298 | #define wl_bb_set_config(mask) XIo_Out32(WL_BUF_REG_CONFIG, (XIo_In32(WL_BUF_REG_CONFIG) | (mask))) |
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| 299 | #define wl_bb_clear_config(mask) XIo_Out32(WL_BUF_REG_CONFIG, (XIo_In32(WL_BUF_REG_CONFIG) & ~(mask))) |
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| 300 | |
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| 301 | #define wl_bb_set_rssi_clk(value) XIo_Out32(WL_BUF_REG_CONFIG, ((XIo_In32(WL_BUF_REG_CONFIG) & ~WL_BUF_REG_CONFIG_RSSI_CLK_SEL) | ((value << 8) & WL_BUF_REG_CONFIG_RSSI_CLK_SEL))) |
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| 302 | |
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| 303 | #define wl_bb_get_tx_delay() XIo_In32(WL_BUF_REG_TX_DELAY) |
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| 304 | #define wl_bb_set_tx_delay(delay) XIo_Out32(WL_BUF_REG_TX_DELAY, delay) |
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| 305 | |
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| 306 | #define wl_bb_get_rx_length() XIo_In32(WL_BUF_REG_RX_LENGTH) |
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| 307 | #define wl_bb_set_rx_length(length) XIo_Out32(WL_BUF_REG_RX_LENGTH, length) |
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| 308 | |
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| 309 | #define wl_bb_get_tx_length() XIo_In32(WL_BUF_REG_TX_LENGTH) |
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| 310 | #define wl_bb_set_tx_length(length) XIo_Out32(WL_BUF_REG_TX_LENGTH, length) |
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| 311 | |
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| 312 | #define wl_bb_get_rf_buffer_sel() XIo_In32(WL_BUF_REG_RF_BUFFER_SEL) |
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| 313 | #define wl_bb_set_rf_buffer_sel_rfa(ant) XIo_Out32(WL_BUF_REG_RF_BUFFER_SEL, ((XIo_In32(WL_BUF_REG_RF_BUFFER_SEL) & ~RFA_BUF_SEL) | ((ant ) & RFA_BUF_SEL))) |
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| 314 | #define wl_bb_set_rf_buffer_sel_rfb(ant) XIo_Out32(WL_BUF_REG_RF_BUFFER_SEL, ((XIo_In32(WL_BUF_REG_RF_BUFFER_SEL) & ~RFB_BUF_SEL) | ((ant << 8) & RFB_BUF_SEL))) |
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| 315 | #define wl_bb_set_rf_buffer_sel_rfc(ant) XIo_Out32(WL_BUF_REG_RF_BUFFER_SEL, ((XIo_In32(WL_BUF_REG_RF_BUFFER_SEL) & ~RFC_BUF_SEL) | ((ant << 16) & RFC_BUF_SEL))) |
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| 316 | #define wl_bb_set_rf_buffer_sel_rfd(ant) XIo_Out32(WL_BUF_REG_RF_BUFFER_SEL, ((XIo_In32(WL_BUF_REG_RF_BUFFER_SEL) & ~RFD_BUF_SEL) | ((ant << 24) & RFD_BUF_SEL))) |
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| 317 | #define wl_bb_set_rf_buffer_sel(rfa, rfb, rfc, rfd) XIo_Out32(WL_BUF_REG_RF_BUFFER_SEL, (((rfa) & RFA_BUF_SEL) | ((rfb << 8) & RFB_BUF_SEL) | ((rfc << 16) & RFC_BUF_SEL) | ((rfd << 24) & RFD_BUF_SEL))) |
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| 318 | |
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| 319 | #define wl_bb_get_rx_buffer_en() XIo_In32(WL_BUF_REG_RX_BUF_EN) |
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| 320 | #define wl_bb_set_rx_buffer_en(rf_sel) XIo_Out32(WL_BUF_REG_RX_BUF_EN, (XIo_In32(WL_BUF_REG_RX_BUF_EN) | rf_sel)) |
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| 321 | #define wl_bb_clear_rx_buffer_en(rf_sel) XIo_Out32(WL_BUF_REG_RX_BUF_EN, (XIo_In32(WL_BUF_REG_RX_BUF_EN) & ~(rf_sel))) |
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| 322 | |
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| 323 | #define wl_bb_get_tx_buffer_en() XIo_In32(WL_BUF_REG_TX_BUF_EN) |
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| 324 | #define wl_bb_set_tx_buffer_en(rf_sel) XIo_Out32(WL_BUF_REG_TX_BUF_EN, (XIo_In32(WL_BUF_REG_TX_BUF_EN) | rf_sel)) |
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| 325 | #define wl_bb_clear_tx_buffer_en(rf_sel) XIo_Out32(WL_BUF_REG_TX_BUF_EN, (XIo_In32(WL_BUF_REG_TX_BUF_EN) & ~(rf_sel))) |
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| 326 | |
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| 327 | #define wl_bb_get_agc_done_addr() XIo_In32(WL_BUF_REG_AGC_DONE_ADDR) |
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| 328 | #define wl_bb_get_rfa_agc_done_rssi() (XIo_In32(WL_BUF_REG_RF_AB_AGC_DONE_RSSI) & 0x000003FF) |
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| 329 | #define wl_bb_get_rfb_agc_done_rssi() ((XIo_In32(WL_BUF_REG_RF_AB_AGC_DONE_RSSI) & 0x03FF0000) >> 16) |
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| 330 | #define wl_bb_get_rfc_agc_done_rssi() (XIo_In32(WL_BUF_REG_RF_CD_AGC_DONE_RSSI) & 0x000003FF) |
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| 331 | #define wl_bb_get_rfd_agc_done_rssi() ((XIo_In32(WL_BUF_REG_RF_CD_AGC_DONE_RSSI) & 0x03FF0000) >> 16) |
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| 332 | |
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| 333 | #define wl_bb_get_rf_rx_iq_buf_rd_byte_offset() XIo_In32(WL_BUF_REG_RF_RX_IQ_BUF_RD_BYTE_OFFSET) |
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| 334 | #define wl_bb_set_rf_rx_iq_buf_rd_byte_offset(offset) XIo_Out32(WL_BUF_REG_RF_RX_IQ_BUF_RD_BYTE_OFFSET, offset) |
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| 335 | |
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| 336 | #define wl_bb_get_rf_rx_iq_buf_wr_byte_offset() XIo_In32(WL_BUF_REG_RF_RX_IQ_BUF_WR_BYTE_OFFSET_UPDATE) |
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| 337 | #define wl_bb_set_rf_rx_iq_buf_wr_byte_offset(offset) XIo_Out32(WL_BUF_REG_RF_RX_IQ_BUF_WR_BYTE_OFFSET, offset) |
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| 338 | |
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| 339 | #define wl_bb_get_rf_rx_iq_threshold() XIo_In32(WL_BUF_REG_RF_RX_IQ_THRESHOLD) |
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| 340 | #define wl_bb_set_rf_rx_iq_threshold(num_samples) XIo_Out32(WL_BUF_REG_RF_RX_IQ_THRESHOLD, num_samples) |
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| 341 | |
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| 342 | #define wl_bb_get_rf_rx_iq_buf_occupancy() XIo_In32(WL_BUF_REG_RF_RX_IQ_BUF_OCCUPANCY) |
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| 343 | |
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| 344 | #define wl_bb_get_rf_tx_iq_buf_rd_byte_offset() XIo_In32(WL_BUF_REG_RF_TX_IQ_BUF_RD_BYTE_OFFSET) |
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| 345 | |
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| 346 | #define wl_bb_get_rf_tx_iq_buf_wr_byte_offset() XIo_In32(WL_BUF_REG_RF_TX_IQ_BUF_WR_BYTE_OFFSET) |
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| 347 | #define wl_bb_set_rf_tx_iq_buf_wr_byte_offset(offset) XIo_Out32(WL_BUF_REG_RF_TX_IQ_BUF_WR_BYTE_OFFSET, offset) |
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| 348 | |
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| 349 | #define wl_bb_get_rf_tx_iq_threshold() XIo_In32(WL_BUF_REG_RF_TX_IQ_THRESHOLD) |
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| 350 | #define wl_bb_set_rf_tx_iq_threshold(num_samples) XIo_Out32(WL_BUF_REG_RF_TX_IQ_THRESHOLD, num_samples) |
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| 351 | |
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| 352 | #define wl_bb_get_rf_tx_iq_buf_occupancy() XIo_In32(WL_BUF_REG_RF_TX_IQ_BUF_OCCUPANCY) |
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| 353 | #define wl_bb_get_rf_tx_iq_status() XIo_In32(WL_BUF_REG_RF_TX_IQ_STATUS) |
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| 354 | |
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| 355 | #define wl_bb_get_rf_rx_iq_rssi_error() ((XIo_In32(WL_BUF_REG_INT_STATUS) & RF_RX_IQ_RSSI_ERROR) >> 24) |
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| 356 | #define wl_bb_clear_rf_rx_iq_rssi_error() XIo_Out32(WL_BUF_REG_RF_ERROR_CLR, RF_RX_IQ_RSSI_ERROR_CLR) |
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| 357 | |
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| 358 | #define wl_bb_get_rf_tx_iq_error() ((XIo_In32(WL_BUF_REG_INT_STATUS) & RF_TX_IQ_ERROR) >> 25) |
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| 359 | #define wl_bb_clear_rf_tx_iq_error() XIo_Out32(WL_BUF_REG_RF_ERROR_CLR, RF_TX_IQ_ERROR_CLR) |
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| 360 | |
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| 361 | #define wl_bb_get_int_status() (XIo_In32(WL_BUF_REG_INT_STATUS) & WL_BUF_INT_ALL) |
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| 362 | |
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| 363 | #define wl_bb_get_rfa_tx_count() XIo_In32(WL_BUF_REG_RFA_TX_COUNTER) |
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| 364 | #define wl_bb_get_rfb_tx_count() XIo_In32(WL_BUF_REG_RFB_TX_COUNTER) |
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| 365 | #define wl_bb_get_rfc_tx_count() XIo_In32(WL_BUF_REG_RFC_TX_COUNTER) |
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| 366 | #define wl_bb_get_rfd_tx_count() XIo_In32(WL_BUF_REG_RFD_TX_COUNTER) |
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| 367 | #define wl_bb_get_rfa_rx_count() XIo_In32(WL_BUF_REG_RFA_RX_COUNTER) |
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| 368 | #define wl_bb_get_rfb_rx_count() XIo_In32(WL_BUF_REG_RFB_RX_COUNTER) |
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| 369 | #define wl_bb_get_rfc_rx_count() XIo_In32(WL_BUF_REG_RFC_RX_COUNTER) |
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| 370 | #define wl_bb_get_rfd_rx_count() XIo_In32(WL_BUF_REG_RFD_RX_COUNTER) |
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| 371 | |
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| 372 | #define wl_bb_set_txrx_counter_reset(rf) XIo_Out32(WL_BUF_REG_TXRX_COUNTER_RESET, (rf & WL_BUF_TXRX_COUNTER_RESET_TXRX_ALL)) |
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| 373 | #define wl_bb_clear_txrx_counter_reset() XIo_Out32(WL_BUF_REG_TXRX_COUNTER_RESET, 0) |
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| 374 | |
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| 375 | |
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| 376 | |
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| 377 | // Macros for other values from the buffers core |
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| 378 | #define wl_get_dram_init_done() ((XIo_In32(WL_BUF_REG_STATUS) & WL_BUF_REG_STATUS_DRAM_INIT_DONE) >> 16) |
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| 379 | |
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| 380 | #define wl_get_timer_64_MSB() XIo_In32(WL_TIMER_64_MSB) |
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| 381 | #define wl_get_timer_64_LSB() XIo_In32(WL_TIMER_64_LSB) |
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| 382 | |
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| 383 | |
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| 384 | |
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| 385 | // **************************************************************************** |
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| 386 | // AGC Defines |
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| 387 | // |
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| 388 | #define AGC_A 0x10000000 |
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| 389 | #define AGC_B 0x20000000 |
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| 390 | #define AGC_C 0x40000000 |
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| 391 | #define AGC_D 0x80000000 |
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| 392 | |
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| 393 | |
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| 394 | // AGC Register definitions |
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| 395 | #define WL_AGC_REG_RESET XPAR_WARPLAB_AGC_MEMMAP_RESET |
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| 396 | #define WL_AGC_REG_TIMING_AGC XPAR_WARPLAB_AGC_MEMMAP_TIMING_AGC |
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| 397 | #define WL_AGC_REG_TIMING_DCO XPAR_WARPLAB_AGC_MEMMAP_TIMING_DCO |
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| 398 | #define WL_AGC_REG_TARGET XPAR_WARPLAB_AGC_MEMMAP_TARGET |
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| 399 | #define WL_AGC_REG_CONFIG XPAR_WARPLAB_AGC_MEMMAP_CONFIG |
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| 400 | #define WL_AGC_REG_RSSI_PWR_CALIB XPAR_WARPLAB_AGC_MEMMAP_RSSI_PWR_CALIB |
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| 401 | #define WL_AGC_REG_IIR_COEF_B0 XPAR_WARPLAB_AGC_MEMMAP_IIR_COEF_B0 |
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| 402 | #define WL_AGC_REG_IIR_COEF_A1 XPAR_WARPLAB_AGC_MEMMAP_IIR_COEF_A1 |
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| 403 | #define WL_AGC_TIMING_RESET XPAR_WARPLAB_AGC_MEMMAP_TIMING_RESET |
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| 404 | #define WL_AGC_SW_RESET XPAR_WARPLAB_AGC_MEMMAP_SW_RESET |
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| 405 | #define WL_AGC_RESET_MODE XPAR_WARPLAB_AGC_MEMMAP_RESET_MODE |
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| 406 | #define WL_AGC_RX_LENGTH XPAR_WARPLAB_AGC_MEMMAP_RX_LENGTH |
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| 407 | #define WL_AGC_OVERRIDE XPAR_WARPLAB_AGC_MEMMAP_AGC_OVERRIDE |
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| 408 | |
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| 409 | #define WL_AGC_GAINS XPAR_WARPLAB_BUFFERS_MEMMAP_AGC_GAINS |
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| 410 | |
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| 411 | |
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| 412 | #define WL_AGC_RESET_MODE_RESET_PER_RX_MASK 0x00000001 |
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| 413 | |
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| 414 | #define WL_AGC_RX_LENGTH_VALUE_MASK 0xFFFFFFFF |
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| 415 | |
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| 416 | |
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| 417 | // AGC gains reg: |
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| 418 | // [ 4: 0]: RF A BBG |
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| 419 | // [ 6: 5]: RF A RFG |
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| 420 | // [7]: RF A RXHP |
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| 421 | // [12: 8]: RF B BBG |
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| 422 | // [14:13]: RF B RFG |
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| 423 | // [15]: RF B RXHP |
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| 424 | // [20:16]: RF C BBG |
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| 425 | // [22:21]: RF C RFG |
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| 426 | // [23]: RF C RXHP |
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| 427 | // [28:24]: RF D BBG |
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| 428 | // [30:29]: RF D RFG |
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| 429 | // [31]: RF D RXHP |
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| 430 | // |
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| 431 | #define wl_get_agc_gains_raw() XIo_In32(WL_AGC_GAINS) |
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| 432 | |
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| 433 | #define wl_get_agc_RFG(ant) (((ant==0) ? (Xil_In32(WL_AGC_GAINS) >> 5) : \ |
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| 434 | (ant==1) ? (Xil_In32(WL_AGC_GAINS) >> 13) : \ |
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| 435 | (ant==2) ? (Xil_In32(WL_AGC_GAINS) >> 21) : \ |
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| 436 | (Xil_In32(WL_AGC_GAINS) >> 29)) & 0x3) |
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| 437 | |
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| 438 | #define wl_get_agc_BBG(ant) (((ant==0) ? (Xil_In32(WL_AGC_GAINS) >> 0) : \ |
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| 439 | (ant==1) ? (Xil_In32(WL_AGC_GAINS) >> 8) : \ |
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| 440 | (ant==2) ? (Xil_In32(WL_AGC_GAINS) >> 16) : \ |
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| 441 | (Xil_In32(WL_AGC_GAINS) >> 24)) & 0x1F) |
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| 442 | |
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| 443 | #define wl_get_agc_RXHP(ant) (((ant==0) ? (Xil_In32(WL_AGC_GAINS) >> 7) : \ |
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| 444 | (ant==1) ? (Xil_In32(WL_AGC_GAINS) >> 15) : \ |
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| 445 | (ant==2) ? (Xil_In32(WL_AGC_GAINS) >> 23) : \ |
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| 446 | (Xil_In32(WL_AGC_GAINS) >> 31)) & 0x1) |
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| 447 | |
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| 448 | |
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| 449 | // AGC Macros |
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| 450 | #define wl_agc_get_reset() XIo_In32(WL_AGC_REG_RESET) |
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| 451 | #define wl_agc_set_reset(data) XIo_Out32(WL_AGC_REG_RESET, (data & 0x1)) |
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| 452 | |
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| 453 | #define wl_agc_get_AGC_timing() XIo_In32(WL_AGC_REG_TIMING_AGC) |
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| 454 | #define wl_agc_set_AGC_timing(capt_rssi_1, capt_rssi_2, capt_v_db, agc_done) \ |
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| 455 | Xil_Out32(WL_AGC_REG_TIMING_AGC, ((capt_rssi_1 & 0xFF) | ((capt_rssi_2 & 0xFF) << 8) | \ |
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| 456 | ((capt_v_db & 0xFF) << 16) | ((agc_done & 0xFF) << 24))) |
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| 457 | |
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| 458 | #define wl_agc_get_DCO_timing() XIo_In32(WL_AGC_REG_TIMING_DCO) |
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| 459 | #define wl_agc_set_DCO_timing(start_dco, en_iir_filt) \ |
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| 460 | Xil_Out32(WL_AGC_REG_TIMING_DCO, ((start_dco & 0xFF) | ((en_iir_filt & 0xFF) << 8))) |
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| 461 | |
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| 462 | #define wl_agc_get_target() XIo_In32(WL_AGC_REG_TARGET) |
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| 463 | #define wl_agc_set_target(target_pwr) Xil_Out32(WL_AGC_REG_TARGET, (target_pwr & 0x3F)) |
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| 464 | |
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| 465 | #define wl_agc_get_config() XIo_In32(WL_AGC_REG_CONFIG) |
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| 466 | #define wl_agc_set_config_all(thresh32, thresh21, avg_len, v_db_adj, init_g_bb) \ |
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| 467 | Xil_Out32(WL_AGC_REG_CONFIG, (((thresh32 & 0xFF) << 0) | \ |
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| 468 | ((thresh21 & 0xFF) << 8) | \ |
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| 469 | ((avg_len & 0x03) << 16) | \ |
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| 470 | ((v_db_adj & 0x3F) << 18) | \ |
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| 471 | ((init_g_bb & 0x1F) << 24))) |
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| 472 | |
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| 473 | #define wl_agc_set_config(avg_len, v_db_adj, init_g_bb) \ |
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| 474 | Xil_Out32(WL_AGC_REG_CONFIG, ((XIo_In32(WL_AGC_REG_CONFIG) & 0x0000FFFF) | \ |
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| 475 | ((avg_len & 0x03) << 16) | \ |
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| 476 | ((v_db_adj & 0x3F) << 18) | \ |
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| 477 | ((init_g_bb & 0x1F) << 24))) |
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| 478 | |
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| 479 | #define wl_agc_set_config_thresh(thresh32, thresh21) \ |
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| 480 | Xil_Out32(WL_AGC_REG_CONFIG, ((XIo_In32(WL_AGC_REG_CONFIG) & 0xFFFF0000) | \ |
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| 481 | ((thresh32 & 0xFF) << 0) | \ |
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| 482 | ((thresh21 & 0xFF) << 8))) |
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| 483 | |
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| 484 | #define wl_agc_get_RSSI_pwr_calib() XIo_In32(WL_AGC_REG_RSSI_PWR_CALIB) |
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| 485 | #define wl_agc_set_RSSI_pwr_calib(g3, g2, g1) Xil_Out32(WL_AGC_REG_RSSI_PWR_CALIB, ((g3 & 0xFF) | ((g2 & 0xFF)<<8) | ((g1 & 0xFF)<<16))) |
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| 486 | |
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| 487 | #define wl_agc_get_reset_timing() XIo_In32(WL_AGC_TIMING_RESET) |
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| 488 | #define wl_agc_set_reset_timing(rxhp, g_rf, g_bb) Xil_Out32(WL_AGC_TIMING_RESET, ((rxhp & 0xFF) | ((g_rf & 0xFF)<<8) | ( (g_bb & 0xFF)<<16))) |
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| 489 | |
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| 490 | #define wl_agc_get_rx_length() XIo_In32(WL_AGC_RX_LENGTH) |
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| 491 | #define wl_agc_set_rx_length(data) XIo_Out32(WL_AGC_RX_LENGTH, data) |
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| 492 | |
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| 493 | #define wl_agc_get_reset_mode() XIo_In32(WL_AGC_RESET_MODE) |
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| 494 | #define wl_agc_enable_reset_per_rx() XIo_Out32(WL_AGC_RESET_MODE, (XIo_In32(WL_AGC_RESET_MODE) | WL_AGC_RESET_MODE_RESET_PER_RX_MASK)) |
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| 495 | #define wl_agc_disable_reset_per_rx() XIo_Out32(WL_AGC_RESET_MODE, (XIo_In32(WL_AGC_RESET_MODE) & ~WL_AGC_RESET_MODE_RESET_PER_RX_MASK)) |
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| 496 | |
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| 497 | #define wl_agc_get_override() XIo_In32(WL_AGC_OVERRIDE) |
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| 498 | #define wl_agc_set_override(data) Xil_Out32(WL_AGC_OVERRIDE, data) |
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| 499 | |
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| 500 | #define wl_agc_get_iir_coef_a1() XIo_In32(WL_AGC_REG_IIR_COEF_A1) |
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| 501 | #define wl_agc_set_iir_coef_a1(data) Xil_Out32(WL_AGC_REG_IIR_COEF_A1, data) |
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| 502 | |
|---|
| 503 | #define wl_agc_get_iir_coef_b0() XIo_In32(WL_AGC_REG_IIR_COEF_B0) |
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| 504 | #define wl_agc_set_iir_coef_b0(data) Xil_Out32(WL_AGC_REG_IIR_COEF_B0, data) |
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| 505 | |
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| 506 | |
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| 507 | |
|---|
| 508 | /*********************** Global Structure Definitions ************************/ |
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| 509 | |
|---|
| 510 | typedef u32 wl_samp; |
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| 511 | |
|---|
| 512 | // Common sample header flags between Read IQ / Write IQ |
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| 513 | #define SAMPLE_HDR_FLAG_IQ_ERROR 0x01 |
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| 514 | #define SAMPLE_HDR_FLAG_IQ_NOT_READY 0x02 |
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| 515 | |
|---|
| 516 | |
|---|
| 517 | // Write IQ sample header flags |
|---|
| 518 | #define SAMPLE_HDR_FLAG_CHKSUM_RESET 0x10 |
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| 519 | #define SAMPLE_HDR_FLAG_LAST_WRITE 0x20 |
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| 520 | |
|---|
| 521 | |
|---|
| 522 | // Sample header |
|---|
| 523 | typedef struct{ |
|---|
| 524 | u16 buff_sel; |
|---|
| 525 | u8 flags; |
|---|
| 526 | u8 sample_iq_id; |
|---|
| 527 | u32 start_samp; |
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| 528 | u32 num_samp; |
|---|
| 529 | } wl_bb_samp_hdr; |
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| 530 | |
|---|
| 531 | |
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| 532 | |
|---|
| 533 | |
|---|
| 534 | /******************************** Functions **********************************/ |
|---|
| 535 | |
|---|
| 536 | int baseband_init(u8 dram_present, u8 configure_buffers); |
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| 537 | int baseband_process_cmd(int socket_index, void * from, wl_cmd_resp * command, wl_cmd_resp * response); |
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| 538 | |
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| 539 | u32 wl_bb_get_supported_tx_length(); |
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| 540 | u32 wl_bb_get_supported_rx_length(); |
|---|
| 541 | |
|---|
| 542 | u32 baseband_get_checksum(); |
|---|
| 543 | u32 baseband_update_checksum(u16 newdata, u8 reset ); |
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| 544 | |
|---|
| 545 | // AGC Functions |
|---|
| 546 | void warplab_agc_init(); |
|---|
| 547 | void warplab_agc_enable_DCO(u32 enable); |
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| 548 | void warplab_agc_reset(); |
|---|
| 549 | inline void warplab_agc_setNoiseEstimate(short int noiseEst); |
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| 550 | void warplab_set_agc_rx_length(u32 num_samples); |
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| 551 | |
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| 552 | |
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| 553 | |
|---|
| 554 | /**********************************************************************************************************************/ |
|---|
| 555 | /** |
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| 556 | * @brief WARP v3 Specific Functions |
|---|
| 557 | * |
|---|
| 558 | **********************************************************************************************************************/ |
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| 559 | |
|---|
| 560 | #ifdef WARP_HW_VER_v3 |
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| 561 | |
|---|
| 562 | /***************************** Include Files *********************************/ |
|---|
| 563 | #include <xintc.h> |
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| 564 | |
|---|
| 565 | /*************************** Constant Definitions ****************************/ |
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| 566 | |
|---|
| 567 | // ********************************************************************** |
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| 568 | // Memory defines for DDR sample buffers |
|---|
| 569 | // |
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| 570 | // Currently, the RX buffer must be 8x the size of the RSSI buffer. In order to |
|---|
| 571 | // minimize the unused space, we are allocating the buffers in the ratio: |
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| 572 | // |
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| 573 | // 2RF / 4RF (2GB DDR) |
|---|
| 574 | // RX - 8x --> 512 / 256 MB |
|---|
| 575 | // TX - 7x --> 448 / 224 MB |
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| 576 | // RSSI - 1x --> 64 / 32 MB |
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| 577 | // |
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| 578 | // NOTE: Buffers must be allocated on temporary buffer size boundaries (ie WARPLAB_IQ_TX_BUF_SIZE) |
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| 579 | // NOTE: These values will not be use if DRAM is not available. Instead, the buffers will default |
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| 580 | // back to WARPLab 7.4.0 sizes |
|---|
| 581 | // |
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| 582 | |
|---|
| 583 | #if 1 |
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| 584 | |
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| 585 | // To make it easier to define the buffers, we should allocate the space for the buffers in chunks |
|---|
| 586 | // For 4 RF interfaces: 32 MB / increment (ie 2^23 samples) |
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| 587 | // For 2 RF interfaces: 64 MB / increment (ie 2^24 samples) |
|---|
| 588 | // |
|---|
| 589 | #if WARPLAB_CONFIG_4RF |
|---|
| 590 | #define WL_BUF_DEFAULT_CHUNK_SIZE (DDR_SIZE / 64) |
|---|
| 591 | #else |
|---|
| 592 | #define WL_BUF_DEFAULT_CHUNK_SIZE (DDR_SIZE / 32) |
|---|
| 593 | #endif |
|---|
| 594 | |
|---|
| 595 | // Define the maximum number of sample supported base on the "chunk" size |
|---|
| 596 | #define WL_BUF_DEFAULT_RX_MAX_SAMPLES (((8 * WL_BUF_DEFAULT_CHUNK_SIZE) >> 2) - 1) |
|---|
| 597 | #define WL_BUF_DEFAULT_TX_MAX_SAMPLES (((7 * WL_BUF_DEFAULT_CHUNK_SIZE) >> 2) - 1) |
|---|
| 598 | |
|---|
| 599 | // Define RF A Buffer addresses / sizes |
|---|
| 600 | #define WL_BUF_DEFAULT_IQ_RX_BUF_A_ADDR (DRAM_BASEADDR + ( 0 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
|---|
| 601 | #define WL_BUF_DEFAULT_IQ_TX_BUF_A_ADDR (DRAM_BASEADDR + ( 8 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
|---|
| 602 | #define WL_BUF_DEFAULT_RSSI_BUF_A_ADDR (DRAM_BASEADDR + (15 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
|---|
| 603 | #define WL_BUF_DEFAULT_IQ_RX_BUF_A_SIZE (8 * WL_BUF_DEFAULT_CHUNK_SIZE) |
|---|
| 604 | #define WL_BUF_DEFAULT_IQ_TX_BUF_A_SIZE (7 * WL_BUF_DEFAULT_CHUNK_SIZE) |
|---|
| 605 | #define WL_BUF_DEFAULT_RSSI_BUF_A_SIZE (1 * WL_BUF_DEFAULT_CHUNK_SIZE) |
|---|
| 606 | |
|---|
| 607 | // Define RF B Buffer addresses / sizes |
|---|
| 608 | #define WL_BUF_DEFAULT_IQ_RX_BUF_B_ADDR (DRAM_BASEADDR + (16 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
|---|
| 609 | #define WL_BUF_DEFAULT_IQ_TX_BUF_B_ADDR (DRAM_BASEADDR + (24 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
|---|
| 610 | #define WL_BUF_DEFAULT_RSSI_BUF_B_ADDR (DRAM_BASEADDR + (31 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
|---|
| 611 | #define WL_BUF_DEFAULT_IQ_RX_BUF_B_SIZE (8 * WL_BUF_DEFAULT_CHUNK_SIZE) |
|---|
| 612 | #define WL_BUF_DEFAULT_IQ_TX_BUF_B_SIZE (7 * WL_BUF_DEFAULT_CHUNK_SIZE) |
|---|
| 613 | #define WL_BUF_DEFAULT_RSSI_BUF_B_SIZE (1 * WL_BUF_DEFAULT_CHUNK_SIZE) |
|---|
| 614 | |
|---|
| 615 | #if WARPLAB_CONFIG_4RF |
|---|
| 616 | // Define RF C Buffer addresses / sizes |
|---|
| 617 | #define WL_BUF_DEFAULT_IQ_RX_BUF_C_ADDR (DRAM_BASEADDR + (32 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
|---|
| 618 | #define WL_BUF_DEFAULT_IQ_TX_BUF_C_ADDR (DRAM_BASEADDR + (40 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
|---|
| 619 | #define WL_BUF_DEFAULT_RSSI_BUF_C_ADDR (DRAM_BASEADDR + (47 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
|---|
| 620 | #define WL_BUF_DEFAULT_IQ_RX_BUF_C_SIZE (8 * WL_BUF_DEFAULT_CHUNK_SIZE) |
|---|
| 621 | #define WL_BUF_DEFAULT_IQ_TX_BUF_C_SIZE (7 * WL_BUF_DEFAULT_CHUNK_SIZE) |
|---|
| 622 | #define WL_BUF_DEFAULT_RSSI_BUF_C_SIZE (1 * WL_BUF_DEFAULT_CHUNK_SIZE) |
|---|
| 623 | |
|---|
| 624 | // Define RF D Buffer addresses / sizes |
|---|
| 625 | #define WL_BUF_DEFAULT_IQ_RX_BUF_D_ADDR (DRAM_BASEADDR + (48 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
|---|
| 626 | #define WL_BUF_DEFAULT_IQ_TX_BUF_D_ADDR (DRAM_BASEADDR + (56 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
|---|
| 627 | #define WL_BUF_DEFAULT_RSSI_BUF_D_ADDR (DRAM_BASEADDR + (63 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
|---|
| 628 | #define WL_BUF_DEFAULT_IQ_RX_BUF_D_SIZE (8 * WL_BUF_DEFAULT_CHUNK_SIZE) |
|---|
| 629 | #define WL_BUF_DEFAULT_IQ_TX_BUF_D_SIZE (7 * WL_BUF_DEFAULT_CHUNK_SIZE) |
|---|
| 630 | #define WL_BUF_DEFAULT_RSSI_BUF_D_SIZE (1 * WL_BUF_DEFAULT_CHUNK_SIZE) |
|---|
| 631 | #else |
|---|
| 632 | #if WL_BUF_DEBUG_4RF_ON_2RF |
|---|
| 633 | // In the case we want to debug the 4RF buffers on a 2RF design, |
|---|
| 634 | // map RFC -> RFA and RFD -> RFB |
|---|
| 635 | |
|---|
| 636 | // Define RF C Buffer addresses / sizes |
|---|
| 637 | #define WL_BUF_DEFAULT_IQ_RX_BUF_C_ADDR (DRAM_BASEADDR + ( 0 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
|---|
| 638 | #define WL_BUF_DEFAULT_IQ_TX_BUF_C_ADDR (DRAM_BASEADDR + ( 8 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
|---|
| 639 | #define WL_BUF_DEFAULT_RSSI_BUF_C_ADDR (DRAM_BASEADDR + (15 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
|---|
| 640 | #define WL_BUF_DEFAULT_IQ_RX_BUF_C_SIZE (8 * WL_BUF_DEFAULT_CHUNK_SIZE) |
|---|
| 641 | #define WL_BUF_DEFAULT_IQ_TX_BUF_C_SIZE (7 * WL_BUF_DEFAULT_CHUNK_SIZE) |
|---|
| 642 | #define WL_BUF_DEFAULT_RSSI_BUF_C_SIZE (1 * WL_BUF_DEFAULT_CHUNK_SIZE) |
|---|
| 643 | |
|---|
| 644 | // Define RF D Buffer addresses / sizes |
|---|
| 645 | #define WL_BUF_DEFAULT_IQ_RX_BUF_D_ADDR (DRAM_BASEADDR + (16 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
|---|
| 646 | #define WL_BUF_DEFAULT_IQ_TX_BUF_D_ADDR (DRAM_BASEADDR + (24 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
|---|
| 647 | #define WL_BUF_DEFAULT_RSSI_BUF_D_ADDR (DRAM_BASEADDR + (31 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
|---|
| 648 | #define WL_BUF_DEFAULT_IQ_RX_BUF_D_SIZE (8 * WL_BUF_DEFAULT_CHUNK_SIZE) |
|---|
| 649 | #define WL_BUF_DEFAULT_IQ_TX_BUF_D_SIZE (7 * WL_BUF_DEFAULT_CHUNK_SIZE) |
|---|
| 650 | #define WL_BUF_DEFAULT_RSSI_BUF_D_SIZE (1 * WL_BUF_DEFAULT_CHUNK_SIZE) |
|---|
| 651 | #else |
|---|
| 652 | // Define RF C Buffer addresses / sizes |
|---|
| 653 | #define WL_BUF_DEFAULT_IQ_RX_BUF_C_ADDR 0 |
|---|
| 654 | #define WL_BUF_DEFAULT_IQ_TX_BUF_C_ADDR 0 |
|---|
| 655 | #define WL_BUF_DEFAULT_RSSI_BUF_C_ADDR 0 |
|---|
| 656 | #define WL_BUF_DEFAULT_IQ_RX_BUF_C_SIZE 0 |
|---|
| 657 | #define WL_BUF_DEFAULT_IQ_TX_BUF_C_SIZE 0 |
|---|
| 658 | #define WL_BUF_DEFAULT_RSSI_BUF_C_SIZE 0 |
|---|
| 659 | |
|---|
| 660 | // Define RF D Buffer addresses / sizes |
|---|
| 661 | #define WL_BUF_DEFAULT_IQ_RX_BUF_D_ADDR 0 |
|---|
| 662 | #define WL_BUF_DEFAULT_IQ_TX_BUF_D_ADDR 0 |
|---|
| 663 | #define WL_BUF_DEFAULT_RSSI_BUF_D_ADDR 0 |
|---|
| 664 | #define WL_BUF_DEFAULT_IQ_RX_BUF_D_SIZE 0 |
|---|
| 665 | #define WL_BUF_DEFAULT_IQ_TX_BUF_D_SIZE 0 |
|---|
| 666 | #define WL_BUF_DEFAULT_RSSI_BUF_D_SIZE 0 |
|---|
| 667 | #endif |
|---|
| 668 | #endif |
|---|
| 669 | |
|---|
| 670 | #endif // #if 1 |
|---|
| 671 | |
|---|
| 672 | |
|---|
| 673 | // ********************************************************************** |
|---|
| 674 | // Alternate Example Memory defines for DDR sample buffers |
|---|
| 675 | // |
|---|
| 676 | // Currently, the RX buffer must be 8x the size of the RSSI buffer. In order to |
|---|
| 677 | // minimize the unused space, we are allocating the buffers in the ratio: |
|---|
| 678 | // |
|---|
| 679 | // (2GB DDR) Max Tx / Max RX / 1RF / 2RF / 4RF |
|---|
| 680 | // RX - 8x --> 128 kB / 1820 MB / 1024 MB / 512 MB / 256 MB |
|---|
| 681 | // TX - 7x --> 2048 MB / 128 kB / 896 MB / 448 MB / 224 MB |
|---|
| 682 | // RSSI - 1x --> 16 kB / 228 MB / 128 MB / 64 MB / 32 MB |
|---|
| 683 | // |
|---|
| 684 | // NOTE: Buffers must be allocated on temporary buffer size boundaries (ie WARPLAB_IQ_TX_BUF_SIZE) |
|---|
| 685 | // NOTE: These values will not be use if DRAM is not available. Instead, the buffers will default |
|---|
| 686 | // back to WARPLab 7.4.0 sizes |
|---|
| 687 | // |
|---|
| 688 | |
|---|
| 689 | #if 0 |
|---|
| 690 | |
|---|
| 691 | //------------------------------------------------------------------------ |
|---|
| 692 | // 1RF Case |
|---|
| 693 | //------------------------------------------------------------------------ |
|---|
| 694 | |
|---|
| 695 | #define WL_BUF_DEFAULT_CHUNK_SIZE (DDR_SIZE / 16) |
|---|
| 696 | |
|---|
| 697 | // Define the maximum number of sample supported base on the "chunk" size |
|---|
| 698 | #define WL_BUF_DEFAULT_RX_MAX_SAMPLES (((8 * WL_BUF_DEFAULT_CHUNK_SIZE) >> 2) - 1) |
|---|
| 699 | #define WL_BUF_DEFAULT_TX_MAX_SAMPLES (((7 * WL_BUF_DEFAULT_CHUNK_SIZE) >> 2) - 1) |
|---|
| 700 | |
|---|
| 701 | // Define RF A Buffer addresses / sizes |
|---|
| 702 | #define WL_BUF_DEFAULT_IQ_RX_BUF_A_ADDR (DRAM_BASEADDR + ( 0 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
|---|
| 703 | #define WL_BUF_DEFAULT_IQ_TX_BUF_A_ADDR (DRAM_BASEADDR + ( 8 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
|---|
| 704 | #define WL_BUF_DEFAULT_RSSI_BUF_A_ADDR (DRAM_BASEADDR + (15 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
|---|
| 705 | #define WL_BUF_DEFAULT_IQ_RX_BUF_A_SIZE (8 * WL_BUF_DEFAULT_CHUNK_SIZE) |
|---|
| 706 | #define WL_BUF_DEFAULT_IQ_TX_BUF_A_SIZE (7 * WL_BUF_DEFAULT_CHUNK_SIZE) |
|---|
| 707 | #define WL_BUF_DEFAULT_RSSI_BUF_A_SIZE (1 * WL_BUF_DEFAULT_CHUNK_SIZE) |
|---|
| 708 | |
|---|
| 709 | |
|---|
| 710 | #if WL_BUF_DEBUG_4RF_ON_2RF |
|---|
| 711 | // In the case we want to debug the 4RF buffers on a 1RF design, |
|---|
| 712 | // map RFB -> RFA, RFC -> RFA and RFD -> RFA |
|---|
| 713 | |
|---|
| 714 | // Define RF B Buffer addresses / sizes |
|---|
| 715 | #define WL_BUF_DEFAULT_IQ_RX_BUF_B_ADDR WL_BUF_DEFAULT_IQ_RX_BUF_A_ADDR |
|---|
| 716 | #define WL_BUF_DEFAULT_IQ_TX_BUF_B_ADDR WL_BUF_DEFAULT_IQ_TX_BUF_A_ADDR |
|---|
| 717 | #define WL_BUF_DEFAULT_RSSI_BUF_B_ADDR WL_BUF_DEFAULT_RSSI_BUF_A_ADDR |
|---|
| 718 | #define WL_BUF_DEFAULT_IQ_RX_BUF_B_SIZE WL_BUF_DEFAULT_IQ_RX_BUF_A_SIZE |
|---|
| 719 | #define WL_BUF_DEFAULT_IQ_TX_BUF_B_SIZE WL_BUF_DEFAULT_IQ_TX_BUF_A_SIZE |
|---|
| 720 | #define WL_BUF_DEFAULT_RSSI_BUF_B_SIZE WL_BUF_DEFAULT_RSSI_BUF_A_SIZE |
|---|
| 721 | |
|---|
| 722 | // Define RF C Buffer addresses / sizes |
|---|
| 723 | #define WL_BUF_DEFAULT_IQ_RX_BUF_C_ADDR WL_BUF_DEFAULT_IQ_RX_BUF_A_ADDR |
|---|
| 724 | #define WL_BUF_DEFAULT_IQ_TX_BUF_C_ADDR WL_BUF_DEFAULT_IQ_TX_BUF_A_ADDR |
|---|
| 725 | #define WL_BUF_DEFAULT_RSSI_BUF_C_ADDR WL_BUF_DEFAULT_RSSI_BUF_A_ADDR |
|---|
| 726 | #define WL_BUF_DEFAULT_IQ_RX_BUF_C_SIZE WL_BUF_DEFAULT_IQ_RX_BUF_A_SIZE |
|---|
| 727 | #define WL_BUF_DEFAULT_IQ_TX_BUF_C_SIZE WL_BUF_DEFAULT_IQ_TX_BUF_A_SIZE |
|---|
| 728 | #define WL_BUF_DEFAULT_RSSI_BUF_C_SIZE WL_BUF_DEFAULT_RSSI_BUF_A_SIZE |
|---|
| 729 | |
|---|
| 730 | // Define RF D Buffer addresses / sizes |
|---|
| 731 | #define WL_BUF_DEFAULT_IQ_RX_BUF_D_ADDR WL_BUF_DEFAULT_IQ_RX_BUF_A_ADDR |
|---|
| 732 | #define WL_BUF_DEFAULT_IQ_TX_BUF_D_ADDR WL_BUF_DEFAULT_IQ_TX_BUF_A_ADDR |
|---|
| 733 | #define WL_BUF_DEFAULT_RSSI_BUF_D_ADDR WL_BUF_DEFAULT_RSSI_BUF_A_ADDR |
|---|
| 734 | #define WL_BUF_DEFAULT_IQ_RX_BUF_D_SIZE WL_BUF_DEFAULT_IQ_RX_BUF_A_SIZE |
|---|
| 735 | #define WL_BUF_DEFAULT_IQ_TX_BUF_D_SIZE WL_BUF_DEFAULT_IQ_TX_BUF_A_SIZE |
|---|
| 736 | #define WL_BUF_DEFAULT_RSSI_BUF_D_SIZE WL_BUF_DEFAULT_RSSI_BUF_A_SIZE |
|---|
| 737 | #else |
|---|
| 738 | // Define RF B Buffer addresses / sizes |
|---|
| 739 | #define WL_BUF_DEFAULT_IQ_RX_BUF_B_ADDR 0 |
|---|
| 740 | #define WL_BUF_DEFAULT_IQ_TX_BUF_B_ADDR 0 |
|---|
| 741 | #define WL_BUF_DEFAULT_RSSI_BUF_B_ADDR 0 |
|---|
| 742 | #define WL_BUF_DEFAULT_IQ_RX_BUF_B_SIZE 0 |
|---|
| 743 | #define WL_BUF_DEFAULT_IQ_TX_BUF_B_SIZE 0 |
|---|
| 744 | #define WL_BUF_DEFAULT_RSSI_BUF_B_SIZE 0 |
|---|
| 745 | |
|---|
| 746 | // Define RF C Buffer addresses / sizes |
|---|
| 747 | #define WL_BUF_DEFAULT_IQ_RX_BUF_C_ADDR 0 |
|---|
| 748 | #define WL_BUF_DEFAULT_IQ_TX_BUF_C_ADDR 0 |
|---|
| 749 | #define WL_BUF_DEFAULT_RSSI_BUF_C_ADDR 0 |
|---|
| 750 | #define WL_BUF_DEFAULT_IQ_RX_BUF_C_SIZE 0 |
|---|
| 751 | #define WL_BUF_DEFAULT_IQ_TX_BUF_C_SIZE 0 |
|---|
| 752 | #define WL_BUF_DEFAULT_RSSI_BUF_C_SIZE 0 |
|---|
| 753 | |
|---|
| 754 | // Define RF D Buffer addresses / sizes |
|---|
| 755 | #define WL_BUF_DEFAULT_IQ_RX_BUF_D_ADDR 0 |
|---|
| 756 | #define WL_BUF_DEFAULT_IQ_TX_BUF_D_ADDR 0 |
|---|
| 757 | #define WL_BUF_DEFAULT_RSSI_BUF_D_ADDR 0 |
|---|
| 758 | #define WL_BUF_DEFAULT_IQ_RX_BUF_D_SIZE 0 |
|---|
| 759 | #define WL_BUF_DEFAULT_IQ_TX_BUF_D_SIZE 0 |
|---|
| 760 | #define WL_BUF_DEFAULT_RSSI_BUF_D_SIZE 0 |
|---|
| 761 | #endif |
|---|
| 762 | |
|---|
| 763 | #endif // #if 0 |
|---|
| 764 | |
|---|
| 765 | |
|---|
| 766 | |
|---|
| 767 | // ********************************************************************** |
|---|
| 768 | // Memory defines for BRAM sample buffers |
|---|
| 769 | // - Renamed from XPAR* here for easier maintenance |
|---|
| 770 | // |
|---|
| 771 | #define WARPLAB_IQ_RX_BUF_A XPAR_RFA_IQ_RX_BUFFER_CTRL_S_AXI_BASEADDR |
|---|
| 772 | #define WARPLAB_IQ_TX_BUF_A XPAR_RFA_IQ_TX_BUFFER_CTRL_S_AXI_BASEADDR |
|---|
| 773 | #define WARPLAB_RSSI_BUF_A XPAR_RFA_RSSI_BUFFER_CTRL_S_AXI_BASEADDR |
|---|
| 774 | |
|---|
| 775 | #define WARPLAB_IQ_RX_BUF_A_SIZE (XPAR_RFA_IQ_RX_BUFFER_CTRL_S_AXI_HIGHADDR - XPAR_RFA_IQ_RX_BUFFER_CTRL_S_AXI_BASEADDR + 1) |
|---|
| 776 | #define WARPLAB_IQ_TX_BUF_A_SIZE (XPAR_RFA_IQ_TX_BUFFER_CTRL_S_AXI_HIGHADDR - XPAR_RFA_IQ_TX_BUFFER_CTRL_S_AXI_BASEADDR + 1) |
|---|
| 777 | #define WARPLAB_RSSI_BUF_A_SIZE (XPAR_RFA_RSSI_BUFFER_CTRL_S_AXI_HIGHADDR - XPAR_RFA_RSSI_BUFFER_CTRL_S_AXI_BASEADDR + 1) |
|---|
| 778 | |
|---|
| 779 | #define WARPLAB_IQ_RX_BUF_B XPAR_RFB_IQ_RX_BUFFER_CTRL_S_AXI_BASEADDR |
|---|
| 780 | #define WARPLAB_IQ_TX_BUF_B XPAR_RFB_IQ_TX_BUFFER_CTRL_S_AXI_BASEADDR |
|---|
| 781 | #define WARPLAB_RSSI_BUF_B XPAR_RFB_RSSI_BUFFER_CTRL_S_AXI_BASEADDR |
|---|
| 782 | |
|---|
| 783 | #define WARPLAB_IQ_RX_BUF_B_SIZE (XPAR_RFB_IQ_RX_BUFFER_CTRL_S_AXI_HIGHADDR - XPAR_RFB_IQ_RX_BUFFER_CTRL_S_AXI_BASEADDR + 1) |
|---|
| 784 | #define WARPLAB_IQ_TX_BUF_B_SIZE (XPAR_RFB_IQ_TX_BUFFER_CTRL_S_AXI_HIGHADDR - XPAR_RFB_IQ_TX_BUFFER_CTRL_S_AXI_BASEADDR + 1) |
|---|
| 785 | #define WARPLAB_RSSI_BUF_B_SIZE (XPAR_RFB_RSSI_BUFFER_CTRL_S_AXI_HIGHADDR - XPAR_RFB_RSSI_BUFFER_CTRL_S_AXI_BASEADDR + 1) |
|---|
| 786 | |
|---|
| 787 | |
|---|
| 788 | // NOTE: Since the 2RF design does not contain memories for the RFC and RFD buffers |
|---|
| 789 | // we will map RFC and RFD to 0 and set the buffer size to 0 so there are no issues |
|---|
| 790 | // since there is no physical memory allocated (unlike previous revisions |
|---|
| 791 | // where the memory was still allocated even though it wasn't used). |
|---|
| 792 | // |
|---|
| 793 | #if WARPLAB_CONFIG_4RF |
|---|
| 794 | #define WARPLAB_IQ_RX_BUF_C XPAR_RFC_IQ_RX_BUFFER_CTRL_S_AXI_BASEADDR |
|---|
| 795 | #define WARPLAB_IQ_TX_BUF_C XPAR_RFC_IQ_TX_BUFFER_CTRL_S_AXI_BASEADDR |
|---|
| 796 | #define WARPLAB_RSSI_BUF_C XPAR_RFC_RSSI_BUFFER_CTRL_S_AXI_BASEADDR |
|---|
| 797 | |
|---|
| 798 | #define WARPLAB_IQ_RX_BUF_C_SIZE (XPAR_RFC_IQ_RX_BUFFER_CTRL_S_AXI_HIGHADDR - XPAR_RFC_IQ_RX_BUFFER_CTRL_S_AXI_BASEADDR + 1) |
|---|
| 799 | #define WARPLAB_IQ_TX_BUF_C_SIZE (XPAR_RFC_IQ_TX_BUFFER_CTRL_S_AXI_HIGHADDR - XPAR_RFC_IQ_TX_BUFFER_CTRL_S_AXI_BASEADDR + 1) |
|---|
| 800 | #define WARPLAB_RSSI_BUF_C_SIZE (XPAR_RFC_RSSI_BUFFER_CTRL_S_AXI_HIGHADDR - XPAR_RFC_RSSI_BUFFER_CTRL_S_AXI_BASEADDR + 1) |
|---|
| 801 | |
|---|
| 802 | #define WARPLAB_IQ_RX_BUF_D XPAR_RFD_IQ_RX_BUFFER_CTRL_S_AXI_BASEADDR |
|---|
| 803 | #define WARPLAB_IQ_TX_BUF_D XPAR_RFD_IQ_TX_BUFFER_CTRL_S_AXI_BASEADDR |
|---|
| 804 | #define WARPLAB_RSSI_BUF_D XPAR_RFD_RSSI_BUFFER_CTRL_S_AXI_BASEADDR |
|---|
| 805 | |
|---|
| 806 | #define WARPLAB_IQ_RX_BUF_D_SIZE (XPAR_RFD_IQ_RX_BUFFER_CTRL_S_AXI_HIGHADDR - XPAR_RFD_IQ_RX_BUFFER_CTRL_S_AXI_BASEADDR + 1) |
|---|
| 807 | #define WARPLAB_IQ_TX_BUF_D_SIZE (XPAR_RFD_IQ_TX_BUFFER_CTRL_S_AXI_HIGHADDR - XPAR_RFD_IQ_TX_BUFFER_CTRL_S_AXI_BASEADDR + 1) |
|---|
| 808 | #define WARPLAB_RSSI_BUF_D_SIZE (XPAR_RFD_RSSI_BUFFER_CTRL_S_AXI_HIGHADDR - XPAR_RFD_RSSI_BUFFER_CTRL_S_AXI_BASEADDR + 1) |
|---|
| 809 | #else |
|---|
| 810 | #if WL_BUF_DEBUG_4RF_ON_2RF |
|---|
| 811 | // In the case we want to debug the 4RF buffers on a 2RF design, |
|---|
| 812 | // map RFC -> RFA and RFD -> RFB |
|---|
| 813 | #define WARPLAB_IQ_RX_BUF_C WARPLAB_IQ_RX_BUF_A |
|---|
| 814 | #define WARPLAB_IQ_TX_BUF_C WARPLAB_IQ_TX_BUF_A |
|---|
| 815 | #define WARPLAB_RSSI_BUF_C WARPLAB_RSSI_BUF_A |
|---|
| 816 | |
|---|
| 817 | #define WARPLAB_IQ_RX_BUF_C_SIZE WARPLAB_IQ_RX_BUF_A_SIZE |
|---|
| 818 | #define WARPLAB_IQ_TX_BUF_C_SIZE WARPLAB_IQ_TX_BUF_A_SIZE |
|---|
| 819 | #define WARPLAB_RSSI_BUF_C_SIZE WARPLAB_RSSI_BUF_A_SIZE |
|---|
| 820 | |
|---|
| 821 | #define WARPLAB_IQ_RX_BUF_D WARPLAB_IQ_RX_BUF_B |
|---|
| 822 | #define WARPLAB_IQ_TX_BUF_D WARPLAB_IQ_TX_BUF_B |
|---|
| 823 | #define WARPLAB_RSSI_BUF_D WARPLAB_RSSI_BUF_B |
|---|
| 824 | |
|---|
| 825 | #define WARPLAB_IQ_RX_BUF_D_SIZE WARPLAB_IQ_RX_BUF_B_SIZE |
|---|
| 826 | #define WARPLAB_IQ_TX_BUF_D_SIZE WARPLAB_IQ_TX_BUF_B_SIZE |
|---|
| 827 | #define WARPLAB_RSSI_BUF_D_SIZE WARPLAB_RSSI_BUF_B_SIZE |
|---|
| 828 | #else |
|---|
| 829 | #define WARPLAB_IQ_RX_BUF_C 0 |
|---|
| 830 | #define WARPLAB_IQ_TX_BUF_C 0 |
|---|
| 831 | #define WARPLAB_RSSI_BUF_C 0 |
|---|
| 832 | |
|---|
| 833 | #define WARPLAB_IQ_RX_BUF_C_SIZE 0 |
|---|
| 834 | #define WARPLAB_IQ_TX_BUF_C_SIZE 0 |
|---|
| 835 | #define WARPLAB_RSSI_BUF_C_SIZE 0 |
|---|
| 836 | |
|---|
| 837 | #define WARPLAB_IQ_RX_BUF_D 0 |
|---|
| 838 | #define WARPLAB_IQ_TX_BUF_D 0 |
|---|
| 839 | #define WARPLAB_RSSI_BUF_D 0 |
|---|
| 840 | |
|---|
| 841 | #define WARPLAB_IQ_RX_BUF_D_SIZE 0 |
|---|
| 842 | #define WARPLAB_IQ_TX_BUF_D_SIZE 0 |
|---|
| 843 | #define WARPLAB_RSSI_BUF_D_SIZE 0 |
|---|
| 844 | #endif |
|---|
| 845 | #endif |
|---|
| 846 | |
|---|
| 847 | |
|---|
| 848 | |
|---|
| 849 | // ********************************************************************** |
|---|
| 850 | // Defines for WARPLab Buffers Core |
|---|
| 851 | // - Renamed from XPAR* here for easier maintenance |
|---|
| 852 | // |
|---|
| 853 | |
|---|
| 854 | // Interupt ID |
|---|
| 855 | #define WL_BUF_RX_INTERRUPT_ID XPAR_INTC_0_W3_WARPLAB_BUFFERS_AXIW_0_RF_RX_IQ_RSSI_INT_VEC_ID ///< XParameters rename of buffers core rx interrupt |
|---|
| 856 | #define WL_BUF_TX_INTERRUPT_ID XPAR_INTC_0_W3_WARPLAB_BUFFERS_AXIW_0_RF_TX_IQ_INT_VEC_ID ///< XParameters rename of buffers core tx interrupt |
|---|
| 857 | |
|---|
| 858 | |
|---|
| 859 | |
|---|
| 860 | |
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| 861 | /*********************** Global Structure Definitions ************************/ |
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| 862 | |
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| 863 | /******************************** Functions **********************************/ |
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| 864 | |
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| 865 | int wl_baseband_setup_interrupt(XIntc* intc); |
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| 866 | |
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| 867 | #endif |
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| 868 | |
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| 869 | #endif /* WL_BASEBAND_H_ */ |
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