[4284] | 1 | /** @file wl_trigger_manager.h |
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| 2 | * @brief WARPLab Framework (Trigger Manager) |
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| 3 | * |
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| 4 | * This contains the code for WARPLab Framework. |
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| 5 | * |
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| 6 | * @copyright Copyright 2013, Mango Communications. All rights reserved. |
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| 7 | * Distributed under the WARP license (http://warpproject.org/license) |
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| 8 | * |
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| 9 | * @author Chris Hunter (chunter [at] mangocomm.com) |
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| 10 | * @author Patrick Murphy (murphpo [at] mangocomm.com) |
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| 11 | * @author Erik Welsh (welsh [at] mangocomm.com) |
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| 12 | */ |
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[1995] | 13 | |
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[4284] | 14 | /***************************** Include Files *********************************/ |
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| 15 | |
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| 16 | // WARPLab includes |
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[1915] | 17 | #include "wl_common.h" |
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| 18 | |
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[4284] | 19 | |
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| 20 | |
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| 21 | /*************************** Constant Definitions ****************************/ |
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[1915] | 22 | #ifndef TRIGCONF_H_ |
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| 23 | #define TRIGCONF_H_ |
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| 24 | |
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[4284] | 25 | |
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| 26 | // ********************************************************************** |
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| 27 | // Command IDs (must match the CMD_ properties in wl_transport_*.m) |
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[4184] | 28 | // |
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[4783] | 29 | #define CMDID_TRIG_MNGR_ADD_ETHERNET_TRIG 0x000001 |
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| 30 | #define CMDID_TRIG_MNGR_DEL_ETHERNET_TRIG 0x000002 |
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| 31 | #define CMDID_TRIG_MNGR_CLR_ETHERNET_TRIGS 0x000003 |
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| 32 | #define CMDID_TRIG_MNGR_HW_SW_ETHERNET_TRIG 0x000004 |
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[4184] | 33 | |
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[4783] | 34 | #define CMDID_TRIG_MNGR_INPUT_SEL 0x000010 |
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| 35 | #define CMDID_TRIG_MNGR_OUTPUT_DELAY 0x000011 |
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| 36 | #define CMDID_TRIG_MNGR_OUTPUT_HOLD 0x000012 |
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| 37 | #define CMDID_TRIG_MNGR_OUTPUT_READ 0x000013 |
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| 38 | #define CMDID_TRIG_MNGR_OUTPUT_CLEAR 0x000014 |
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[1949] | 39 | |
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[4783] | 40 | #define CMDID_TRIG_MNGR_INPUT_ENABLE 0x000020 |
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| 41 | #define CMDID_TRIG_MNGR_INPUT_DEBOUNCE 0x000021 |
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| 42 | #define CMDID_TRIG_MNGR_INPUT_DELAY 0x000022 |
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| 43 | #define CMDID_TRIG_MNGR_IDELAY 0x000023 |
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| 44 | #define CMDID_TRIG_MNGR_ODELAY 0x000024 |
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[4184] | 45 | |
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[4783] | 46 | #define CMDID_TRIG_MNGR_ENERGY_BUSY_THRESHOLD 0x000030 |
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| 47 | #define CMDID_TRIG_MNGR_ENERGY_RSSI_AVG_LEN 0x000031 |
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| 48 | #define CMDID_TRIG_MNGR_ENERGY_BUSY_MIN_LEN 0x000032 |
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| 49 | #define CMDID_TRIG_MNGR_ENERGY_IFC_SEL 0x000033 |
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[4284] | 50 | |
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[4783] | 51 | #define CMDID_TRIG_MNGR_TEST_TRIGGER 0x000080 |
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[4328] | 52 | |
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| 53 | |
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[4783] | 54 | |
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[4184] | 55 | // ---------------------------------------------------------------------------- |
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[4783] | 56 | // Misc Defines |
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| 57 | // |
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| 58 | #define NUM_INPUT_TRIGGERS 9 |
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| 59 | #define NUM_OUTPUT_TRIGGERS 6 |
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[1915] | 60 | |
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[4783] | 61 | #define ETH_TRIG_HW 0 |
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| 62 | #define ETH_TRIG_SW 1 |
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| 63 | #define ETH_TRIG_INVALID 0xFFFFFFFF |
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[1915] | 64 | |
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| 65 | |
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[2009] | 66 | |
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[4783] | 67 | // ---------------------------------------------------------------------------- |
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| 68 | // Register Name Mapping |
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| 69 | // |
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| 70 | #define TRIG_MNGR_REG_CORE_INFO XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_CORE_INFO |
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[2009] | 71 | |
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[4783] | 72 | #define TRIG_MNGR_REG_TRIG_OUTPUT XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT |
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[2009] | 73 | |
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[4783] | 74 | #define TRIG_MNGR_REG_TRIG_IN_CONF_0 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_IN_CONF_0 |
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| 75 | #define TRIG_MNGR_REG_TRIG_IN_CONF_1 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_IN_CONF_1 |
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| 76 | #define TRIG_MNGR_REG_TRIG_IN_CONF_2 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_IN_CONF_2 |
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| 77 | #define TRIG_MNGR_REG_TRIG_IN_CONF_3 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_IN_CONF_3 |
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| 78 | #define TRIG_MNGR_REG_TRIG_IN_CONF_4 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_IN_CONF_4 |
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| 79 | #define TRIG_MNGR_REG_TRIG_IN_CONF_5 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_IN_CONF_5 |
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| 80 | #define TRIG_MNGR_REG_TRIG_IN_CONF_6 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_IN_CONF_6 |
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| 81 | #define TRIG_MNGR_REG_TRIG_IN_CONF_7 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_IN_CONF_7 |
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| 82 | #define TRIG_MNGR_REG_TRIG_IN_CONF_8 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_IN_CONF_8 |
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[2009] | 83 | |
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[4783] | 84 | #define TRIG_MNGR_REG_TRIG_OUT_0_CONF_0 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT_0_CONF_0 |
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| 85 | #define TRIG_MNGR_REG_TRIG_OUT_0_CONF_1 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT_0_CONF_1 |
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| 86 | #define TRIG_MNGR_REG_TRIG_OUT_1_CONF_0 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT_1_CONF_0 |
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| 87 | #define TRIG_MNGR_REG_TRIG_OUT_1_CONF_1 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT_1_CONF_1 |
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| 88 | #define TRIG_MNGR_REG_TRIG_OUT_2_CONF_0 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT_2_CONF_0 |
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| 89 | #define TRIG_MNGR_REG_TRIG_OUT_2_CONF_1 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT_2_CONF_1 |
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| 90 | #define TRIG_MNGR_REG_TRIG_OUT_3_CONF_0 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT_3_CONF_0 |
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| 91 | #define TRIG_MNGR_REG_TRIG_OUT_3_CONF_1 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT_3_CONF_1 |
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| 92 | #define TRIG_MNGR_REG_TRIG_OUT_4_CONF_0 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT_4_CONF_0 |
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| 93 | #define TRIG_MNGR_REG_TRIG_OUT_4_CONF_1 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT_4_CONF_1 |
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| 94 | #define TRIG_MNGR_REG_TRIG_OUT_5_CONF_0 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT_5_CONF_0 |
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| 95 | #define TRIG_MNGR_REG_TRIG_OUT_5_CONF_1 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT_5_CONF_1 |
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| 96 | |
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| 97 | #define TRIG_MNGR_REG_TRIG_IODELAYS_CONTROL XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_IODELAYS_CONTROL |
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| 98 | #define TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_ODELAY_CFG_CMPLL |
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| 99 | #define TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_ODELAY_CFG_DEBUG_HDR |
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| 100 | #define TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_IDELAY_CFG_CMPLL |
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| 101 | #define TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_IDELAY_CFG_DEBUG_HDR |
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| 102 | |
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| 103 | #define TRIG_MNGR_REG_RSSI_PKT_DET_CONFIG XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_RSSI_PKT_DET_CONFIG |
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| 104 | #define TRIG_MNGR_REG_RSSI_PKT_DET_DURATIONS XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_RSSI_PKT_DET_DURATIONS |
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| 105 | #define TRIG_MNGR_REG_RSSI_PKT_DET_THRESHOLDS XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_RSSI_PKT_DET_THRESHOLDS |
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| 106 | |
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| 107 | #define TRIG_MNGR_REG_PKT_OPS_0 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_PKTOPS0 |
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| 108 | #define TRIG_MNGR_REG_PKT_OPS_1 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_PKTOPS1 |
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[4786] | 109 | #define TRIG_MNGR_REG_PKT_TEMPLATE_0 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_PKTTEMPLATE0 |
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| 110 | #define TRIG_MNGR_REG_PKT_TEMPLATE_1 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_PKTTEMPLATE1 |
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[4783] | 111 | |
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| 112 | |
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| 113 | |
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[4184] | 114 | // ---------------------------------------------------------------------------- |
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| 115 | // INPUT TRIGGER CONFIGURATION |
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[4783] | 116 | // |
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| 117 | // |
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| 118 | // -------------------------------------------------------- |
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| 119 | // Configuration Register 0 |
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| 120 | // [ 4: 0] - Input Delay |
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| 121 | // [29] - Use SW / HW for trigger (Ethernet triggers only) |
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| 122 | // [30] - Raise Trigger (Ethernet and software triggers only) |
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| 123 | // [30] - Debounce (External pin input triggers only) |
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| 124 | // [31] - Reset |
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| 125 | // |
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| 126 | #define INPUT_DELAY_MASK 0x0000001F |
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[2009] | 127 | |
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[4783] | 128 | #define INPUT_ETH_TRIGGER_SW_HW_MASK 0x20000000 |
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| 129 | |
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| 130 | #define INPUT_RAISE_TRIGGER_MASK 0x40000000 |
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| 131 | #define INPUT_EXT_TRIGGER_DEBOUNCE_MASK 0x40000000 |
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| 132 | |
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[4927] | 133 | #define INPUT_DISABLE_MASK 0x80000000 |
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[4783] | 134 | |
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| 135 | |
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[4184] | 136 | // -------------------------------------------------------- |
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[4783] | 137 | // Macros |
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| 138 | // |
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| 139 | #define trigger_proc_in_eth_A_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_0) & (~INPUT_DELAY_MASK)) | (val & INPUT_DELAY_MASK)) |
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| 140 | #define trigger_proc_in_eth_A_get_delay() (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_0) & INPUT_DELAY_MASK) |
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| 141 | #define trigger_proc_in_eth_A_use_sw_trig() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_0) | (INPUT_ETH_TRIGGER_SW_HW_MASK))) |
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| 142 | #define trigger_proc_in_eth_A_use_hw_trig() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_0) & (~INPUT_ETH_TRIGGER_SW_HW_MASK))) |
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| 143 | #define trigger_proc_in_eth_A_raise_trigger() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_0) | (INPUT_RAISE_TRIGGER_MASK))) |
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| 144 | #define trigger_proc_in_eth_A_lower_trigger() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_0) & (~INPUT_RAISE_TRIGGER_MASK))) |
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[4927] | 145 | #define trigger_proc_in_eth_A_trig_disable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_0) | (INPUT_DISABLE_MASK))) |
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| 146 | #define trigger_proc_in_eth_A_trig_enable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_0) & (~INPUT_DISABLE_MASK))) |
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[2009] | 147 | |
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[4927] | 148 | #define trigger_proc_in_energy_trig_disable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_1) | (INPUT_DISABLE_MASK))) |
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| 149 | #define trigger_proc_in_energy_trig_enable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_1) & (~INPUT_DISABLE_MASK))) |
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[2009] | 150 | |
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[4783] | 151 | #define trigger_proc_in_agc_done_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_2, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_2) & (~INPUT_DELAY_MASK)) | (val & INPUT_DELAY_MASK)) |
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| 152 | #define trigger_proc_in_agc_done_get_delay() (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_2) & INPUT_DELAY_MASK) |
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[4927] | 153 | #define trigger_proc_in_agc_done_trig_disable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_2, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_2) | (INPUT_DISABLE_MASK))) |
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| 154 | #define trigger_proc_in_agc_done_trig_enable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_2, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_2) & (~INPUT_DISABLE_MASK))) |
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[2009] | 155 | |
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[4783] | 156 | #define trigger_proc_in_software_raise_trigger() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_3, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_3) | (INPUT_RAISE_TRIGGER_MASK))) |
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| 157 | #define trigger_proc_in_software_lower_trigger() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_3, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_3) & (~INPUT_RAISE_TRIGGER_MASK))) |
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[4927] | 158 | #define trigger_proc_in_software_trig_disable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_3, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_3) | (INPUT_DISABLE_MASK))) |
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| 159 | #define trigger_proc_in_software_trig_enable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_3, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_3) & (~INPUT_DISABLE_MASK))) |
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[2024] | 160 | |
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[4783] | 161 | #define trigger_proc_in_ext_P0_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_4, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_4) & (~INPUT_DELAY_MASK)) | (val & INPUT_DELAY_MASK)) |
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| 162 | #define trigger_proc_in_ext_P0_get_delay() (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_4) & INPUT_DELAY_MASK) |
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| 163 | #define trigger_proc_in_ext_P0_debounce_mode(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_4, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_4) & (~INPUT_EXT_TRIGGER_DEBOUNCE_MASK)) | ((val & 1) << 30)) |
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[4927] | 164 | #define trigger_proc_in_ext_P0_trig_disable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_4, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_4) | (INPUT_DISABLE_MASK))) |
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| 165 | #define trigger_proc_in_ext_P0_trig_enable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_4, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_4) & (~INPUT_DISABLE_MASK))) |
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[2009] | 166 | |
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[4783] | 167 | #define trigger_proc_in_ext_P1_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_5, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_5) & (~INPUT_DELAY_MASK)) | (val & INPUT_DELAY_MASK)) |
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| 168 | #define trigger_proc_in_ext_P1_get_delay() (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_5) & INPUT_DELAY_MASK) |
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| 169 | #define trigger_proc_in_ext_P1_debounce_mode(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_5, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_5) & (~INPUT_EXT_TRIGGER_DEBOUNCE_MASK)) | ((val & 1) << 30)) |
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[4927] | 170 | #define trigger_proc_in_ext_P1_trig_disable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_5, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_5) | (INPUT_DISABLE_MASK))) |
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| 171 | #define trigger_proc_in_ext_P1_trig_enable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_5, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_5) & (~INPUT_DISABLE_MASK))) |
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[2009] | 172 | |
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[4783] | 173 | #define trigger_proc_in_ext_P2_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_6, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_6) & (~INPUT_DELAY_MASK)) | (val & INPUT_DELAY_MASK)) |
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| 174 | #define trigger_proc_in_ext_P2_get_delay() (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_6) & INPUT_DELAY_MASK) |
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| 175 | #define trigger_proc_in_ext_P2_debounce_mode(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_6, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_6) & (~INPUT_EXT_TRIGGER_DEBOUNCE_MASK)) | ((val & 1) << 30)) |
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[4927] | 176 | #define trigger_proc_in_ext_P2_trig_disable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_6, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_6) | (INPUT_DISABLE_MASK))) |
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| 177 | #define trigger_proc_in_ext_P2_trig_enable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_6, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_6) & (~INPUT_DISABLE_MASK))) |
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[2009] | 178 | |
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[4783] | 179 | #define trigger_proc_in_ext_P3_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_7, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_7) & (~INPUT_DELAY_MASK)) | (val & INPUT_DELAY_MASK)) |
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| 180 | #define trigger_proc_in_ext_P3_get_delay() (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_7) & INPUT_DELAY_MASK) |
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| 181 | #define trigger_proc_in_ext_P3_debounce_mode(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_7, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_7) & (~INPUT_EXT_TRIGGER_DEBOUNCE_MASK)) | ((val & 1) << 30)) |
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[4927] | 182 | #define trigger_proc_in_ext_P3_trig_disable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_7, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_7) | (INPUT_DISABLE_MASK))) |
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| 183 | #define trigger_proc_in_ext_P3_trig_enable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_7, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_7) & (~INPUT_DISABLE_MASK))) |
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[2009] | 184 | |
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[4783] | 185 | #define trigger_proc_in_eth_B_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_8, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_8) & (~INPUT_DELAY_MASK)) | (val & INPUT_DELAY_MASK)) |
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| 186 | #define trigger_proc_in_eth_B_get_delay() (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_8) & INPUT_DELAY_MASK) |
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| 187 | #define trigger_proc_in_eth_B_use_sw_trig() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_8, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_8) | (INPUT_ETH_TRIGGER_SW_HW_MASK))) |
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| 188 | #define trigger_proc_in_eth_B_use_hw_trig() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_8, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_8) & (~INPUT_ETH_TRIGGER_SW_HW_MASK))) |
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| 189 | #define trigger_proc_in_eth_B_raise_trigger() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_8, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_8) | (INPUT_RAISE_TRIGGER_MASK))) |
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| 190 | #define trigger_proc_in_eth_B_lower_trigger() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_8, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_8) & (~INPUT_RAISE_TRIGGER_MASK))) |
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[4927] | 191 | #define trigger_proc_in_eth_B_trig_disable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_8, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_8) | (INPUT_DISABLE_MASK))) |
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| 192 | #define trigger_proc_in_eth_B_trig_enable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_8, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_8) & (~INPUT_DISABLE_MASK))) |
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[2009] | 193 | |
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| 194 | |
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| 195 | |
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[4783] | 196 | // ---------------------------------------------------------------------------- |
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| 197 | // IDELAY / ODELAY CONFIGURATION |
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| 198 | // |
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| 199 | // |
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| 200 | #define IO_DELAY_MASK 0x0000001F |
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[2009] | 201 | |
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[4783] | 202 | #define IO_DELAY_TYPE_PIN 0x00000000 |
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| 203 | #define IO_DELAY_TYPE_CM_PLL 0x00000001 |
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| 204 | |
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| 205 | |
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| 206 | // -------------------------------------------------------- |
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| 207 | // IDELAY / ODELAY Config register (CM-PLL and PIN registers) |
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| 208 | // [ 4: 0] - External Pin 0 IDELAY / ODELAY value |
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| 209 | // [12: 8] - External Pin 1 IDELAY / ODELAY value |
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| 210 | // [20:16] - External Pin 2 IDELAY / ODELAY value |
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| 211 | // [28:24] - External Pin 3 IDELAY / ODELAY value |
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| 212 | // |
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| 213 | #define EXT_P0_IO_DELAY_MASK 0x0000001F |
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| 214 | #define EXT_P1_IO_DELAY_MASK 0x00001F00 |
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| 215 | #define EXT_P2_IO_DELAY_MASK 0x001F0000 |
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| 216 | #define EXT_P3_IO_DELAY_MASK 0x1F000000 |
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| 217 | |
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| 218 | #define EXT_P0_IO_DELAY_BIT_SHIFT 0 |
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| 219 | #define EXT_P1_IO_DELAY_BIT_SHIFT 8 |
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| 220 | #define EXT_P2_IO_DELAY_BIT_SHIFT 16 |
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| 221 | #define EXT_P3_IO_DELAY_BIT_SHIFT 24 |
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| 222 | |
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| 223 | |
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| 224 | // -------------------------------------------------------- |
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| 225 | // IDELAY / ODELAY Control register |
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| 226 | // [0] - IDELAY update |
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| 227 | // [1] - ODELAY update |
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| 228 | // |
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| 229 | #define IDELAY_UPDATE_MASK 0x00000001 |
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| 230 | #define ODELAY_UPDATE_MASK 0x00000002 |
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| 231 | |
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| 232 | |
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| 233 | // -------------------------------------------------------- |
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| 234 | // Macros |
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| 235 | // |
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| 236 | #define trigger_proc_in_ext_P0_set_idelay_pin(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN, ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN) & (~EXT_P0_IO_DELAY_MASK)) | ((val & IO_DELAY_MASK) << EXT_P0_IO_DELAY_BIT_SHIFT))) |
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| 237 | #define trigger_proc_in_ext_P0_set_idelay_cm_pll(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL, ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL) & (~EXT_P0_IO_DELAY_MASK)) | ((val & IO_DELAY_MASK) << EXT_P0_IO_DELAY_BIT_SHIFT))) |
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| 238 | #define trigger_proc_in_ext_P0_set_odelay_pin(val) XIo_Out32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN, ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN) & (~EXT_P0_IO_DELAY_MASK)) | ((val & IO_DELAY_MASK) << EXT_P0_IO_DELAY_BIT_SHIFT))) |
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| 239 | #define trigger_proc_in_ext_P0_set_odelay_cm_pll(val) XIo_Out32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL, ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL) & (~EXT_P0_IO_DELAY_MASK)) | ((val & IO_DELAY_MASK) << EXT_P0_IO_DELAY_BIT_SHIFT))) |
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| 240 | #define trigger_proc_in_ext_P0_get_idelay_pin() ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN) & EXT_P0_IO_DELAY_MASK) >> EXT_P0_IO_DELAY_BIT_SHIFT) |
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| 241 | #define trigger_proc_in_ext_P0_get_idelay_cm_pll() ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL) & EXT_P0_IO_DELAY_MASK) >> EXT_P0_IO_DELAY_BIT_SHIFT) |
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| 242 | #define trigger_proc_in_ext_P0_get_odelay_pin() ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN) & EXT_P0_IO_DELAY_MASK) >> EXT_P0_IO_DELAY_BIT_SHIFT) |
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| 243 | #define trigger_proc_in_ext_P0_get_odelay_cm_pll() ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL) & EXT_P0_IO_DELAY_MASK) >> EXT_P0_IO_DELAY_BIT_SHIFT) |
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| 244 | |
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| 245 | #define trigger_proc_in_ext_P1_set_idelay_pin(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN, ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN) & (~EXT_P1_IO_DELAY_MASK)) | ((val & IO_DELAY_MASK) << EXT_P1_IO_DELAY_BIT_SHIFT))) |
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| 246 | #define trigger_proc_in_ext_P1_set_idelay_cm_pll(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL, ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL) & (~EXT_P1_IO_DELAY_MASK)) | ((val & IO_DELAY_MASK) << EXT_P1_IO_DELAY_BIT_SHIFT))) |
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| 247 | #define trigger_proc_in_ext_P1_set_odelay_pin(val) XIo_Out32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN, ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN) & (~EXT_P1_IO_DELAY_MASK)) | ((val & IO_DELAY_MASK) << EXT_P1_IO_DELAY_BIT_SHIFT))) |
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| 248 | #define trigger_proc_in_ext_P1_set_odelay_cm_pll(val) XIo_Out32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL, ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL) & (~EXT_P1_IO_DELAY_MASK)) | ((val & IO_DELAY_MASK) << EXT_P1_IO_DELAY_BIT_SHIFT))) |
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| 249 | #define trigger_proc_in_ext_P1_get_idelay_pin() ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN) & EXT_P1_IO_DELAY_MASK) >> EXT_P1_IO_DELAY_BIT_SHIFT) |
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| 250 | #define trigger_proc_in_ext_P1_get_idelay_cm_pll() ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL) & EXT_P1_IO_DELAY_MASK) >> EXT_P1_IO_DELAY_BIT_SHIFT) |
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| 251 | #define trigger_proc_in_ext_P1_get_odelay_pin() ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN) & EXT_P1_IO_DELAY_MASK) >> EXT_P1_IO_DELAY_BIT_SHIFT) |
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| 252 | #define trigger_proc_in_ext_P1_get_odelay_cm_pll() ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL) & EXT_P1_IO_DELAY_MASK) >> EXT_P1_IO_DELAY_BIT_SHIFT) |
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| 253 | |
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| 254 | #define trigger_proc_in_ext_P2_set_idelay_pin(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN, ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN) & (~EXT_P2_IO_DELAY_MASK)) | ((val & IO_DELAY_MASK) << EXT_P2_IO_DELAY_BIT_SHIFT))) |
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| 255 | #define trigger_proc_in_ext_P2_set_idelay_cm_pll(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL, ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL) & (~EXT_P2_IO_DELAY_MASK)) | ((val & IO_DELAY_MASK) << EXT_P2_IO_DELAY_BIT_SHIFT))) |
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| 256 | #define trigger_proc_in_ext_P2_set_odelay_pin(val) XIo_Out32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN, ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN) & (~EXT_P2_IO_DELAY_MASK)) | ((val & IO_DELAY_MASK) << EXT_P2_IO_DELAY_BIT_SHIFT))) |
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| 257 | #define trigger_proc_in_ext_P2_set_odelay_cm_pll(val) XIo_Out32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL, ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL) & (~EXT_P2_IO_DELAY_MASK)) | ((val & IO_DELAY_MASK) << EXT_P2_IO_DELAY_BIT_SHIFT))) |
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| 258 | #define trigger_proc_in_ext_P2_get_idelay_pin() ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN) & EXT_P2_IO_DELAY_MASK) >> EXT_P2_IO_DELAY_BIT_SHIFT) |
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| 259 | #define trigger_proc_in_ext_P2_get_idelay_cm_pll() ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL) & EXT_P2_IO_DELAY_MASK) >> EXT_P2_IO_DELAY_BIT_SHIFT) |
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| 260 | #define trigger_proc_in_ext_P2_get_odelay_pin() ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN) & EXT_P2_IO_DELAY_MASK) >> EXT_P2_IO_DELAY_BIT_SHIFT) |
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| 261 | #define trigger_proc_in_ext_P2_get_odelay_cm_pll() ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL) & EXT_P2_IO_DELAY_MASK) >> EXT_P2_IO_DELAY_BIT_SHIFT) |
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| 262 | |
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| 263 | #define trigger_proc_in_ext_P3_set_idelay_pin(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN, ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN) & (~EXT_P3_IO_DELAY_MASK)) | ((val & IO_DELAY_MASK) << EXT_P3_IO_DELAY_BIT_SHIFT))) |
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| 264 | #define trigger_proc_in_ext_P3_set_idelay_cm_pll(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL, ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL) & (~EXT_P3_IO_DELAY_MASK)) | ((val & IO_DELAY_MASK) << EXT_P3_IO_DELAY_BIT_SHIFT))) |
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| 265 | #define trigger_proc_in_ext_P3_set_odelay_pin(val) XIo_Out32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN, ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN) & (~EXT_P3_IO_DELAY_MASK)) | ((val & IO_DELAY_MASK) << EXT_P3_IO_DELAY_BIT_SHIFT))) |
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| 266 | #define trigger_proc_in_ext_P3_set_odelay_cm_pll(val) XIo_Out32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL, ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL) & (~EXT_P3_IO_DELAY_MASK)) | ((val & IO_DELAY_MASK) << EXT_P3_IO_DELAY_BIT_SHIFT))) |
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| 267 | #define trigger_proc_in_ext_P3_get_idelay_pin() ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN) & EXT_P3_IO_DELAY_MASK) >> EXT_P3_IO_DELAY_BIT_SHIFT) |
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| 268 | #define trigger_proc_in_ext_P3_get_idelay_cm_pll() ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL) & EXT_P3_IO_DELAY_MASK) >> EXT_P3_IO_DELAY_BIT_SHIFT) |
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| 269 | #define trigger_proc_in_ext_P3_get_odelay_pin() ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN) & EXT_P3_IO_DELAY_MASK) >> EXT_P3_IO_DELAY_BIT_SHIFT) |
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| 270 | #define trigger_proc_in_ext_P3_get_odelay_cm_pll() ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL) & EXT_P3_IO_DELAY_MASK) >> EXT_P3_IO_DELAY_BIT_SHIFT) |
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| 271 | |
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| 272 | |
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| 273 | #define trigger_proc_idelay_update_set() XIo_Out32(TRIG_MNGR_REG_TRIG_IODELAYS_CONTROL, ((XIo_In32(TRIG_MNGR_REG_TRIG_IODELAYS_CONTROL) & (~IDELAY_UPDATE_MASK)) | IDELAY_UPDATE_MASK)) |
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| 274 | #define trigger_proc_idelay_update_clear() XIo_Out32(TRIG_MNGR_REG_TRIG_IODELAYS_CONTROL, (XIo_In32(TRIG_MNGR_REG_TRIG_IODELAYS_CONTROL) & (~IDELAY_UPDATE_MASK))) |
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| 275 | |
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| 276 | #define trigger_proc_odelay_update_set() XIo_Out32(TRIG_MNGR_REG_TRIG_IODELAYS_CONTROL, ((XIo_In32(TRIG_MNGR_REG_TRIG_IODELAYS_CONTROL) & (~ODELAY_UPDATE_MASK)) | ODELAY_UPDATE_MASK)) |
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| 277 | #define trigger_proc_odelay_update_clear() XIo_Out32(TRIG_MNGR_REG_TRIG_IODELAYS_CONTROL, (XIo_In32(TRIG_MNGR_REG_TRIG_IODELAYS_CONTROL) & (~ODELAY_UPDATE_MASK))) |
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| 278 | |
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| 279 | |
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| 280 | |
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[4184] | 281 | // ---------------------------------------------------------------------------- |
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| 282 | // OUTPUT TRIGGER CONFIGURATION |
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| 283 | // |
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| 284 | // The output triggers are: |
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| 285 | // OUT0 - Baseband |
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| 286 | // OUT1 - AGC |
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[4783] | 287 | // OUT2 - External output pin 0 |
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| 288 | // OUT3 - External output pin 1 |
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| 289 | // OUT4 - External output pin 2 |
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| 290 | // OUT5 - External output pin 3 |
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[4184] | 291 | // |
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| 292 | // -------------------------------------------------------- |
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[4783] | 293 | // Configuration Register 0 |
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| 294 | // [ 8: 0] - AND terms used to trigger output |
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| 295 | // [15: 9] - Reserved |
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| 296 | // [24:16] - OR terms used to trigger output |
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| 297 | // [31:25] - Reserved |
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| 298 | // |
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[4438] | 299 | #define AND_OFFSET_BITS 0 |
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| 300 | |
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[4284] | 301 | #define AND_ETH_A 0x00000001 |
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| 302 | #define AND_ENERGY 0x00000002 |
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| 303 | #define AND_AGC_DONE 0x00000004 |
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| 304 | #define AND_SOFTWARE 0x00000008 |
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| 305 | #define AND_DEBUG0 0x00000010 |
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| 306 | #define AND_DEBUG1 0x00000020 |
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| 307 | #define AND_DEBUG2 0x00000040 |
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| 308 | #define AND_DEBUG3 0x00000080 |
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| 309 | #define AND_ETH_B 0x00000100 |
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| 310 | #define AND_ALL 0x000001FF |
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[2009] | 311 | |
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[4438] | 312 | #define OR_OFFSET_BITS 16 |
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| 313 | |
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[4284] | 314 | #define OR_ETH_A 0x00010000 |
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| 315 | #define OR_ENERGY 0x00020000 |
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| 316 | #define OR_AGC_DONE 0x00040000 |
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| 317 | #define OR_SOFTWARE 0x00080000 |
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| 318 | #define OR_DEBUG0 0x00100000 |
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| 319 | #define OR_DEBUG1 0x00200000 |
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| 320 | #define OR_DEBUG2 0x00400000 |
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| 321 | #define OR_DEBUG3 0x00800000 |
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| 322 | #define OR_ETH_B 0x01000000 |
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| 323 | #define OR_ALL 0x01FF0000 |
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[2009] | 324 | |
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[4783] | 325 | |
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| 326 | // -------------------------------------------------------- |
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| 327 | // Configuration Register 1 |
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[4927] | 328 | // [15: 0] - Output Trigger Delay |
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| 329 | // [29:16] - Reserved |
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| 330 | // [30] - Output Trigger Pulse Extender Bypass |
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[4783] | 331 | // [31] - Reset |
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| 332 | // |
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| 333 | // NOTE: The AGC output trigger has an extended delay to allow for more flexibility about when to |
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| 334 | // start the AGC. The Delay value for the AGC is 16 bits. |
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| 335 | // |
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| 336 | // |
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[4927] | 337 | #define OUT_DELAY_MASK 0x0000FFFF |
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[4783] | 338 | |
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[4927] | 339 | #define OUT_PULSE_EXTENDER_BYPASS_MASK 0x40000000 |
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| 340 | #define OUT_HOLD_MODE_MASK 0x80000000 |
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[2009] | 341 | |
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[4927] | 342 | #define OUT_HOLD_MODE_ENABLE 0 |
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| 343 | #define OUT_HOLD_MODE_DISABLE 1 |
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[4438] | 344 | |
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[4927] | 345 | |
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[4184] | 346 | // -------------------------------------------------------- |
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[4284] | 347 | // Register Macros |
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[2018] | 348 | |
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[4783] | 349 | #define trigger_proc_out0_set_config(mask) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_0_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_0_CONF_0) | (mask))) |
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| 350 | #define trigger_proc_out0_clear_config(mask) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_0_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_0_CONF_0) & (~(mask)))) |
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[4927] | 351 | #define trigger_proc_out0_get_hold_mode() ((XIo_In32(TRIG_MNGR_REG_TRIG_OUT_0_CONF_1) & OUT_HOLD_MODE_MASK) >> 31) |
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| 352 | #define trigger_proc_out0_set_hold_mode(val) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_0_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_0_CONF_1) & (~(OUT_HOLD_MODE_MASK))) | ((val << 31) & OUT_HOLD_MODE_MASK)) |
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| 353 | #define trigger_proc_out0_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_0_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_0_CONF_1) & (~(OUT_DELAY_MASK ))) | (val & OUT_DELAY_MASK )) |
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[4783] | 354 | #define trigger_proc_out0_get_reg_0() XIo_In32(TRIG_MNGR_REG_TRIG_OUT_0_CONF_0) |
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| 355 | #define trigger_proc_out0_get_reg_1() XIo_In32(TRIG_MNGR_REG_TRIG_OUT_0_CONF_1) |
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[2018] | 356 | |
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[4783] | 357 | #define trigger_proc_out1_set_config(mask) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_1_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_1_CONF_0) | (mask))) |
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| 358 | #define trigger_proc_out1_clear_config(mask) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_1_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_1_CONF_0) & (~(mask)))) |
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[4927] | 359 | #define trigger_proc_out1_get_hold_mode() ((XIo_In32(TRIG_MNGR_REG_TRIG_OUT_1_CONF_1) & OUT_HOLD_MODE_MASK) >> 31) |
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| 360 | #define trigger_proc_out1_set_hold_mode(val) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_1_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_1_CONF_1) & (~(OUT_HOLD_MODE_MASK))) | ((val << 31) & OUT_HOLD_MODE_MASK)) |
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| 361 | #define trigger_proc_out1_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_1_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_1_CONF_1) & (~(OUT_DELAY_MASK ))) | (val & OUT_DELAY_MASK )) |
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[4783] | 362 | #define trigger_proc_out1_get_reg_0() XIo_In32(TRIG_MNGR_REG_TRIG_OUT_1_CONF_0) |
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| 363 | #define trigger_proc_out1_get_reg_1() XIo_In32(TRIG_MNGR_REG_TRIG_OUT_1_CONF_1) |
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[2028] | 364 | |
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[4783] | 365 | #define trigger_proc_out2_set_config(mask) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_2_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_2_CONF_0) | (mask))) |
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| 366 | #define trigger_proc_out2_clear_config(mask) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_2_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_2_CONF_0) & (~(mask)))) |
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[4927] | 367 | #define trigger_proc_out2_get_hold_mode() ((XIo_In32(TRIG_MNGR_REG_TRIG_OUT_2_CONF_1) & OUT_HOLD_MODE_MASK) >> 31) |
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| 368 | #define trigger_proc_out2_set_hold_mode(val) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_2_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_2_CONF_1) & (~(OUT_HOLD_MODE_MASK))) | ((val << 31) & OUT_HOLD_MODE_MASK)) |
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| 369 | #define trigger_proc_out2_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_2_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_2_CONF_1) & (~(OUT_DELAY_MASK ))) | (val & OUT_DELAY_MASK )) |
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[4783] | 370 | #define trigger_proc_out2_get_reg_0() XIo_In32(TRIG_MNGR_REG_TRIG_OUT_2_CONF_0) |
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| 371 | #define trigger_proc_out2_get_reg_1() XIo_In32(TRIG_MNGR_REG_TRIG_OUT_2_CONF_1) |
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[2028] | 372 | |
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[4783] | 373 | #define trigger_proc_out3_set_config(mask) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_3_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_3_CONF_0) | (mask))) |
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| 374 | #define trigger_proc_out3_clear_config(mask) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_3_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_3_CONF_0) & (~(mask)))) |
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[4927] | 375 | #define trigger_proc_out3_get_hold_mode() ((XIo_In32(TRIG_MNGR_REG_TRIG_OUT_3_CONF_1) & OUT_HOLD_MODE_MASK) >> 31) |
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| 376 | #define trigger_proc_out3_set_hold_mode(val) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_3_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_3_CONF_1) & (~(OUT_HOLD_MODE_MASK))) | ((val << 31) & OUT_HOLD_MODE_MASK)) |
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| 377 | #define trigger_proc_out3_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_3_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_3_CONF_1) & (~(OUT_DELAY_MASK ))) | (val & OUT_DELAY_MASK )) |
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[4783] | 378 | #define trigger_proc_out3_get_reg_0() XIo_In32(TRIG_MNGR_REG_TRIG_OUT_3_CONF_0) |
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| 379 | #define trigger_proc_out3_get_reg_1() XIo_In32(TRIG_MNGR_REG_TRIG_OUT_3_CONF_1) |
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[2028] | 380 | |
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[4783] | 381 | #define trigger_proc_out4_set_config(mask) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_4_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_4_CONF_0) | (mask))) |
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| 382 | #define trigger_proc_out4_clear_config(mask) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_4_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_4_CONF_0) & (~(mask)))) |
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[4927] | 383 | #define trigger_proc_out4_get_hold_mode() ((XIo_In32(TRIG_MNGR_REG_TRIG_OUT_4_CONF_1) & OUT_HOLD_MODE_MASK) >> 31) |
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| 384 | #define trigger_proc_out4_set_hold_mode(val) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_4_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_4_CONF_1) & (~(OUT_HOLD_MODE_MASK))) | ((val << 31) & OUT_HOLD_MODE_MASK)) |
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| 385 | #define trigger_proc_out4_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_4_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_4_CONF_1) & (~(OUT_DELAY_MASK ))) | (val & OUT_DELAY_MASK )) |
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[4783] | 386 | #define trigger_proc_out4_get_reg_0() XIo_In32(TRIG_MNGR_REG_TRIG_OUT_4_CONF_0) |
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| 387 | #define trigger_proc_out4_get_reg_1() XIo_In32(TRIG_MNGR_REG_TRIG_OUT_4_CONF_1) |
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[4184] | 388 | |
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[4783] | 389 | #define trigger_proc_out5_set_config(mask) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_5_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_5_CONF_0) | (mask))) |
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| 390 | #define trigger_proc_out5_clear_config(mask) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_5_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_5_CONF_0) & (~(mask)))) |
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[4927] | 391 | #define trigger_proc_out5_get_hold_mode() ((XIo_In32(TRIG_MNGR_REG_TRIG_OUT_5_CONF_1) & OUT_HOLD_MODE_MASK) >> 31) |
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| 392 | #define trigger_proc_out5_set_hold_mode(val) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_5_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_5_CONF_1) & (~(OUT_HOLD_MODE_MASK))) | ((val << 31) & OUT_HOLD_MODE_MASK)) |
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| 393 | #define trigger_proc_out5_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_5_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_5_CONF_1) & (~(OUT_DELAY_MASK ))) | (val & OUT_DELAY_MASK )) |
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[4783] | 394 | #define trigger_proc_out5_get_reg_0() XIo_In32(TRIG_MNGR_REG_TRIG_OUT_5_CONF_0) |
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| 395 | #define trigger_proc_out5_get_reg_1() XIo_In32(TRIG_MNGR_REG_TRIG_OUT_5_CONF_1) |
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[4184] | 396 | |
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| 397 | |
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| 398 | |
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| 399 | // ---------------------------------------------------------------------------- |
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[4783] | 400 | // Misc Registers |
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[4184] | 401 | // |
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[4783] | 402 | // -------------------------------------------------------- |
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| 403 | // Trigger Output Value Register: |
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| 404 | // [ 7: 0] - Number of Trigger Inputs |
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| 405 | // [15: 8] - Number of Trigger Outputs |
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| 406 | // [23:16] - Core ID |
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| 407 | // [31:24] - Reserved |
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| 408 | // |
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| 409 | #define trigger_proc_get_core_info() (XIo_In32(TRIG_MNGR_REG_CORE_INFO)) |
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[4184] | 410 | |
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[4783] | 411 | |
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| 412 | |
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[4184] | 413 | // -------------------------------------------------------- |
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[4783] | 414 | // Trigger Output Value Register: |
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| 415 | // [ 0] - Value of Output Trigger 0 |
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| 416 | // [ 1] - Value of Output Trigger 1 |
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| 417 | // [ 2] - Value of Output Trigger 2 |
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| 418 | // [ 3] - Value of Output Trigger 3 |
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| 419 | // [ 4] - Value of Output Trigger 4 |
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| 420 | // [ 5] - Value of Output Trigger 5 |
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| 421 | // [31: 6] - Reserved |
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| 422 | // |
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| 423 | #define OUT0 0x00000001 |
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| 424 | #define OUT1 0x00000002 |
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| 425 | #define OUT2 0x00000004 |
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| 426 | #define OUT3 0x00000008 |
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| 427 | #define OUT4 0x00000010 |
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| 428 | #define OUT5 0x00000020 |
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[4184] | 429 | |
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| 430 | |
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[4783] | 431 | // -------------------------------------------------------- |
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| 432 | // Macros |
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| 433 | // |
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| 434 | #define trigger_proc_get_output_values() (XIo_In32(TRIG_MNGR_REG_TRIG_OUTPUT)) |
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[4284] | 435 | |
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[4783] | 436 | |
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| 437 | |
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| 438 | // ---------------------------------------------------------------------------- |
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| 439 | // Energy Detection Registers |
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| 440 | // |
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[4184] | 441 | // -------------------------------------------------------- |
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[4783] | 442 | // Configuration Register: |
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| 443 | // [ 0] - Detect energy on RFA |
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| 444 | // [ 1] - Detect energy on RFB |
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| 445 | // [ 2] - Detect energy on RFC |
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| 446 | // [ 3] - Detect energy on RFD |
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| 447 | // [30: 4] - Reserved |
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| 448 | // [31] - Reset |
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| 449 | // |
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| 450 | #define WL_PACKET_DETECT_CONFIG_REG_RESET 0x80000000 |
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| 451 | #define WL_PACKET_DETECT_CONFIG_REG_MASK_A 0x00000001 |
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| 452 | #define WL_PACKET_DETECT_CONFIG_REG_MASK_B 0x00000002 |
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| 453 | #define WL_PACKET_DETECT_CONFIG_REG_MASK_C 0x00000004 |
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| 454 | #define WL_PACKET_DETECT_CONFIG_REG_MASK_D 0x00000008 |
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| 455 | #define WL_PACKET_DETECT_CONFIG_REG_MASK_ALL 0x0000000F |
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| 456 | |
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| 457 | |
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| 458 | // -------------------------------------------------------- |
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[4184] | 459 | // Macros |
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[4783] | 460 | // |
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[4184] | 461 | |
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| 462 | // Convert interface masks to packet detect mask |
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[4783] | 463 | #define IFC_TO_PACKET_DETECT_MASK(val) (val >> 28) |
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[4184] | 464 | |
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[4783] | 465 | #define wl_packet_detect_set_config(mask) XIo_Out32(TRIG_MNGR_REG_RSSI_PKT_DET_CONFIG, (XIo_In32(TRIG_MNGR_REG_RSSI_PKT_DET_CONFIG) | (mask))) |
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| 466 | #define wl_packet_detect_clear_config(mask) XIo_Out32(TRIG_MNGR_REG_RSSI_PKT_DET_CONFIG, (XIo_In32(TRIG_MNGR_REG_RSSI_PKT_DET_CONFIG) & (~(mask)))) |
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[4184] | 467 | |
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[4783] | 468 | #define wl_packet_detect_set_idle_threshold(idle) XIo_Out32(TRIG_MNGR_REG_RSSI_PKT_DET_THRESHOLDS, (XIo_In32(TRIG_MNGR_REG_RSSI_PKT_DET_THRESHOLDS) & (~0x0000FFFF)) | (idle & 0x0000FFFF)) |
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| 469 | #define wl_packet_detect_set_busy_threshold(busy) XIo_Out32(TRIG_MNGR_REG_RSSI_PKT_DET_THRESHOLDS, (XIo_In32(TRIG_MNGR_REG_RSSI_PKT_DET_THRESHOLDS) & (~0xFFFF0000)) | ((busy << 16)& 0xFFFF0000)) |
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[4184] | 470 | |
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[4783] | 471 | #define wl_packet_detect_set_RSSI_duration(rssi) XIo_Out32(TRIG_MNGR_REG_RSSI_PKT_DET_DURATIONS, (XIo_In32(TRIG_MNGR_REG_RSSI_PKT_DET_DURATIONS) & (~0x1F0000)) | ((rssi <<16)& 0x1F0000)) |
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| 472 | #define wl_packet_detect_set_idle_duration(idle) XIo_Out32(TRIG_MNGR_REG_RSSI_PKT_DET_DURATIONS, (XIo_In32(TRIG_MNGR_REG_RSSI_PKT_DET_DURATIONS) & (~0x0000FF)) | (idle & 0x0000FF)) |
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| 473 | #define wl_packet_detect_set_busy_duration(busy) XIo_Out32(TRIG_MNGR_REG_RSSI_PKT_DET_DURATIONS, (XIo_In32(TRIG_MNGR_REG_RSSI_PKT_DET_DURATIONS) & (~0x00FF00)) | ((busy << 8)& 0x00FF00)) |
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[4184] | 474 | |
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[4284] | 475 | |
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| 476 | |
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[4783] | 477 | // ---------------------------------------------------------------------------- |
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| 478 | // Defines for warplab_trigger_proc core operators |
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| 479 | |
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| 480 | // Equals |
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| 481 | #define U8_OP_EQ 0x01 |
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| 482 | #define U16_OP_EQ ((U8_OP_EQ << 8) | U8_OP_EQ) |
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| 483 | #define U32_OP_EQ ((U8_OP_EQ << 24) | (U8_OP_EQ << 16) | (U8_OP_EQ << 8) | U8_OP_EQ) |
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| 484 | |
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| 485 | // Not-equals |
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| 486 | #define U8_OP_NEQ 0x02 |
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| 487 | #define U16_OP_NEQ ((U8_OP_NEQ << 8) | U8_OP_NEQ) |
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| 488 | #define U32_OP_NEQ ((U8_OP_NEQ << 24) | (U8_OP_NEQ << 16) | (U8_OP_NEQ << 8) | U8_OP_NEQ) |
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| 489 | |
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| 490 | // No care (byte is ignored) |
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| 491 | #define U8_OP_NC 0x00 |
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| 492 | #define U16_OP_NC ((U8_OP_NC << 8) | U8_OP_NC) |
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| 493 | #define U32_OP_NC ((U8_OP_NC << 24) | (U8_OP_NC << 16) | (U8_OP_NC << 8) | U8_OP_NC) |
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| 494 | |
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| 495 | // Any-of-and (and(x,y) > 0) |
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| 496 | #define U8_OP_AA 0x03 |
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| 497 | #define U16_OP_AA ((U8_OP_AA << 8) | U8_OP_AA) |
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| 498 | #define U32_OP_AA ((U8_OP_AA << 24) | (U8_OP_AA << 16) | (U8_OP_AA << 8) | U8_OP_AA) |
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| 499 | |
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| 500 | |
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| 501 | |
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[4284] | 502 | /*********************** Global Structure Definitions ************************/ |
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| 503 | |
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| 504 | |
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| 505 | |
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| 506 | /*************************** Function Prototypes *****************************/ |
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| 507 | int trigmngr_init(); |
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| 508 | |
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[4514] | 509 | int trigmngr_process_cmd(int socket_index, void * from, wl_cmd_resp * command, wl_cmd_resp * response); |
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[4284] | 510 | |
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[4466] | 511 | void trigmngr_trigger_in(u32 trig_id, u32 eth_dev_num); |
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[4284] | 512 | |
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| 513 | |
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[1915] | 514 | #endif /* TRIGCONF_H_ */ |
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