| Line | |
|---|
| 1 | README |
|---|
| 2 | |
|---|
| 3 | This WARPLab Buffers core was taken from the WARP v3 WARPLab 7.5.0 release. This is straight |
|---|
| 4 | copy of the w3 Buffers core, renamed for the WARP v2 hardware, except for the following modifications: |
|---|
| 5 | |
|---|
| 6 | - Updated Model properties to reference w2_warplab_buffers_init.m |
|---|
| 7 | - Updated EDK processor block to use PLB bus |
|---|
| 8 | - Modified buffers interface block to use internal 32-bit memories vs external 128-bit memories |
|---|
| 9 | - Updated bus definitions to remove external memories |
|---|
| 10 | - Updated ADC inputs to be Fix_14_13 vs Fix_12_11 |
|---|
| 11 | - Updated DAC outputs to be Fix_16_15 vs Fix_12_11 |
|---|
| 12 | - Updated Config register to reserve *_WORD_ORDER |
|---|
| 13 | |
|---|
| 14 | NOTE: Logic exists in this core to support the same extended buffer addressing. However, the MPD has |
|---|
| 15 | not been modified to declare the ports as interrupts and the interrupt ports have not been connected |
|---|
| 16 | to the processor. Therefore, the Tx / Rx length should never be set greater than the supported |
|---|
| 17 | number of samples (2^14 for WARPLab 7.5.1) and the Tx / Rx IQ Thesholds should be set to the supported |
|---|
| 18 | number of samples (2^14 for WARPLab 7.5.1). |
|---|
| 19 | |
|---|
| 20 | |
|---|
Note: See
TracBrowser
for help on using the repository browser.
