source: ResearchApps/PHY/WARPLAB/WARPLab7/Sysgen_Reference/w2/warplab_trigger_proc/w2_warplab_trigger_proc_init.m

Last change on this file was 4465, checked in by welsh, 9 years ago

Version 1.04.a. Updates to register map for trigger inputs; Added bits to allow for SW control of Ethernet triggers for Eth A.

File size: 5.1 KB
Line 
1% ------------------------------------------------------------------------
2%  Initial Register Values
3% ------------------------------------------------------------------------
4
5% ------------------------------------------------------------------------
6% Trigger Input Configuration Register:
7%   Basic register format:
8%       [31]   - Reset
9%       [30]   - Debounce
10%       [29:5] - Reserved
11%       [4:0]  - Input Delay
12%   This register is replicated for each of the trigger inputs.  There are
13%   a number of reserved bits per trigger input in case the input delay
14%   needs to be increased in the future.
15%
16%   Input Trigger order:
17%       0 - Ethernet A
18%             NOTE:  Debounce bit is used as a SW trigger
19%                    Bit 29 is reserved (used in WARP v3 version)
20%       1 - Energy Detection
21%             NOTE:  Debounce bit is not supported
22%                    Delay is not supported
23%       2 - AGC
24%             NOTE:  Debounce bit is not supported
25%       3 - Software Trigger
26%             NOTE:  Debounce bit is used as a SW trigger
27%                    Delay is not supported
28%       4 - Debug Input Pin 0
29%       5 - Debug Input Pin 1
30%       6 - Debug Input Pin 2
31%       7 - Debug Input Pin 3
32%       8 - Ethernet B (Not supported)
33%         
34%
35TRIG_IN_CONF_0 = hex2dec('80000000');
36TRIG_IN_CONF_1 = hex2dec('80000000');
37TRIG_IN_CONF_2 = hex2dec('80000000');
38TRIG_IN_CONF_3 = hex2dec('80000000');
39TRIG_IN_CONF_4 = hex2dec('C0000000');    % Debounce enabled
40TRIG_IN_CONF_5 = hex2dec('C0000000');    % Debounce enabled
41TRIG_IN_CONF_6 = hex2dec('C0000000');    % Debounce enabled
42TRIG_IN_CONF_7 = hex2dec('C0000000');    % Debounce enabled
43TRIG_IN_CONF_8 = hex2dec('80000000');
44
45
46% ------------------------------------------------------------------------
47% Trigger Output Configuration Register:
48%   Register format:
49%       CONF_0:
50%           [31:25] - Reserved
51%           [24]    - Output OR use trigger input 8
52%           [23]    - Output OR use trigger input 7
53%           [22]    - Output OR use trigger input 6
54%           [21]    - Output OR use trigger input 5
55%           [20]    - Output OR use trigger input 4
56%           [19]    - Output OR use trigger input 3
57%           [18]    - Output OR use trigger input 2
58%           [17]    - Output OR use trigger input 1
59%           [16]    - Output OR use trigger input 0
60%           [15: 9] - Reserved
61%           [ 8]    - Output AND use trigger input 8
62%           [ 7]    - Output AND use trigger input 7
63%           [ 6]    - Output AND use trigger input 6
64%           [ 5]    - Output AND use trigger input 5
65%           [ 4]    - Output AND use trigger input 4
66%           [ 3]    - Output AND use trigger input 3
67%           [ 2]    - Output AND use trigger input 2
68%           [ 1]    - Output AND use trigger input 1
69%           [ 0]    - Output AND use trigger input 0
70%       CONF_1:
71%           [31]    - Reset
72%           [30: 5] - Reserved
73%           [ 4: 0] - Output Delay
74%   These two registers are replicated for each of the trigger outputs.
75%
76%   Output Trigger order (connected in MHS file):
77%       0 - Buffer trigger input
78%       1 - AGC packet in
79%       2 - Debug Output Pin 0
80%       3 - Debug Output Pin 1
81%       4 - Debug Output Pin 2
82%       5 - Debug Output Pin 3
83%
84TRIG_OUT_5_CONF_0 = hex2dec('0');
85TRIG_OUT_5_CONF_1 = hex2dec('80000000');
86
87TRIG_OUT_4_CONF_0 = hex2dec('0');
88TRIG_OUT_4_CONF_1 = hex2dec('80000000');
89
90TRIG_OUT_3_CONF_0 = hex2dec('0');
91TRIG_OUT_3_CONF_1 = hex2dec('80000000');
92
93TRIG_OUT_2_CONF_0 = hex2dec('0');
94TRIG_OUT_2_CONF_1 = hex2dec('80000000');
95
96TRIG_OUT_1_CONF_0 = hex2dec('0');
97TRIG_OUT_1_CONF_1 = hex2dec('80000000');
98
99TRIG_OUT_0_CONF_0 = hex2dec('0');
100TRIG_OUT_0_CONF_1 = hex2dec('80000000');
101
102
103% ------------------------------------------------------------------------
104% RSSI Packet Detection Configuration Register
105%   Register format:
106%       [31]    - Packet detect reset
107%       [30: 4] - Reserved
108%       [ 3]    - Packet detect mask RF D
109%       [ 2]    - Packet detect mask RF C
110%       [ 1]    - Packet detect mask RF B
111%       [ 0]    - Packet detect mask RF A
112%
113RSSI_PKT_DET_CONFIG = hex2dec('0');
114
115% ------------------------------------------------------------------------
116% RSSI Packet Detection Threshold Register
117%   Register format:
118%       [31:16] - Packet detect energy threshold busy
119%       [15: 0] - Packet detect energy threshold idle
120%
121RSSI_PKT_DET_THRESHOLDS = hex2dec('0');
122
123% ------------------------------------------------------------------------
124% RSSI Packet Detection Duration Register
125%   Register format:
126%       [31:21] - Reserved
127%       [20:16] - Packet detect RSSI average length
128%       [15: 8] - Packet detect duration busy
129%       [ 7: 0] - Packet detect duration idle
130%
131RSSI_PKT_DET_DURATIONS = hex2dec('0');
132
133
134% ------------------------------------------------------------------------
135% Ethernet Trigger Memories
136%     NOTE:  WARP v2 does not allow for Ethernet Triggers
137%
138% PKT_OPS_0      = hex2dec('0');
139% PKT_TEMPLATE_0 = hex2dec('0');
140%
141% PKT_OPS_1      = hex2dec('0');
142% PKT_TEMPLATE_1 = hex2dec('0');
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