| 1 | %IMPORTANT: if you change any of the NumSamps values, you must update the |
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| 2 | % EDK Processor block with the new shared memory sizes. We recommend |
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| 3 | % deleting the existing EDK Processor block and re-adding it, to ensure |
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| 4 | % all changes are reflected |
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| 5 | |
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| 6 | NumSamps_Tx_IQ = 2^15; |
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| 7 | NumSamps_Rx_IQ = 2^15; |
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| 8 | NumSamps_Rx_RSSI = 2^13; |
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| 9 | |
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| 10 | simulation = 0; |
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| 11 | |
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| 12 | % ------------------------------------------------------------------------ |
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| 13 | % Initial Register Values |
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| 14 | % ------------------------------------------------------------------------ |
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| 15 | |
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| 16 | if (simulation == 0) |
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| 17 | rx_length = 0; % Default 0 |
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| 18 | rf_rx_iq_threshold = 0; % Default 0 |
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| 19 | rf_rx_iq_buf_rd_byte_offset = 0; % Default 0 |
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| 20 | rf_rx_iq_buf_wr_byte_offset = 0; % Default 0 |
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| 21 | |
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| 22 | tx_length = 0; % Default 0 |
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| 23 | rf_tx_iq_threshold = 0; % Default 0 |
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| 24 | rf_tx_iq_buf_rd_byte_offset = 0; % Default 0 |
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| 25 | rf_tx_iq_buf_wr_byte_offset = 0; % Default 0 |
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| 26 | |
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| 27 | rf_error_clr = 0; % Default 0 |
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| 28 | |
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| 29 | rx_buf_en = 0; % Default 0 |
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| 30 | tx_buf_en = 0; % Default 0 |
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| 31 | |
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| 32 | txrx_counter_reset = 0; % Default 0 |
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| 33 | else |
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| 34 | rx_length = hex2dec('0000FFFF'); % Default (NumSamps_Rx_IQ - 1) |
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| 35 | rf_rx_iq_threshold = hex2dec('00002000'); % Default (NumSamps_Rx_IQ / 2) |
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| 36 | rf_rx_iq_buf_rd_byte_offset = 0; % Default 0 |
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| 37 | rf_rx_iq_buf_wr_byte_offset = 0; % Default 0 |
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| 38 | |
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| 39 | tx_length = hex2dec('0000FFFF'); % Default (NumSamps_Tx_IQ - 1) |
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| 40 | rf_tx_iq_threshold = hex2dec('00004000'); % Default (NumSamps_Tx_IQ / 2) |
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| 41 | rf_tx_iq_buf_wr_byte_offset = hex2dec('00020000'); % Default (NumSamps_Tx_IQ * 4) |
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| 42 | |
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| 43 | rf_error_clr = 0; % Default 0 |
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| 44 | |
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| 45 | rx_buf_en = hex2dec('0000000F'); % Default hex2dec('0000000F') |
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| 46 | tx_buf_en = hex2dec('0000000F'); % Default hex2dec('0000000F') |
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| 47 | end |
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| 48 | |
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| 49 | |
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| 50 | % ------------------------------------------------------------------------ |
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| 51 | % Buffer Configuration Register: |
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| 52 | % Register format: |
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| 53 | % [31:26] - Reserved |
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| 54 | % [25:24] - Scope data select |
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| 55 | % [23:21] - Reserved |
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| 56 | % [20] - Counter data select |
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| 57 | % [17] - TX Byte order |
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| 58 | % [16] - TX Word order |
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| 59 | % [17] - RX Byte order |
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| 60 | % [16] - RX Word order |
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| 61 | % [15:10] - Reserved |
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| 62 | % [ 9: 8] - RSSI clock select |
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| 63 | % [7] - AGC IQ select RFD |
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| 64 | % [6] - AGC IQ select RFC |
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| 65 | % [5] - AGC IQ select RFB |
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| 66 | % [4] - AGC IQ select RFA |
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| 67 | % [ 3: 2] - Reserved |
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| 68 | % [1] - Stop Tx |
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| 69 | % [0] - Continous Tx |
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| 70 | % |
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| 71 | if (simulation == 0) |
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| 72 | wl_buffers_config_init = 0; % Initialize the Config register to zero |
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| 73 | else |
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| 74 | wl_buffers_config_init = hex2dec('001A0100'); % Initialize the Config register to 0x001A0100 |
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| 75 | end |
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| 76 | |
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| 77 | |
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| 78 | % ------------------------------------------------------------------------ |
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| 79 | % Tx Delay Register: |
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| 80 | % Register format: |
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| 81 | % [31: 0] - Tx Delay |
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| 82 | % |
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| 83 | wl_buffers_tx_delay_init = 1000; % This will provide a Tx Delay of 1001 samples |
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| 84 | |
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| 85 | |
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| 86 | % ------------------------------------------------------------------------ |
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| 87 | % RF Buffer Select Register: |
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| 88 | % Register format: |
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| 89 | % [31:26] - Reserved |
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| 90 | % [25:24] - RFD buffer select |
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| 91 | % [23:18] - Reserved |
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| 92 | % [17:16] - RFC buffer select |
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| 93 | % [15:10] - Reserved |
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| 94 | % [ 9: 8] - RFB buffer select |
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| 95 | % [ 7: 2] - Reserved |
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| 96 | % [ 1: 0] - RFA buffer select |
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| 97 | % |
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| 98 | % RF* buffer select values: |
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| 99 | % 0 - RFA Tx buffer |
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| 100 | % 1 - RFB Tx buffer |
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| 101 | % 2 - RFC Tx buffer |
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| 102 | % 3 - RFD Tx buffer |
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| 103 | % |
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| 104 | wl_buffers_rf_buffer_sel = hex2dec('03020100'); % Select the buffer to use for the output |
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