source: ResearchApps/PHY/WARPLAB/WARPLab7/Sysgen_Reference/w3/warplab_trigger_proc/trig_idelay.v

Last change on this file was 4830, checked in by welsh, 7 years ago

Version 1.07.g - Output delays are now 16 bit for all outputs. Moved trigger input enables to register in IOB.

File size: 1.8 KB
Line 
1module trig_idelay (
2    input          idelay_clk,
3    input          idelay_rst,
4   
5    input          input_pin,
6    output reg     input_delayed,
7   
8    input [4:0]    delay_val,
9    input          update_delay
10);
11
12    wire trig_idelay_out;
13
14    initial begin
15        input_delayed = 0;
16    end
17   
18    IODELAYE1 #(
19      .CINVCTRL_SEL("FALSE"),          // Enable dynamic clock inversion ("TRUE"/"FALSE")
20      .DELAY_SRC("I"),                 // Delay input ("I", "CLKIN", "DATAIN", "IO", "O")
21      .HIGH_PERFORMANCE_MODE("TRUE"),  // Reduced jitter ("TRUE"), Reduced power ("FALSE")
22      .IDELAY_TYPE("VAR_LOADABLE"),    // "DEFAULT", "FIXED", "VARIABLE", or "VAR_LOADABLE"
23      .IDELAY_VALUE(0),                // Input delay tap setting (0-32)
24      .REFCLK_FREQUENCY(200.0),        // IDELAYCTRL clock input frequency in MHz
25      .SIGNAL_PATTERN("DATA")          // "DATA" or "CLOCK" input signal
26    )
27    IODELAYE1_inst (
28      .C(idelay_clk),                  // 1-bit input - Clock input
29     
30      .RST(update_delay),              // 1-bit input - Active high, synchronous reset, resets delay chain to IDELAY_VALUE/
31     
32      .CE(1'b0),                       // 1-bit input - Active high enable increment/decrement function
33     
34      .CINVCTRL(1'b0),                 // 1-bit input - Dynamically inverts the Clock (C) polarity
35      .CNTVALUEIN(delay_val),          // 5-bit input - Counter value for loadable counter application
36
37      .IDATAIN(input_pin),             // 1-bit input - Delay data input
38
39      .DATAOUT(trig_idelay_out)        // 1-bit output - Delayed data output
40    );
41   
42    //synthesis attribute IOB of input_delayed is true;
43    always @(posedge idelay_clk) begin
44        if (idelay_rst)
45            input_delayed <= 0;
46        else
47            input_delayed <= trig_idelay_out;
48    end
49endmodule
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