[4747] | 1 | module trig_idelays ( |
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[4830] | 2 | input clk, |
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| 3 | input ce, |
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| 4 | |
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| 5 | input [3:0] trigs_disable, |
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| 6 | input [3:0] trigs_in_pin, |
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| 7 | output [3:0] trigs_in_delayed, |
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[4747] | 8 | |
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[4830] | 9 | input [4:0] trig0_dly, |
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| 10 | input [4:0] trig1_dly, |
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| 11 | input [4:0] trig2_dly, |
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| 12 | input [4:0] trig3_dly, |
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[4747] | 13 | |
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[4830] | 14 | input update_delays |
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[4747] | 15 | ); |
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| 16 | |
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| 17 | trig_idelay trig0_idelay ( |
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[4830] | 18 | .idelay_clk(clk), |
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| 19 | .idelay_rst(trigs_disable[0]), |
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[4747] | 20 | .input_pin(trigs_in_pin[0]), |
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| 21 | .input_delayed(trigs_in_delayed[0]), |
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| 22 | .delay_val(trig0_dly), |
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[4830] | 23 | .update_delay(update_delays) |
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[4747] | 24 | ); |
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| 25 | |
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| 26 | trig_idelay trig1_idelay ( |
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[4830] | 27 | .idelay_clk(clk), |
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| 28 | .idelay_rst(trigs_disable[1]), |
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[4747] | 29 | .input_pin(trigs_in_pin[1]), |
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| 30 | .input_delayed(trigs_in_delayed[1]), |
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| 31 | .delay_val(trig1_dly), |
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[4830] | 32 | .update_delay(update_delays) |
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[4747] | 33 | ); |
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| 34 | |
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| 35 | trig_idelay trig2_idelay ( |
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[4830] | 36 | .idelay_clk(clk), |
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| 37 | .idelay_rst(trigs_disable[2]), |
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[4747] | 38 | .input_pin(trigs_in_pin[2]), |
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| 39 | .input_delayed(trigs_in_delayed[2]), |
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| 40 | .delay_val(trig2_dly), |
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[4830] | 41 | .update_delay(update_delays) |
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[4747] | 42 | ); |
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| 43 | |
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| 44 | trig_idelay trig3_idelay ( |
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[4830] | 45 | .idelay_clk(clk), |
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| 46 | .idelay_rst(trigs_disable[3]), |
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[4747] | 47 | .input_pin(trigs_in_pin[3]), |
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| 48 | .input_delayed(trigs_in_delayed[3]), |
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| 49 | .delay_val(trig3_dly), |
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[4830] | 50 | .update_delay(update_delays) |
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[4747] | 51 | ); |
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| 52 | |
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| 53 | endmodule |
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