source: ResearchApps/PHY/WARPLAB/WARPLab7/Sysgen_Reference/w3/warplab_trigger_proc/trig_idelays.v

Last change on this file was 4830, checked in by welsh, 7 years ago

Version 1.07.g - Output delays are now 16 bit for all outputs. Moved trigger input enables to register in IOB.

File size: 1.2 KB
Line 
1module trig_idelays (
2    input          clk,
3    input          ce,
4
5    input  [3:0]   trigs_disable,   
6    input  [3:0]   trigs_in_pin,
7    output [3:0]   trigs_in_delayed,
8   
9    input  [4:0]   trig0_dly,
10    input  [4:0]   trig1_dly,
11    input  [4:0]   trig2_dly,
12    input  [4:0]   trig3_dly,
13
14    input          update_delays
15);
16
17    trig_idelay trig0_idelay (
18        .idelay_clk(clk),
19        .idelay_rst(trigs_disable[0]),
20        .input_pin(trigs_in_pin[0]),
21        .input_delayed(trigs_in_delayed[0]),
22        .delay_val(trig0_dly),
23        .update_delay(update_delays)
24    );
25
26    trig_idelay trig1_idelay (
27        .idelay_clk(clk),
28        .idelay_rst(trigs_disable[1]),
29        .input_pin(trigs_in_pin[1]),
30        .input_delayed(trigs_in_delayed[1]),
31        .delay_val(trig1_dly),
32        .update_delay(update_delays)
33    );
34
35    trig_idelay trig2_idelay (
36        .idelay_clk(clk),
37        .idelay_rst(trigs_disable[2]),
38        .input_pin(trigs_in_pin[2]),
39        .input_delayed(trigs_in_delayed[2]),
40        .delay_val(trig2_dly),
41        .update_delay(update_delays)
42    );
43
44    trig_idelay trig3_idelay (
45        .idelay_clk(clk),
46        .idelay_rst(trigs_disable[3]),
47        .input_pin(trigs_in_pin[3]),
48        .input_delayed(trigs_in_delayed[3]),
49        .delay_val(trig3_dly),
50        .update_delay(update_delays)
51    );
52
53endmodule
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