source: ResearchApps/PHY/WARPLAB/WARPLab7/Sysgen_Reference/w3/warplab_trigger_proc/trig_odelay.v

Last change on this file was 4830, checked in by welsh, 8 years ago

Version 1.07.g - Output delays are now 16 bit for all outputs. Moved trigger input enables to register in IOB.

File size: 2.0 KB
Line 
1module trig_odelay (
2    input          odelay_clk,
3    input          odelay_rst,
4   
5    input          trig_output,
6    output         trig_output_delayed,
7   
8    input [4:0]    delay_val,
9    input          update_delay
10);
11
12    reg trig_output_reg;
13   
14    initial begin
15        trig_output_reg = 0;
16    end
17   
18    IODELAYE1 #(
19      .CINVCTRL_SEL("FALSE"),          // Enable dynamic clock inversion ("TRUE"/"FALSE")
20      .DELAY_SRC("O"),                 // Delay input ("I", "CLKIN", "DATAIN", "IO", "O")
21      .HIGH_PERFORMANCE_MODE("TRUE"),  // Reduced jitter ("TRUE"), Reduced power ("FALSE")
22      .ODELAY_TYPE("VAR_LOADABLE"),    // "DEFAULT", "FIXED", "VARIABLE", or "VAR_LOADABLE"
23      .ODELAY_VALUE(0),                // Input delay tap setting (0-32)
24      .REFCLK_FREQUENCY(200.0),        // IDELAYCTRL clock input frequency in MHz
25      .SIGNAL_PATTERN("DATA")          // "DATA" or "CLOCK" input signal
26    )
27    IODELAYE1_inst (
28      .C(odelay_clk),                  // 1-bit input - Clock input
29      .T(1'b0),                        // 1-bit input - 3-state input control port (1 - IDELAY, 0 - ODELAY)
30      .RST(update_delay),              // 1-bit input - Active high, synchronous reset, resets delay chain to IDELAY_VALUE/
31     
32      .CE(1'b0),                       // 1-bit input - Active high enable increment/decrement function
33     
34      .CINVCTRL(1'b0),                 // 1-bit input - Dynamically inverts the Clock (C) polarity
35      .CNTVALUEIN(delay_val),          // 5-bit input - Counter value for loadable counter application
36     
37      .ODATAIN(trig_output_reg),       // 1-bit input - Data input for the output datapath from the device
38     
39      .DATAOUT(trig_output_delayed)    // 1-bit output - Delayed data output
40    );
41   
42    // synthesis attribute IOB of trig_output_reg is true;
43    always @(posedge odelay_clk) begin
44        if (odelay_rst)
45            trig_output_reg <= 0;
46        else
47            trig_output_reg <= trig_output;
48    end
49endmodule
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