[4747] | 1 | module trig_odelay ( |
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[4830] | 2 | input odelay_clk, |
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| 3 | input odelay_rst, |
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| 4 | |
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| 5 | input trig_output, |
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| 6 | output trig_output_delayed, |
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[4747] | 7 | |
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[4830] | 8 | input [4:0] delay_val, |
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| 9 | input update_delay |
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[4747] | 10 | ); |
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| 11 | |
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[4751] | 12 | reg trig_output_reg; |
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[4747] | 13 | |
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[4830] | 14 | initial begin |
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| 15 | trig_output_reg = 0; |
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| 16 | end |
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| 17 | |
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[4750] | 18 | IODELAYE1 #( |
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[4747] | 19 | .CINVCTRL_SEL("FALSE"), // Enable dynamic clock inversion ("TRUE"/"FALSE") |
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[4799] | 20 | .DELAY_SRC("O"), // Delay input ("I", "CLKIN", "DATAIN", "IO", "O") |
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[4747] | 21 | .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE") |
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[4799] | 22 | .ODELAY_TYPE("VAR_LOADABLE"), // "DEFAULT", "FIXED", "VARIABLE", or "VAR_LOADABLE" |
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| 23 | .ODELAY_VALUE(0), // Input delay tap setting (0-32) |
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[4747] | 24 | .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz |
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| 25 | .SIGNAL_PATTERN("DATA") // "DATA" or "CLOCK" input signal |
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[4750] | 26 | ) |
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| 27 | IODELAYE1_inst ( |
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[4749] | 28 | .C(odelay_clk), // 1-bit input - Clock input |
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[4795] | 29 | .T(1'b0), // 1-bit input - 3-state input control port (1 - IDELAY, 0 - ODELAY) |
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[4750] | 30 | .RST(update_delay), // 1-bit input - Active high, synchronous reset, resets delay chain to IDELAY_VALUE/ |
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| 31 | |
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[4749] | 32 | .CE(1'b0), // 1-bit input - Active high enable increment/decrement function |
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[4750] | 33 | |
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[4749] | 34 | .CINVCTRL(1'b0), // 1-bit input - Dynamically inverts the Clock (C) polarity |
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| 35 | .CNTVALUEIN(delay_val), // 5-bit input - Counter value for loadable counter application |
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[4750] | 36 | |
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| 37 | .ODATAIN(trig_output_reg), // 1-bit input - Data input for the output datapath from the device |
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| 38 | |
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| 39 | .DATAOUT(trig_output_delayed) // 1-bit output - Delayed data output |
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| 40 | ); |
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[4747] | 41 | |
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[4830] | 42 | // synthesis attribute IOB of trig_output_reg is true; |
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| 43 | always @(posedge odelay_clk) begin |
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| 44 | if (odelay_rst) |
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| 45 | trig_output_reg <= 0; |
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| 46 | else |
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| 47 | trig_output_reg <= trig_output; |
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| 48 | end |
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[4747] | 49 | endmodule |
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