source: ResearchApps/PHY/WARPLAB/WARPLab7/Sysgen_Reference/w3/warplab_trigger_proc/trig_odelays.v

Last change on this file was 4830, checked in by welsh, 7 years ago

Version 1.07.g - Output delays are now 16 bit for all outputs. Moved trigger input enables to register in IOB.

File size: 1.2 KB
Line 
1module trig_odelays (
2    input          clk,
3    input          ce,
4   
5    input          trigs_disable,
6    input  [3:0]   trigs_in,
7    output [3:0]   trigs_out_pins,
8   
9    input  [4:0]   trig0_dly,
10    input  [4:0]   trig1_dly,
11    input  [4:0]   trig2_dly,
12    input  [4:0]   trig3_dly,
13
14    input          update_delays
15);
16
17    trig_odelay trig0_odelay (
18        .odelay_clk(clk),
19        .odelay_rst(trigs_disable),
20        .trig_output(trigs_in[0]),
21        .trig_output_delayed(trigs_out_pins[0]),
22        .delay_val(trig0_dly),
23        .update_delay(update_delays)
24    );
25
26    trig_odelay trig1_odelay (
27        .odelay_clk(clk),
28        .odelay_rst(trigs_disable),
29        .trig_output(trigs_in[1]),
30        .trig_output_delayed(trigs_out_pins[1]),
31        .delay_val(trig1_dly),
32        .update_delay(update_delays)
33    );
34
35    trig_odelay trig2_odelay (
36        .odelay_clk(clk),
37        .odelay_rst(trigs_disable),
38        .trig_output(trigs_in[2]),
39        .trig_output_delayed(trigs_out_pins[2]),
40        .delay_val(trig2_dly),
41        .update_delay(update_delays)
42    );
43
44    trig_odelay trig3_odelay (
45        .odelay_clk(clk),
46        .odelay_rst(trigs_disable),
47        .trig_output(trigs_in[3]),
48        .trig_output_delayed(trigs_out_pins[3]),
49        .delay_val(trig3_dly),
50        .update_delay(update_delays)
51    );
52
53endmodule
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